4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
39 select HAVE_ARCH_TRACEHOOK
41 select HAVE_CC_STACKPROTECTOR
42 select HAVE_CONTEXT_TRACKING
43 select HAVE_C_RECORDMCOUNT
44 select HAVE_DEBUG_KMEMLEAK
45 select HAVE_DMA_API_DEBUG
47 select HAVE_DMA_CONTIGUOUS if MMU
48 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
49 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
50 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
51 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
52 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
53 select HAVE_GENERIC_DMA_COHERENT
54 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
55 select HAVE_IDE if PCI || ISA || PCMCIA
56 select HAVE_IRQ_TIME_ACCOUNTING
57 select HAVE_KERNEL_GZIP
58 select HAVE_KERNEL_LZ4
59 select HAVE_KERNEL_LZMA
60 select HAVE_KERNEL_LZO
62 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
63 select HAVE_KRETPROBES if (HAVE_KPROBES)
65 select HAVE_MOD_ARCH_SPECIFIC
66 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
67 select HAVE_OPTPROBES if !THUMB2_KERNEL
68 select HAVE_PERF_EVENTS
70 select HAVE_PERF_USER_STACK_DUMP
71 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
72 select HAVE_REGS_AND_STACK_ACCESS_API
73 select HAVE_SYSCALL_TRACEPOINTS
75 select HAVE_VIRT_CPU_ACCOUNTING_GEN
76 select IRQ_FORCED_THREADING
77 select MODULES_USE_ELF_REL
80 select OLD_SIGSUSPEND3
81 select PERF_USE_VMALLOC
83 select SYS_SUPPORTS_APM_EMULATION
84 # Above selects are sorted alphabetically; please add new ones
85 # according to that. Thanks.
87 The ARM series is a line of low-power-consumption RISC chip designs
88 licensed by ARM Ltd and targeted at embedded applications and
89 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
90 manufactured, but legacy ARM-based PC hardware remains popular in
91 Europe. There is an ARM Linux project with a web page at
92 <http://www.arm.linux.org.uk/>.
94 config ARM_HAS_SG_CHAIN
95 select ARCH_HAS_SG_CHAIN
98 config NEED_SG_DMA_LENGTH
101 config ARM_DMA_USE_IOMMU
103 select ARM_HAS_SG_CHAIN
104 select NEED_SG_DMA_LENGTH
108 config ARM_DMA_IOMMU_ALIGNMENT
109 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
113 DMA mapping framework by default aligns all buffers to the smallest
114 PAGE_SIZE order which is greater than or equal to the requested buffer
115 size. This works well for buffers up to a few hundreds kilobytes, but
116 for larger buffers it just a waste of address space. Drivers which has
117 relatively small addressing window (like 64Mib) might run out of
118 virtual space with just a few allocations.
120 With this parameter you can specify the maximum PAGE_SIZE order for
121 DMA IOMMU buffers. Larger buffers will be aligned only to this
122 specified order. The order is expressed as a power of two multiplied
127 config MIGHT_HAVE_PCI
130 config SYS_SUPPORTS_APM_EMULATION
135 select GENERIC_ALLOCATOR
146 The Extended Industry Standard Architecture (EISA) bus was
147 developed as an open alternative to the IBM MicroChannel bus.
149 The EISA bus provided some of the features of the IBM MicroChannel
150 bus while maintaining backward compatibility with cards made for
151 the older ISA bus. The EISA bus saw limited use between 1988 and
152 1995 when it was made obsolete by the PCI bus.
154 Say Y here if you are building a kernel for an EISA-based machine.
161 config STACKTRACE_SUPPORT
165 config HAVE_LATENCYTOP_SUPPORT
170 config LOCKDEP_SUPPORT
174 config TRACE_IRQFLAGS_SUPPORT
178 config RWSEM_XCHGADD_ALGORITHM
182 config ARCH_HAS_ILOG2_U32
185 config ARCH_HAS_ILOG2_U64
188 config ARCH_HAS_BANDGAP
191 config FIX_EARLYCON_MEM
194 config GENERIC_HWEIGHT
198 config GENERIC_CALIBRATE_DELAY
202 config ARCH_MAY_HAVE_PC_FDC
208 config NEED_DMA_MAP_STATE
211 config ARCH_SUPPORTS_UPROBES
214 config ARCH_HAS_DMA_SET_COHERENT_MASK
217 config GENERIC_ISA_DMA
223 config NEED_RET_TO_USER
231 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
232 default DRAM_BASE if REMAP_VECTORS_TO_RAM
235 The base address of exception vectors. This must be two pages
238 config ARM_PATCH_PHYS_VIRT
239 bool "Patch physical to virtual translations at runtime" if EMBEDDED
241 depends on !XIP_KERNEL && MMU
242 depends on !ARCH_REALVIEW || !SPARSEMEM
244 Patch phys-to-virt and virt-to-phys translation functions at
245 boot and module load time according to the position of the
246 kernel in system memory.
248 This can only be used with non-XIP MMU kernels where the base
249 of physical memory is at a 16MB boundary.
251 Only disable this option if you know that you do not require
252 this feature (eg, building a kernel for a single machine) and
253 you need to shrink the kernel to the minimal size.
255 config NEED_MACH_IO_H
258 Select this when mach/io.h is required to provide special
259 definitions for this platform. The need for mach/io.h should
260 be avoided when possible.
262 config NEED_MACH_MEMORY_H
265 Select this when mach/memory.h is required to provide special
266 definitions for this platform. The need for mach/memory.h should
267 be avoided when possible.
270 hex "Physical address of main memory" if MMU
271 depends on !ARM_PATCH_PHYS_VIRT
272 default DRAM_BASE if !MMU
273 default 0x00000000 if ARCH_EBSA110 || \
278 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
279 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
280 default 0x20000000 if ARCH_S5PV210
281 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
282 default 0xc0000000 if ARCH_SA1100
284 Please provide the physical address corresponding to the
285 location of main memory in your system.
291 config PGTABLE_LEVELS
293 default 3 if ARM_LPAE
296 source "init/Kconfig"
298 source "kernel/Kconfig.freezer"
303 bool "MMU-based Paged Memory Management Support"
306 Select if you want MMU-based virtualised addressing space
307 support by paged memory management. If unsure, say 'Y'.
310 # The "ARM system type" choice list is ordered alphabetically by option
311 # text. Please add new entries in the option alphabetic order.
314 prompt "ARM system type"
315 default ARCH_VERSATILE if !MMU
316 default ARCH_MULTIPLATFORM if MMU
318 config ARCH_MULTIPLATFORM
319 bool "Allow multiple platforms to be selected"
321 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_HAS_SG_CHAIN
323 select ARM_PATCH_PHYS_VIRT
327 select GENERIC_CLOCKEVENTS
328 select MIGHT_HAVE_PCI
329 select MULTI_IRQ_HANDLER
333 config ARM_SINGLE_ARMV7M
334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select GENERIC_CLOCKEVENTS
348 bool "ARM Ltd. RealView family"
349 select ARCH_WANT_OPTIONAL_GPIOLIB
351 select ARM_TIMER_SP804
353 select COMMON_CLK_VERSATILE
354 select GENERIC_CLOCKEVENTS
355 select GPIO_PL061 if GPIOLIB
357 select NEED_MACH_MEMORY_H
358 select PLAT_VERSATILE
359 select PLAT_VERSATILE_SCHED_CLOCK
361 This enables support for ARM Ltd RealView boards.
363 config ARCH_VERSATILE
364 bool "ARM Ltd. Versatile family"
365 select ARCH_WANT_OPTIONAL_GPIOLIB
367 select ARM_TIMER_SP804
370 select GENERIC_CLOCKEVENTS
371 select HAVE_MACH_CLKDEV
373 select PLAT_VERSATILE
374 select PLAT_VERSATILE_CLOCK
375 select PLAT_VERSATILE_SCHED_CLOCK
376 select VERSATILE_FPGA_IRQ
378 This enables support for ARM Ltd Versatile board.
381 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
382 select ARCH_REQUIRE_GPIOLIB
387 select GENERIC_CLOCKEVENTS
391 Support for Cirrus Logic 711x/721x/731x based boards.
394 bool "Cortina Systems Gemini"
395 select ARCH_REQUIRE_GPIOLIB
398 select GENERIC_CLOCKEVENTS
400 Support for the Cortina Systems Gemini family SoCs
404 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
411 This is an evaluation board for the StrongARM processor available
412 from Digital. It has limited hardware on-board, including an
413 Ethernet interface, two PCMCIA sockets, two serial ports and a
418 select ARCH_HAS_HOLES_MEMORYMODEL
419 select ARCH_REQUIRE_GPIOLIB
421 select ARM_PATCH_PHYS_VIRT
427 select GENERIC_CLOCKEVENTS
429 This enables support for the Cirrus EP93xx series of CPUs.
431 config ARCH_FOOTBRIDGE
435 select GENERIC_CLOCKEVENTS
437 select NEED_MACH_IO_H if !MMU
438 select NEED_MACH_MEMORY_H
440 Support for systems based on the DC21285 companion chip
441 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
444 bool "Hilscher NetX based"
448 select GENERIC_CLOCKEVENTS
450 This enables support for systems based on the Hilscher NetX Soc
456 select NEED_MACH_MEMORY_H
457 select NEED_RET_TO_USER
463 Support for Intel's IOP13XX (XScale) family of processors.
468 select ARCH_REQUIRE_GPIOLIB
471 select NEED_RET_TO_USER
475 Support for Intel's 80219 and IOP32X (XScale) family of
481 select ARCH_REQUIRE_GPIOLIB
484 select NEED_RET_TO_USER
488 Support for Intel's IOP33X (XScale) family of processors.
493 select ARCH_HAS_DMA_SET_COHERENT_MASK
494 select ARCH_REQUIRE_GPIOLIB
495 select ARCH_SUPPORTS_BIG_ENDIAN
498 select DMABOUNCE if PCI
499 select GENERIC_CLOCKEVENTS
500 select MIGHT_HAVE_PCI
501 select NEED_MACH_IO_H
502 select USB_EHCI_BIG_ENDIAN_DESC
503 select USB_EHCI_BIG_ENDIAN_MMIO
505 Support for Intel's IXP4XX (XScale) family of processors.
509 select ARCH_REQUIRE_GPIOLIB
511 select GENERIC_CLOCKEVENTS
512 select MIGHT_HAVE_PCI
516 select PLAT_ORION_LEGACY
518 Support for the Marvell Dove SoC 88AP510
521 bool "Marvell MV78xx0"
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
527 select PLAT_ORION_LEGACY
529 Support for the following Marvell MV78xx0 series SoCs:
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
540 select PLAT_ORION_LEGACY
541 select MULTI_IRQ_HANDLER
543 Support for the following Marvell Orion 5x series SoCs:
544 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
545 Orion-2 (5281), Orion-1-90 (6183).
548 bool "Marvell PXA168/910/MMP2"
550 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_ALLOCATOR
553 select GENERIC_CLOCKEVENTS
556 select MULTI_IRQ_HANDLER
561 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
564 bool "Micrel/Kendin KS8695"
565 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
569 select NEED_MACH_MEMORY_H
571 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
572 System-on-Chip devices.
575 bool "Nuvoton W90X900 CPU"
576 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
582 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
583 At present, the w90x900 has been renamed nuc900, regarding
584 the ARM series product line, you can login the following
585 link address to know more.
587 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
588 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
592 select ARCH_REQUIRE_GPIOLIB
597 select GENERIC_CLOCKEVENTS
601 Support for the NXP LPC32XX family of processors
604 bool "PXA2xx/PXA3xx-based"
607 select ARCH_REQUIRE_GPIOLIB
608 select ARM_CPU_SUSPEND if PM
614 select GENERIC_CLOCKEVENTS
618 select MULTI_IRQ_HANDLER
622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
627 select ARCH_MAY_HAVE_PC_FDC
628 select ARCH_SPARSEMEM_ENABLE
629 select ARCH_USES_GETTIMEOFFSET
633 select HAVE_PATA_PLATFORM
635 select NEED_MACH_IO_H
636 select NEED_MACH_MEMORY_H
640 On the Acorn Risc-PC, Linux can support the internal IDE disk and
641 CD-ROM interface, serial and parallel port, and the floppy drive.
646 select ARCH_REQUIRE_GPIOLIB
647 select ARCH_SPARSEMEM_ENABLE
652 select GENERIC_CLOCKEVENTS
656 select MULTI_IRQ_HANDLER
657 select NEED_MACH_MEMORY_H
660 Support for StrongARM 11x0 based boards.
663 bool "Samsung S3C24XX SoCs"
664 select ARCH_REQUIRE_GPIOLIB
667 select CLKSRC_SAMSUNG_PWM
668 select GENERIC_CLOCKEVENTS
670 select HAVE_S3C2410_I2C if I2C
671 select HAVE_S3C2410_WATCHDOG if WATCHDOG
672 select HAVE_S3C_RTC if RTC_CLASS
673 select MULTI_IRQ_HANDLER
674 select NEED_MACH_IO_H
677 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
678 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
679 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
680 Samsung SMDK2410 development board (and derivatives).
683 bool "Samsung S3C64XX"
684 select ARCH_REQUIRE_GPIOLIB
689 select CLKSRC_SAMSUNG_PWM
690 select COMMON_CLK_SAMSUNG
692 select GENERIC_CLOCKEVENTS
694 select HAVE_S3C2410_I2C if I2C
695 select HAVE_S3C2410_WATCHDOG if WATCHDOG
699 select PM_GENERIC_DOMAINS if PM
701 select S3C_GPIO_TRACK
703 select SAMSUNG_WAKEMASK
704 select SAMSUNG_WDT_RESET
706 Samsung S3C64XX series based systems
710 select ARCH_HAS_HOLES_MEMORYMODEL
711 select ARCH_REQUIRE_GPIOLIB
713 select GENERIC_ALLOCATOR
714 select GENERIC_CLOCKEVENTS
715 select GENERIC_IRQ_CHIP
721 Support for TI's DaVinci platform.
726 select ARCH_HAS_HOLES_MEMORYMODEL
728 select ARCH_REQUIRE_GPIOLIB
731 select GENERIC_CLOCKEVENTS
732 select GENERIC_IRQ_CHIP
735 select MULTI_IRQ_HANDLER
736 select NEED_MACH_IO_H if PCCARD
737 select NEED_MACH_MEMORY_H
740 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
744 menu "Multiple platform selection"
745 depends on ARCH_MULTIPLATFORM
747 comment "CPU Core family selection"
750 bool "ARMv4 based platforms (FA526)"
751 depends on !ARCH_MULTI_V6_V7
752 select ARCH_MULTI_V4_V5
755 config ARCH_MULTI_V4T
756 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
757 depends on !ARCH_MULTI_V6_V7
758 select ARCH_MULTI_V4_V5
759 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
760 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
761 CPU_ARM925T || CPU_ARM940T)
764 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
765 depends on !ARCH_MULTI_V6_V7
766 select ARCH_MULTI_V4_V5
767 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
768 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
769 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
771 config ARCH_MULTI_V4_V5
775 bool "ARMv6 based platforms (ARM11)"
776 select ARCH_MULTI_V6_V7
780 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
782 select ARCH_MULTI_V6_V7
786 config ARCH_MULTI_V6_V7
788 select MIGHT_HAVE_CACHE_L2X0
790 config ARCH_MULTI_CPU_AUTO
791 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
797 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
801 select HAVE_ARM_ARCH_TIMER
804 # This is sorted alphabetically by mach-* pathname. However, plat-*
805 # Kconfigs may be included either alphabetically (according to the
806 # plat- suffix) or along side the corresponding mach-* source.
808 source "arch/arm/mach-mvebu/Kconfig"
810 source "arch/arm/mach-alpine/Kconfig"
812 source "arch/arm/mach-asm9260/Kconfig"
814 source "arch/arm/mach-at91/Kconfig"
816 source "arch/arm/mach-axxia/Kconfig"
818 source "arch/arm/mach-bcm/Kconfig"
820 source "arch/arm/mach-berlin/Kconfig"
822 source "arch/arm/mach-clps711x/Kconfig"
824 source "arch/arm/mach-cns3xxx/Kconfig"
826 source "arch/arm/mach-davinci/Kconfig"
828 source "arch/arm/mach-digicolor/Kconfig"
830 source "arch/arm/mach-dove/Kconfig"
832 source "arch/arm/mach-ep93xx/Kconfig"
834 source "arch/arm/mach-footbridge/Kconfig"
836 source "arch/arm/mach-gemini/Kconfig"
838 source "arch/arm/mach-highbank/Kconfig"
840 source "arch/arm/mach-hisi/Kconfig"
842 source "arch/arm/mach-integrator/Kconfig"
844 source "arch/arm/mach-iop32x/Kconfig"
846 source "arch/arm/mach-iop33x/Kconfig"
848 source "arch/arm/mach-iop13xx/Kconfig"
850 source "arch/arm/mach-ixp4xx/Kconfig"
852 source "arch/arm/mach-keystone/Kconfig"
854 source "arch/arm/mach-ks8695/Kconfig"
856 source "arch/arm/mach-meson/Kconfig"
858 source "arch/arm/mach-moxart/Kconfig"
860 source "arch/arm/mach-mv78xx0/Kconfig"
862 source "arch/arm/mach-imx/Kconfig"
864 source "arch/arm/mach-mediatek/Kconfig"
866 source "arch/arm/mach-mxs/Kconfig"
868 source "arch/arm/mach-netx/Kconfig"
870 source "arch/arm/mach-nomadik/Kconfig"
872 source "arch/arm/mach-nspire/Kconfig"
874 source "arch/arm/plat-omap/Kconfig"
876 source "arch/arm/mach-omap1/Kconfig"
878 source "arch/arm/mach-omap2/Kconfig"
880 source "arch/arm/mach-orion5x/Kconfig"
882 source "arch/arm/mach-picoxcell/Kconfig"
884 source "arch/arm/mach-pxa/Kconfig"
885 source "arch/arm/plat-pxa/Kconfig"
887 source "arch/arm/mach-mmp/Kconfig"
889 source "arch/arm/mach-qcom/Kconfig"
891 source "arch/arm/mach-realview/Kconfig"
893 source "arch/arm/mach-rockchip/Kconfig"
895 source "arch/arm/mach-sa1100/Kconfig"
897 source "arch/arm/mach-socfpga/Kconfig"
899 source "arch/arm/mach-spear/Kconfig"
901 source "arch/arm/mach-sti/Kconfig"
903 source "arch/arm/mach-s3c24xx/Kconfig"
905 source "arch/arm/mach-s3c64xx/Kconfig"
907 source "arch/arm/mach-s5pv210/Kconfig"
909 source "arch/arm/mach-exynos/Kconfig"
910 source "arch/arm/plat-samsung/Kconfig"
912 source "arch/arm/mach-shmobile/Kconfig"
914 source "arch/arm/mach-sunxi/Kconfig"
916 source "arch/arm/mach-prima2/Kconfig"
918 source "arch/arm/mach-tegra/Kconfig"
920 source "arch/arm/mach-u300/Kconfig"
922 source "arch/arm/mach-uniphier/Kconfig"
924 source "arch/arm/mach-ux500/Kconfig"
926 source "arch/arm/mach-versatile/Kconfig"
928 source "arch/arm/mach-vexpress/Kconfig"
929 source "arch/arm/plat-versatile/Kconfig"
931 source "arch/arm/mach-vt8500/Kconfig"
933 source "arch/arm/mach-w90x900/Kconfig"
935 source "arch/arm/mach-zx/Kconfig"
937 source "arch/arm/mach-zynq/Kconfig"
939 # ARMv7-M architecture
941 bool "Energy Micro efm32"
942 depends on ARM_SINGLE_ARMV7M
943 select ARCH_REQUIRE_GPIOLIB
945 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
949 bool "NXP LPC18xx/LPC43xx"
950 depends on ARM_SINGLE_ARMV7M
951 select ARCH_HAS_RESET_CONTROLLER
953 select CLKSRC_LPC32XX
956 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
957 high performance microcontrollers.
960 bool "STMicrolectronics STM32"
961 depends on ARM_SINGLE_ARMV7M
962 select ARCH_HAS_RESET_CONTROLLER
963 select ARMV7M_SYSTICK
965 select RESET_CONTROLLER
967 Support for STMicroelectronics STM32 processors.
969 # Definitions to make life easier
975 select GENERIC_CLOCKEVENTS
981 select GENERIC_IRQ_CHIP
984 config PLAT_ORION_LEGACY
991 config PLAT_VERSATILE
994 source "arch/arm/firmware/Kconfig"
996 source arch/arm/mm/Kconfig
999 bool "Enable iWMMXt support"
1000 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1001 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1003 Enable support for iWMMXt context switching at run time if
1004 running on a CPU that supports it.
1006 config MULTI_IRQ_HANDLER
1009 Allow each machine to specify it's own IRQ handler at run time.
1012 source "arch/arm/Kconfig-nommu"
1015 config PJ4B_ERRATA_4742
1016 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1017 depends on CPU_PJ4B && MACH_ARMADA_370
1020 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1021 Event (WFE) IDLE states, a specific timing sensitivity exists between
1022 the retiring WFI/WFE instructions and the newly issued subsequent
1023 instructions. This sensitivity can result in a CPU hang scenario.
1025 The software must insert either a Data Synchronization Barrier (DSB)
1026 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1029 config ARM_ERRATA_326103
1030 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1033 Executing a SWP instruction to read-only memory does not set bit 11
1034 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1035 treat the access as a read, preventing a COW from occurring and
1036 causing the faulting task to livelock.
1038 config ARM_ERRATA_411920
1039 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1040 depends on CPU_V6 || CPU_V6K
1042 Invalidation of the Instruction Cache operation can
1043 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1044 It does not affect the MPCore. This option enables the ARM Ltd.
1045 recommended workaround.
1047 config ARM_ERRATA_430973
1048 bool "ARM errata: Stale prediction on replaced interworking branch"
1051 This option enables the workaround for the 430973 Cortex-A8
1052 r1p* erratum. If a code sequence containing an ARM/Thumb
1053 interworking branch is replaced with another code sequence at the
1054 same virtual address, whether due to self-modifying code or virtual
1055 to physical address re-mapping, Cortex-A8 does not recover from the
1056 stale interworking branch prediction. This results in Cortex-A8
1057 executing the new code sequence in the incorrect ARM or Thumb state.
1058 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1059 and also flushes the branch target cache at every context switch.
1060 Note that setting specific bits in the ACTLR register may not be
1061 available in non-secure mode.
1063 config ARM_ERRATA_458693
1064 bool "ARM errata: Processor deadlock when a false hazard is created"
1066 depends on !ARCH_MULTIPLATFORM
1068 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1069 erratum. For very specific sequences of memory operations, it is
1070 possible for a hazard condition intended for a cache line to instead
1071 be incorrectly associated with a different cache line. This false
1072 hazard might then cause a processor deadlock. The workaround enables
1073 the L1 caching of the NEON accesses and disables the PLD instruction
1074 in the ACTLR register. Note that setting specific bits in the ACTLR
1075 register may not be available in non-secure mode.
1077 config ARM_ERRATA_460075
1078 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1080 depends on !ARCH_MULTIPLATFORM
1082 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1083 erratum. Any asynchronous access to the L2 cache may encounter a
1084 situation in which recent store transactions to the L2 cache are lost
1085 and overwritten with stale memory contents from external memory. The
1086 workaround disables the write-allocate mode for the L2 cache via the
1087 ACTLR register. Note that setting specific bits in the ACTLR register
1088 may not be available in non-secure mode.
1090 config ARM_ERRATA_742230
1091 bool "ARM errata: DMB operation may be faulty"
1092 depends on CPU_V7 && SMP
1093 depends on !ARCH_MULTIPLATFORM
1095 This option enables the workaround for the 742230 Cortex-A9
1096 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1097 between two write operations may not ensure the correct visibility
1098 ordering of the two writes. This workaround sets a specific bit in
1099 the diagnostic register of the Cortex-A9 which causes the DMB
1100 instruction to behave as a DSB, ensuring the correct behaviour of
1103 config ARM_ERRATA_742231
1104 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1105 depends on CPU_V7 && SMP
1106 depends on !ARCH_MULTIPLATFORM
1108 This option enables the workaround for the 742231 Cortex-A9
1109 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1110 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1111 accessing some data located in the same cache line, may get corrupted
1112 data due to bad handling of the address hazard when the line gets
1113 replaced from one of the CPUs at the same time as another CPU is
1114 accessing it. This workaround sets specific bits in the diagnostic
1115 register of the Cortex-A9 which reduces the linefill issuing
1116 capabilities of the processor.
1118 config ARM_ERRATA_643719
1119 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1120 depends on CPU_V7 && SMP
1123 This option enables the workaround for the 643719 Cortex-A9 (prior to
1124 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1125 register returns zero when it should return one. The workaround
1126 corrects this value, ensuring cache maintenance operations which use
1127 it behave as intended and avoiding data corruption.
1129 config ARM_ERRATA_720789
1130 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1133 This option enables the workaround for the 720789 Cortex-A9 (prior to
1134 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1135 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1136 As a consequence of this erratum, some TLB entries which should be
1137 invalidated are not, resulting in an incoherency in the system page
1138 tables. The workaround changes the TLB flushing routines to invalidate
1139 entries regardless of the ASID.
1141 config ARM_ERRATA_743622
1142 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1144 depends on !ARCH_MULTIPLATFORM
1146 This option enables the workaround for the 743622 Cortex-A9
1147 (r2p*) erratum. Under very rare conditions, a faulty
1148 optimisation in the Cortex-A9 Store Buffer may lead to data
1149 corruption. This workaround sets a specific bit in the diagnostic
1150 register of the Cortex-A9 which disables the Store Buffer
1151 optimisation, preventing the defect from occurring. This has no
1152 visible impact on the overall performance or power consumption of the
1155 config ARM_ERRATA_751472
1156 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1158 depends on !ARCH_MULTIPLATFORM
1160 This option enables the workaround for the 751472 Cortex-A9 (prior
1161 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1162 completion of a following broadcasted operation if the second
1163 operation is received by a CPU before the ICIALLUIS has completed,
1164 potentially leading to corrupted entries in the cache or TLB.
1166 config ARM_ERRATA_754322
1167 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1170 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1171 r3p*) erratum. A speculative memory access may cause a page table walk
1172 which starts prior to an ASID switch but completes afterwards. This
1173 can populate the micro-TLB with a stale entry which may be hit with
1174 the new ASID. This workaround places two dsb instructions in the mm
1175 switching code so that no page table walks can cross the ASID switch.
1177 config ARM_ERRATA_754327
1178 bool "ARM errata: no automatic Store Buffer drain"
1179 depends on CPU_V7 && SMP
1181 This option enables the workaround for the 754327 Cortex-A9 (prior to
1182 r2p0) erratum. The Store Buffer does not have any automatic draining
1183 mechanism and therefore a livelock may occur if an external agent
1184 continuously polls a memory location waiting to observe an update.
1185 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1186 written polling loops from denying visibility of updates to memory.
1188 config ARM_ERRATA_364296
1189 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1192 This options enables the workaround for the 364296 ARM1136
1193 r0p2 erratum (possible cache data corruption with
1194 hit-under-miss enabled). It sets the undocumented bit 31 in
1195 the auxiliary control register and the FI bit in the control
1196 register, thus disabling hit-under-miss without putting the
1197 processor into full low interrupt latency mode. ARM11MPCore
1200 config ARM_ERRATA_764369
1201 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1202 depends on CPU_V7 && SMP
1204 This option enables the workaround for erratum 764369
1205 affecting Cortex-A9 MPCore with two or more processors (all
1206 current revisions). Under certain timing circumstances, a data
1207 cache line maintenance operation by MVA targeting an Inner
1208 Shareable memory region may fail to proceed up to either the
1209 Point of Coherency or to the Point of Unification of the
1210 system. This workaround adds a DSB instruction before the
1211 relevant cache maintenance functions and sets a specific bit
1212 in the diagnostic control register of the SCU.
1214 config ARM_ERRATA_775420
1215 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1218 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1219 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1220 operation aborts with MMU exception, it might cause the processor
1221 to deadlock. This workaround puts DSB before executing ISB if
1222 an abort may occur on cache maintenance.
1224 config ARM_ERRATA_798181
1225 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1226 depends on CPU_V7 && SMP
1228 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1229 adequately shooting down all use of the old entries. This
1230 option enables the Linux kernel workaround for this erratum
1231 which sends an IPI to the CPUs that are running the same ASID
1232 as the one being invalidated.
1234 config ARM_ERRATA_773022
1235 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1238 This option enables the workaround for the 773022 Cortex-A15
1239 (up to r0p4) erratum. In certain rare sequences of code, the
1240 loop buffer may deliver incorrect instructions. This
1241 workaround disables the loop buffer to avoid the erratum.
1245 source "arch/arm/common/Kconfig"
1252 Find out whether you have ISA slots on your motherboard. ISA is the
1253 name of a bus system, i.e. the way the CPU talks to the other stuff
1254 inside your box. Other bus systems are PCI, EISA, MicroChannel
1255 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1256 newer boards don't support it. If you have ISA, say Y, otherwise N.
1258 # Select ISA DMA controller support
1263 # Select ISA DMA interface
1268 bool "PCI support" if MIGHT_HAVE_PCI
1270 Find out whether you have a PCI motherboard. PCI is the name of a
1271 bus system, i.e. the way the CPU talks to the other stuff inside
1272 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1273 VESA. If you have PCI, say Y, otherwise N.
1279 config PCI_DOMAINS_GENERIC
1280 def_bool PCI_DOMAINS
1282 config PCI_NANOENGINE
1283 bool "BSE nanoEngine PCI support"
1284 depends on SA1100_NANOENGINE
1286 Enable PCI on the BSE nanoEngine board.
1291 config PCI_HOST_ITE8152
1293 depends on PCI && MACH_ARMCORE
1297 source "drivers/pci/Kconfig"
1298 source "drivers/pci/pcie/Kconfig"
1300 source "drivers/pcmcia/Kconfig"
1304 menu "Kernel Features"
1309 This option should be selected by machines which have an SMP-
1312 The only effect of this option is to make the SMP-related
1313 options available to the user for configuration.
1316 bool "Symmetric Multi-Processing"
1317 depends on CPU_V6K || CPU_V7
1318 depends on GENERIC_CLOCKEVENTS
1320 depends on MMU || ARM_MPU
1323 This enables support for systems with more than one CPU. If you have
1324 a system with only one CPU, say N. If you have a system with more
1325 than one CPU, say Y.
1327 If you say N here, the kernel will run on uni- and multiprocessor
1328 machines, but will use only one CPU of a multiprocessor machine. If
1329 you say Y here, the kernel will run on many, but not all,
1330 uniprocessor machines. On a uniprocessor machine, the kernel
1331 will run faster if you say N here.
1333 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1334 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1335 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1337 If you don't know what to do here, say N.
1340 bool "Allow booting SMP kernel on uniprocessor systems"
1341 depends on SMP && !XIP_KERNEL && MMU
1344 SMP kernels contain instructions which fail on non-SMP processors.
1345 Enabling this option allows the kernel to modify itself to make
1346 these instructions safe. Disabling it allows about 1K of space
1349 If you don't know what to do here, say Y.
1351 config ARM_CPU_TOPOLOGY
1352 bool "Support cpu topology definition"
1353 depends on SMP && CPU_V7
1356 Support ARM cpu topology definition. The MPIDR register defines
1357 affinity between processors which is then used to describe the cpu
1358 topology of an ARM System.
1361 bool "Multi-core scheduler support"
1362 depends on ARM_CPU_TOPOLOGY
1364 Multi-core scheduler support improves the CPU scheduler's decision
1365 making when dealing with multi-core CPU chips at a cost of slightly
1366 increased overhead in some places. If unsure say N here.
1369 bool "SMT scheduler support"
1370 depends on ARM_CPU_TOPOLOGY
1372 Improves the CPU scheduler's decision making when dealing with
1373 MultiThreading at a cost of slightly increased overhead in some
1374 places. If unsure say N here.
1379 This option enables support for the ARM system coherency unit
1381 config HAVE_ARM_ARCH_TIMER
1382 bool "Architected timer support"
1384 select ARM_ARCH_TIMER
1385 select GENERIC_CLOCKEVENTS
1387 This option enables support for the ARM architected timer
1392 select CLKSRC_OF if OF
1394 This options enables support for the ARM timer and watchdog unit
1397 bool "Multi-Cluster Power Management"
1398 depends on CPU_V7 && SMP
1400 This option provides the common power management infrastructure
1401 for (multi-)cluster based systems, such as big.LITTLE based
1404 config MCPM_QUAD_CLUSTER
1408 To avoid wasting resources unnecessarily, MCPM only supports up
1409 to 2 clusters by default.
1410 Platforms with 3 or 4 clusters that use MCPM must select this
1411 option to allow the additional clusters to be managed.
1414 bool "big.LITTLE support (Experimental)"
1415 depends on CPU_V7 && SMP
1418 This option enables support selections for the big.LITTLE
1419 system architecture.
1422 bool "big.LITTLE switcher support"
1423 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1424 select ARM_CPU_SUSPEND
1427 The big.LITTLE "switcher" provides the core functionality to
1428 transparently handle transition between a cluster of A15's
1429 and a cluster of A7's in a big.LITTLE system.
1431 config BL_SWITCHER_DUMMY_IF
1432 tristate "Simple big.LITTLE switcher user interface"
1433 depends on BL_SWITCHER && DEBUG_KERNEL
1435 This is a simple and dummy char dev interface to control
1436 the big.LITTLE switcher core code. It is meant for
1437 debugging purposes only.
1440 prompt "Memory split"
1444 Select the desired split between kernel and user memory.
1446 If you are not absolutely sure what you are doing, leave this
1450 bool "3G/1G user/kernel split"
1452 bool "2G/2G user/kernel split"
1454 bool "1G/3G user/kernel split"
1459 default PHYS_OFFSET if !MMU
1460 default 0x40000000 if VMSPLIT_1G
1461 default 0x80000000 if VMSPLIT_2G
1465 int "Maximum number of CPUs (2-32)"
1471 bool "Support for hot-pluggable CPUs"
1474 Say Y here to experiment with turning CPUs off and on. CPUs
1475 can be controlled through /sys/devices/system/cpu.
1478 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1482 Say Y here if you want Linux to communicate with system firmware
1483 implementing the PSCI specification for CPU-centric power
1484 management operations described in ARM document number ARM DEN
1485 0022A ("Power State Coordination Interface System Software on
1488 # The GPIO number here must be sorted by descending number. In case of
1489 # a multiplatform kernel, we just want the highest value required by the
1490 # selected platforms.
1493 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1495 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1496 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1497 default 416 if ARCH_SUNXI
1498 default 392 if ARCH_U8500
1499 default 352 if ARCH_VT8500
1500 default 288 if ARCH_ROCKCHIP
1501 default 264 if MACH_H4700
1504 Maximum number of GPIOs in the system.
1506 If unsure, leave the default value.
1508 source kernel/Kconfig.preempt
1512 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1513 ARCH_S5PV210 || ARCH_EXYNOS4
1514 default 128 if SOC_AT91RM9200
1518 depends on HZ_FIXED = 0
1519 prompt "Timer frequency"
1543 default HZ_FIXED if HZ_FIXED != 0
1544 default 100 if HZ_100
1545 default 200 if HZ_200
1546 default 250 if HZ_250
1547 default 300 if HZ_300
1548 default 500 if HZ_500
1552 def_bool HIGH_RES_TIMERS
1554 config THUMB2_KERNEL
1555 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1556 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1557 default y if CPU_THUMBONLY
1559 select ARM_ASM_UNIFIED
1562 By enabling this option, the kernel will be compiled in
1563 Thumb-2 mode. A compiler/assembler that understand the unified
1564 ARM-Thumb syntax is needed.
1568 config THUMB2_AVOID_R_ARM_THM_JUMP11
1569 bool "Work around buggy Thumb-2 short branch relocations in gas"
1570 depends on THUMB2_KERNEL && MODULES
1573 Various binutils versions can resolve Thumb-2 branches to
1574 locally-defined, preemptible global symbols as short-range "b.n"
1575 branch instructions.
1577 This is a problem, because there's no guarantee the final
1578 destination of the symbol, or any candidate locations for a
1579 trampoline, are within range of the branch. For this reason, the
1580 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1581 relocation in modules at all, and it makes little sense to add
1584 The symptom is that the kernel fails with an "unsupported
1585 relocation" error when loading some modules.
1587 Until fixed tools are available, passing
1588 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1589 code which hits this problem, at the cost of a bit of extra runtime
1590 stack usage in some cases.
1592 The problem is described in more detail at:
1593 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1595 Only Thumb-2 kernels are affected.
1597 Unless you are sure your tools don't have this problem, say Y.
1599 config ARM_ASM_UNIFIED
1603 bool "Use the ARM EABI to compile the kernel"
1605 This option allows for the kernel to be compiled using the latest
1606 ARM ABI (aka EABI). This is only useful if you are using a user
1607 space environment that is also compiled with EABI.
1609 Since there are major incompatibilities between the legacy ABI and
1610 EABI, especially with regard to structure member alignment, this
1611 option also changes the kernel syscall calling convention to
1612 disambiguate both ABIs and allow for backward compatibility support
1613 (selected with CONFIG_OABI_COMPAT).
1615 To use this you need GCC version 4.0.0 or later.
1618 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1619 depends on AEABI && !THUMB2_KERNEL
1621 This option preserves the old syscall interface along with the
1622 new (ARM EABI) one. It also provides a compatibility layer to
1623 intercept syscalls that have structure arguments which layout
1624 in memory differs between the legacy ABI and the new ARM EABI
1625 (only for non "thumb" binaries). This option adds a tiny
1626 overhead to all syscalls and produces a slightly larger kernel.
1628 The seccomp filter system will not be available when this is
1629 selected, since there is no way yet to sensibly distinguish
1630 between calling conventions during filtering.
1632 If you know you'll be using only pure EABI user space then you
1633 can say N here. If this option is not selected and you attempt
1634 to execute a legacy ABI binary then the result will be
1635 UNPREDICTABLE (in fact it can be predicted that it won't work
1636 at all). If in doubt say N.
1638 config ARCH_HAS_HOLES_MEMORYMODEL
1641 config ARCH_SPARSEMEM_ENABLE
1644 config ARCH_SPARSEMEM_DEFAULT
1645 def_bool ARCH_SPARSEMEM_ENABLE
1647 config ARCH_SELECT_MEMORY_MODEL
1648 def_bool ARCH_SPARSEMEM_ENABLE
1650 config HAVE_ARCH_PFN_VALID
1651 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1653 config HAVE_GENERIC_RCU_GUP
1658 bool "High Memory Support"
1661 The address space of ARM processors is only 4 Gigabytes large
1662 and it has to accommodate user address space, kernel address
1663 space as well as some memory mapped IO. That means that, if you
1664 have a large amount of physical memory and/or IO, not all of the
1665 memory can be "permanently mapped" by the kernel. The physical
1666 memory that is not permanently mapped is called "high memory".
1668 Depending on the selected kernel/user memory split, minimum
1669 vmalloc space and actual amount of RAM, you may not need this
1670 option which should result in a slightly faster kernel.
1675 bool "Allocate 2nd-level pagetables from highmem"
1678 The VM uses one page of physical memory for each page table.
1679 For systems with a lot of processes, this can use a lot of
1680 precious low memory, eventually leading to low memory being
1681 consumed by page tables. Setting this option will allow
1682 user-space 2nd level page tables to reside in high memory.
1684 config CPU_SW_DOMAIN_PAN
1685 bool "Enable use of CPU domains to implement privileged no-access"
1686 depends on MMU && !ARM_LPAE
1689 Increase kernel security by ensuring that normal kernel accesses
1690 are unable to access userspace addresses. This can help prevent
1691 use-after-free bugs becoming an exploitable privilege escalation
1692 by ensuring that magic values (such as LIST_POISON) will always
1693 fault when dereferenced.
1695 CPUs with low-vector mappings use a best-efforts implementation.
1696 Their lower 1MB needs to remain accessible for the vectors, but
1697 the remainder of userspace will become appropriately inaccessible.
1699 config HW_PERF_EVENTS
1703 config SYS_SUPPORTS_HUGETLBFS
1707 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1711 config ARCH_WANT_GENERAL_HUGETLB
1714 config ARM_MODULE_PLTS
1715 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1718 Allocate PLTs when loading modules so that jumps and calls whose
1719 targets are too far away for their relative offsets to be encoded
1720 in the instructions themselves can be bounced via veneers in the
1721 module's PLT. This allows modules to be allocated in the generic
1722 vmalloc area after the dedicated module memory area has been
1723 exhausted. The modules will use slightly more memory, but after
1724 rounding up to page size, the actual memory footprint is usually
1727 Say y if you are getting out of memory errors while loading modules
1731 config FORCE_MAX_ZONEORDER
1732 int "Maximum zone order"
1733 default "12" if SOC_AM33XX
1734 default "9" if SA1111 || ARCH_EFM32
1737 The kernel memory allocator divides physically contiguous memory
1738 blocks into "zones", where each zone is a power of two number of
1739 pages. This option selects the largest power of two that the kernel
1740 keeps in the memory allocator. If you need to allocate very large
1741 blocks of physically contiguous memory, then you may need to
1742 increase this value.
1744 This config option is actually maximum order plus one. For example,
1745 a value of 11 means that the largest free memory block is 2^10 pages.
1747 config ALIGNMENT_TRAP
1749 depends on CPU_CP15_MMU
1750 default y if !ARCH_EBSA110
1751 select HAVE_PROC_CPU if PROC_FS
1753 ARM processors cannot fetch/store information which is not
1754 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1755 address divisible by 4. On 32-bit ARM processors, these non-aligned
1756 fetch/store instructions will be emulated in software if you say
1757 here, which has a severe performance impact. This is necessary for
1758 correct operation of some network protocols. With an IP-only
1759 configuration it is safe to say N, otherwise say Y.
1761 config UACCESS_WITH_MEMCPY
1762 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1764 default y if CPU_FEROCEON
1766 Implement faster copy_to_user and clear_user methods for CPU
1767 cores where a 8-word STM instruction give significantly higher
1768 memory write throughput than a sequence of individual 32bit stores.
1770 A possible side effect is a slight increase in scheduling latency
1771 between threads sharing the same address space if they invoke
1772 such copy operations with large buffers.
1774 However, if the CPU data cache is using a write-allocate mode,
1775 this option is unlikely to provide any performance gain.
1779 prompt "Enable seccomp to safely compute untrusted bytecode"
1781 This kernel feature is useful for number crunching applications
1782 that may need to compute untrusted bytecode during their
1783 execution. By using pipes or other transports made available to
1784 the process as file descriptors supporting the read/write
1785 syscalls, it's possible to isolate those applications in
1786 their own address space using seccomp. Once seccomp is
1787 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1788 and the task is only allowed to execute a few safe syscalls
1789 defined by each seccomp mode.
1802 bool "Xen guest support on ARM"
1803 depends on ARM && AEABI && OF
1804 depends on CPU_V7 && !CPU_V6
1805 depends on !GENERIC_ATOMIC64
1807 select ARCH_DMA_ADDR_T_64BIT
1811 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1818 bool "Flattened Device Tree support"
1821 select OF_EARLY_FLATTREE
1822 select OF_RESERVED_MEM
1824 Include support for flattened device tree machine descriptions.
1827 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1830 This is the traditional way of passing data to the kernel at boot
1831 time. If you are solely relying on the flattened device tree (or
1832 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1833 to remove ATAGS support from your kernel binary. If unsure,
1836 config DEPRECATED_PARAM_STRUCT
1837 bool "Provide old way to pass kernel parameters"
1840 This was deprecated in 2001 and announced to live on for 5 years.
1841 Some old boot loaders still use this way.
1843 # Compressed boot loader in ROM. Yes, we really want to ask about
1844 # TEXT and BSS so we preserve their values in the config files.
1845 config ZBOOT_ROM_TEXT
1846 hex "Compressed ROM boot loader base address"
1849 The physical address at which the ROM-able zImage is to be
1850 placed in the target. Platforms which normally make use of
1851 ROM-able zImage formats normally set this to a suitable
1852 value in their defconfig file.
1854 If ZBOOT_ROM is not enabled, this has no effect.
1856 config ZBOOT_ROM_BSS
1857 hex "Compressed ROM boot loader BSS address"
1860 The base address of an area of read/write memory in the target
1861 for the ROM-able zImage which must be available while the
1862 decompressor is running. It must be large enough to hold the
1863 entire decompressed kernel plus an additional 128 KiB.
1864 Platforms which normally make use of ROM-able zImage formats
1865 normally set this to a suitable value in their defconfig file.
1867 If ZBOOT_ROM is not enabled, this has no effect.
1870 bool "Compressed boot loader in ROM/flash"
1871 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1872 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1874 Say Y here if you intend to execute your compressed kernel image
1875 (zImage) directly from ROM or flash. If unsure, say N.
1877 config ARM_APPENDED_DTB
1878 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1881 With this option, the boot code will look for a device tree binary
1882 (DTB) appended to zImage
1883 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1885 This is meant as a backward compatibility convenience for those
1886 systems with a bootloader that can't be upgraded to accommodate
1887 the documented boot protocol using a device tree.
1889 Beware that there is very little in terms of protection against
1890 this option being confused by leftover garbage in memory that might
1891 look like a DTB header after a reboot if no actual DTB is appended
1892 to zImage. Do not leave this option active in a production kernel
1893 if you don't intend to always append a DTB. Proper passing of the
1894 location into r2 of a bootloader provided DTB is always preferable
1897 config ARM_ATAG_DTB_COMPAT
1898 bool "Supplement the appended DTB with traditional ATAG information"
1899 depends on ARM_APPENDED_DTB
1901 Some old bootloaders can't be updated to a DTB capable one, yet
1902 they provide ATAGs with memory configuration, the ramdisk address,
1903 the kernel cmdline string, etc. Such information is dynamically
1904 provided by the bootloader and can't always be stored in a static
1905 DTB. To allow a device tree enabled kernel to be used with such
1906 bootloaders, this option allows zImage to extract the information
1907 from the ATAG list and store it at run time into the appended DTB.
1910 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1911 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1913 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1914 bool "Use bootloader kernel arguments if available"
1916 Uses the command-line options passed by the boot loader instead of
1917 the device tree bootargs property. If the boot loader doesn't provide
1918 any, the device tree bootargs property will be used.
1920 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1921 bool "Extend with bootloader kernel arguments"
1923 The command-line arguments provided by the boot loader will be
1924 appended to the the device tree bootargs property.
1929 string "Default kernel command string"
1932 On some architectures (EBSA110 and CATS), there is currently no way
1933 for the boot loader to pass arguments to the kernel. For these
1934 architectures, you should supply some command-line options at build
1935 time by entering them here. As a minimum, you should specify the
1936 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1939 prompt "Kernel command line type" if CMDLINE != ""
1940 default CMDLINE_FROM_BOOTLOADER
1943 config CMDLINE_FROM_BOOTLOADER
1944 bool "Use bootloader kernel arguments if available"
1946 Uses the command-line options passed by the boot loader. If
1947 the boot loader doesn't provide any, the default kernel command
1948 string provided in CMDLINE will be used.
1950 config CMDLINE_EXTEND
1951 bool "Extend bootloader kernel arguments"
1953 The command-line arguments provided by the boot loader will be
1954 appended to the default kernel command string.
1956 config CMDLINE_FORCE
1957 bool "Always use the default kernel command string"
1959 Always use the default kernel command string, even if the boot
1960 loader passes other arguments to the kernel.
1961 This is useful if you cannot or don't want to change the
1962 command-line options your boot loader passes to the kernel.
1966 bool "Kernel Execute-In-Place from ROM"
1967 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1969 Execute-In-Place allows the kernel to run from non-volatile storage
1970 directly addressable by the CPU, such as NOR flash. This saves RAM
1971 space since the text section of the kernel is not loaded from flash
1972 to RAM. Read-write sections, such as the data section and stack,
1973 are still copied to RAM. The XIP kernel is not compressed since
1974 it has to run directly from flash, so it will take more space to
1975 store it. The flash address used to link the kernel object files,
1976 and for storing it, is configuration dependent. Therefore, if you
1977 say Y here, you must know the proper physical address where to
1978 store the kernel image depending on your own flash memory usage.
1980 Also note that the make target becomes "make xipImage" rather than
1981 "make zImage" or "make Image". The final kernel binary to put in
1982 ROM memory will be arch/arm/boot/xipImage.
1986 config XIP_PHYS_ADDR
1987 hex "XIP Kernel Physical Location"
1988 depends on XIP_KERNEL
1989 default "0x00080000"
1991 This is the physical address in your flash memory the kernel will
1992 be linked for and stored to. This address is dependent on your
1996 bool "Kexec system call (EXPERIMENTAL)"
1997 depends on (!SMP || PM_SLEEP_SMP)
2001 kexec is a system call that implements the ability to shutdown your
2002 current kernel, and to start another kernel. It is like a reboot
2003 but it is independent of the system firmware. And like a reboot
2004 you can start any kernel with it, not just Linux.
2006 It is an ongoing process to be certain the hardware in a machine
2007 is properly shutdown, so do not be surprised if this code does not
2008 initially work for you.
2011 bool "Export atags in procfs"
2012 depends on ATAGS && KEXEC
2015 Should the atags used to boot the kernel be exported in an "atags"
2016 file in procfs. Useful with kexec.
2019 bool "Build kdump crash kernel (EXPERIMENTAL)"
2021 Generate crash dump after being started by kexec. This should
2022 be normally only set in special crash dump kernels which are
2023 loaded in the main kernel with kexec-tools into a specially
2024 reserved region and then later executed after a crash by
2025 kdump/kexec. The crash dump kernel must be compiled to a
2026 memory address not used by the main kernel
2028 For more details see Documentation/kdump/kdump.txt
2030 config AUTO_ZRELADDR
2031 bool "Auto calculation of the decompressed kernel image address"
2033 ZRELADDR is the physical address where the decompressed kernel
2034 image will be placed. If AUTO_ZRELADDR is selected, the address
2035 will be determined at run-time by masking the current IP with
2036 0xf8000000. This assumes the zImage being placed in the first 128MB
2037 from start of memory.
2041 menu "CPU Power Management"
2043 source "drivers/cpufreq/Kconfig"
2045 source "drivers/cpuidle/Kconfig"
2049 menu "Floating point emulation"
2051 comment "At least one emulation must be selected"
2054 bool "NWFPE math emulation"
2055 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2057 Say Y to include the NWFPE floating point emulator in the kernel.
2058 This is necessary to run most binaries. Linux does not currently
2059 support floating point hardware so you need to say Y here even if
2060 your machine has an FPA or floating point co-processor podule.
2062 You may say N here if you are going to load the Acorn FPEmulator
2063 early in the bootup.
2066 bool "Support extended precision"
2067 depends on FPE_NWFPE
2069 Say Y to include 80-bit support in the kernel floating-point
2070 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2071 Note that gcc does not generate 80-bit operations by default,
2072 so in most cases this option only enlarges the size of the
2073 floating point emulator without any good reason.
2075 You almost surely want to say N here.
2078 bool "FastFPE math emulation (EXPERIMENTAL)"
2079 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2081 Say Y here to include the FAST floating point emulator in the kernel.
2082 This is an experimental much faster emulator which now also has full
2083 precision for the mantissa. It does not support any exceptions.
2084 It is very simple, and approximately 3-6 times faster than NWFPE.
2086 It should be sufficient for most programs. It may be not suitable
2087 for scientific calculations, but you have to check this for yourself.
2088 If you do not feel you need a faster FP emulation you should better
2092 bool "VFP-format floating point maths"
2093 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2095 Say Y to include VFP support code in the kernel. This is needed
2096 if your hardware includes a VFP unit.
2098 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2099 release notes and additional status information.
2101 Say N if your target does not have VFP hardware.
2109 bool "Advanced SIMD (NEON) Extension support"
2110 depends on VFPv3 && CPU_V7
2112 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2115 config KERNEL_MODE_NEON
2116 bool "Support for NEON in kernel mode"
2117 depends on NEON && AEABI
2119 Say Y to include support for NEON in kernel mode.
2123 menu "Userspace binary formats"
2125 source "fs/Kconfig.binfmt"
2129 menu "Power management options"
2131 source "kernel/power/Kconfig"
2133 config ARCH_SUSPEND_POSSIBLE
2134 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2135 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2138 config ARM_CPU_SUSPEND
2141 config ARCH_HIBERNATION_POSSIBLE
2144 default y if ARCH_SUSPEND_POSSIBLE
2148 source "net/Kconfig"
2150 source "drivers/Kconfig"
2152 source "drivers/firmware/Kconfig"
2156 source "arch/arm/Kconfig.debug"
2158 source "security/Kconfig"
2160 source "crypto/Kconfig"
2162 source "arch/arm/crypto/Kconfig"
2165 source "lib/Kconfig"
2167 source "arch/arm/kvm/Kconfig"