4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_KERNEL_GZIP
42 select HAVE_KERNEL_LZMA
43 select HAVE_KERNEL_LZO
45 select HAVE_KPROBES if !XIP_KERNEL
46 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
49 select HAVE_PERF_EVENTS
50 select HAVE_REGS_AND_STACK_ACCESS_API
51 select HAVE_SYSCALL_TRACEPOINTS
54 select PERF_USE_VMALLOC
56 select SYS_SUPPORTS_APM_EMULATION
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select MODULES_USE_ELF_REL
59 select CLONE_BACKWARDS
60 select OLD_SIGSUSPEND3
63 The ARM series is a line of low-power-consumption RISC chip designs
64 licensed by ARM Ltd and targeted at embedded applications and
65 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
66 manufactured, but legacy ARM-based PC hardware remains popular in
67 Europe. There is an ARM Linux project with a web page at
68 <http://www.arm.linux.org.uk/>.
70 config ARM_HAS_SG_CHAIN
73 config NEED_SG_DMA_LENGTH
76 config ARM_DMA_USE_IOMMU
78 select ARM_HAS_SG_CHAIN
79 select NEED_SG_DMA_LENGTH
83 config ARM_DMA_IOMMU_ALIGNMENT
84 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
88 DMA mapping framework by default aligns all buffers to the smallest
89 PAGE_SIZE order which is greater than or equal to the requested buffer
90 size. This works well for buffers up to a few hundreds kilobytes, but
91 for larger buffers it just a waste of address space. Drivers which has
92 relatively small addressing window (like 64Mib) might run out of
93 virtual space with just a few allocations.
95 With this parameter you can specify the maximum PAGE_SIZE order for
96 DMA IOMMU buffers. Larger buffers will be aligned only to this
97 specified order. The order is expressed as a power of two multiplied
105 config MIGHT_HAVE_PCI
108 config SYS_SUPPORTS_APM_EMULATION
116 select GENERIC_ALLOCATOR
127 The Extended Industry Standard Architecture (EISA) bus was
128 developed as an open alternative to the IBM MicroChannel bus.
130 The EISA bus provided some of the features of the IBM MicroChannel
131 bus while maintaining backward compatibility with cards made for
132 the older ISA bus. The EISA bus saw limited use between 1988 and
133 1995 when it was made obsolete by the PCI bus.
135 Say Y here if you are building a kernel for an EISA-based machine.
142 config STACKTRACE_SUPPORT
146 config HAVE_LATENCYTOP_SUPPORT
151 config LOCKDEP_SUPPORT
155 config TRACE_IRQFLAGS_SUPPORT
159 config RWSEM_GENERIC_SPINLOCK
163 config RWSEM_XCHGADD_ALGORITHM
166 config ARCH_HAS_ILOG2_U32
169 config ARCH_HAS_ILOG2_U64
172 config ARCH_HAS_CPUFREQ
175 Internal node to signify that the ARCH has CPUFREQ support
176 and that the relevant menu configurations are displayed for
179 config GENERIC_HWEIGHT
183 config GENERIC_CALIBRATE_DELAY
187 config ARCH_MAY_HAVE_PC_FDC
193 config NEED_DMA_MAP_STATE
196 config ARCH_HAS_DMA_SET_COHERENT_MASK
199 config GENERIC_ISA_DMA
205 config NEED_RET_TO_USER
213 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
214 default DRAM_BASE if REMAP_VECTORS_TO_RAM
217 The base address of exception vectors.
219 config ARM_PATCH_PHYS_VIRT
220 bool "Patch physical to virtual translations at runtime" if EMBEDDED
222 depends on !XIP_KERNEL && MMU
223 depends on !ARCH_REALVIEW || !SPARSEMEM
225 Patch phys-to-virt and virt-to-phys translation functions at
226 boot and module load time according to the position of the
227 kernel in system memory.
229 This can only be used with non-XIP MMU kernels where the base
230 of physical memory is at a 16MB boundary.
232 Only disable this option if you know that you do not require
233 this feature (eg, building a kernel for a single machine) and
234 you need to shrink the kernel to the minimal size.
236 config NEED_MACH_GPIO_H
239 Select this when mach/gpio.h is required to provide special
240 definitions for this platform. The need for mach/gpio.h should
241 be avoided when possible.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
260 default DRAM_BASE if !MMU
262 Please provide the physical address corresponding to the
263 location of main memory in your system.
269 source "init/Kconfig"
271 source "kernel/Kconfig.freezer"
276 bool "MMU-based Paged Memory Management Support"
279 Select if you want MMU-based virtualised addressing space
280 support by paged memory management. If unsure, say 'Y'.
283 # The "ARM system type" choice list is ordered alphabetically by option
284 # text. Please add new entries in the option alphabetic order.
287 prompt "ARM system type"
288 default ARCH_VERSATILE if !MMU
289 default ARCH_MULTIPLATFORM if MMU
291 config ARCH_MULTIPLATFORM
292 bool "Allow multiple platforms to be selected"
294 select ARM_PATCH_PHYS_VIRT
297 select MULTI_IRQ_HANDLER
301 config ARCH_INTEGRATOR
302 bool "ARM Ltd. Integrator family"
303 select ARCH_HAS_CPUFREQ
306 select COMMON_CLK_VERSATILE
307 select GENERIC_CLOCKEVENTS
310 select MULTI_IRQ_HANDLER
311 select NEED_MACH_MEMORY_H
312 select PLAT_VERSATILE
314 select VERSATILE_FPGA_IRQ
316 Support for ARM's Integrator platform.
319 bool "ARM Ltd. RealView family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select COMMON_CLK_VERSATILE
325 select GENERIC_CLOCKEVENTS
326 select GPIO_PL061 if GPIOLIB
328 select NEED_MACH_MEMORY_H
329 select PLAT_VERSATILE
330 select PLAT_VERSATILE_CLCD
332 This enables support for ARM Ltd RealView boards.
334 config ARCH_VERSATILE
335 bool "ARM Ltd. Versatile family"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select HAVE_MACH_CLKDEV
344 select PLAT_VERSATILE
345 select PLAT_VERSATILE_CLCD
346 select PLAT_VERSATILE_CLOCK
347 select VERSATILE_FPGA_IRQ
349 This enables support for ARM Ltd Versatile board.
353 select ARCH_REQUIRE_GPIOLIB
357 select NEED_MACH_GPIO_H
358 select NEED_MACH_IO_H if PCCARD
360 select PINCTRL_AT91 if USE_OF
362 This enables support for systems based on Atmel
363 AT91RM9200 and AT91SAM9* processors.
366 bool "Broadcom BCM2835 family"
367 select ARCH_REQUIRE_GPIOLIB
369 select ARM_ERRATA_411920
370 select ARM_TIMER_SP804
375 select GENERIC_CLOCKEVENTS
376 select MULTI_IRQ_HANDLER
378 select PINCTRL_BCM2835
382 This enables support for the Broadcom BCM2835 SoC. This SoC is
383 use in the Raspberry Pi, and Roku 2 devices.
386 bool "Cavium Networks CNS3XXX family"
389 select GENERIC_CLOCKEVENTS
390 select MIGHT_HAVE_CACHE_L2X0
391 select MIGHT_HAVE_PCI
392 select PCI_DOMAINS if PCI
394 Support for Cavium Networks CNS3XXX platform.
397 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
398 select ARCH_REQUIRE_GPIOLIB
403 select GENERIC_CLOCKEVENTS
404 select MULTI_IRQ_HANDLER
405 select NEED_MACH_MEMORY_H
408 Support for Cirrus Logic 711x/721x/731x based boards.
411 bool "Cortina Systems Gemini"
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_USES_GETTIMEOFFSET
416 Support for the Cortina Systems Gemini family SoCs
420 select ARCH_REQUIRE_GPIOLIB
423 select GENERIC_CLOCKEVENTS
424 select GENERIC_IRQ_CHIP
425 select MIGHT_HAVE_CACHE_L2X0
431 Support for CSR SiRFprimaII/Marco/Polo platforms
435 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_IO_H
439 select NEED_MACH_MEMORY_H
442 This is an evaluation board for the StrongARM processor available
443 from Digital. It has limited hardware on-board, including an
444 Ethernet interface, two PCMCIA sockets, two serial ports and a
449 select ARCH_HAS_HOLES_MEMORYMODEL
450 select ARCH_REQUIRE_GPIOLIB
451 select ARCH_USES_GETTIMEOFFSET
456 select NEED_MACH_MEMORY_H
458 This enables support for the Cirrus EP93xx series of CPUs.
460 config ARCH_FOOTBRIDGE
464 select GENERIC_CLOCKEVENTS
466 select NEED_MACH_IO_H if !MMU
467 select NEED_MACH_MEMORY_H
469 Support for systems based on the DC21285 companion chip
470 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
473 bool "Freescale MXS-based"
474 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
479 select HAVE_CLK_PREPARE
480 select MULTI_IRQ_HANDLER
485 Support for Freescale MXS-based family of processors
488 bool "Hilscher NetX based"
492 select GENERIC_CLOCKEVENTS
494 This enables support for systems based on the Hilscher NetX Soc
497 bool "Hynix HMS720x-based"
498 select ARCH_USES_GETTIMEOFFSET
502 This enables support for systems based on the Hynix HMS720x
507 select ARCH_SUPPORTS_MSI
509 select NEED_MACH_MEMORY_H
510 select NEED_RET_TO_USER
515 Support for Intel's IOP13XX (XScale) family of processors.
520 select ARCH_REQUIRE_GPIOLIB
522 select NEED_MACH_GPIO_H
523 select NEED_RET_TO_USER
527 Support for Intel's 80219 and IOP32X (XScale) family of
533 select ARCH_REQUIRE_GPIOLIB
535 select NEED_MACH_GPIO_H
536 select NEED_RET_TO_USER
540 Support for Intel's IOP33X (XScale) family of processors.
545 select ARCH_HAS_DMA_SET_COHERENT_MASK
546 select ARCH_REQUIRE_GPIOLIB
549 select DMABOUNCE if PCI
550 select GENERIC_CLOCKEVENTS
551 select MIGHT_HAVE_PCI
552 select NEED_MACH_IO_H
553 select USB_EHCI_BIG_ENDIAN_MMIO
554 select USB_EHCI_BIG_ENDIAN_DESC
556 Support for Intel's IXP4XX (XScale) family of processors.
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
563 select MIGHT_HAVE_PCI
566 select PLAT_ORION_LEGACY
567 select USB_ARCH_HAS_EHCI
569 Support for the Marvell Dove SoC 88AP510
572 bool "Marvell Kirkwood"
573 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
579 select PINCTRL_KIRKWOOD
580 select PLAT_ORION_LEGACY
582 Support for the following Marvell Kirkwood series SoCs:
583 88F6180, 88F6192 and 88F6281.
586 bool "Marvell MV78xx0"
587 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_CLOCKEVENTS
591 select PLAT_ORION_LEGACY
593 Support for the following Marvell MV78xx0 series SoCs:
599 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
603 select PLAT_ORION_LEGACY
605 Support for the following Marvell Orion 5x series SoCs:
606 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
607 Orion-2 (5281), Orion-1-90 (6183).
610 bool "Marvell PXA168/910/MMP2"
612 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_ALLOCATOR
615 select GENERIC_CLOCKEVENTS
618 select NEED_MACH_GPIO_H
623 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
626 bool "Micrel/Kendin KS8695"
627 select ARCH_REQUIRE_GPIOLIB
630 select GENERIC_CLOCKEVENTS
631 select NEED_MACH_MEMORY_H
633 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
634 System-on-Chip devices.
637 bool "Nuvoton W90X900 CPU"
638 select ARCH_REQUIRE_GPIOLIB
642 select GENERIC_CLOCKEVENTS
644 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
645 At present, the w90x900 has been renamed nuc900, regarding
646 the ARM series product line, you can login the following
647 link address to know more.
649 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
650 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
654 select ARCH_REQUIRE_GPIOLIB
659 select GENERIC_CLOCKEVENTS
662 select USB_ARCH_HAS_OHCI
665 Support for the NXP LPC32XX family of processors
669 select ARCH_HAS_CPUFREQ
670 select ARCH_REQUIRE_GPIOLIB
675 select GENERIC_CLOCKEVENTS
678 select MIGHT_HAVE_CACHE_L2X0
682 This enables support for NVIDIA Tegra based systems (Tegra APX,
683 Tegra 6xx and Tegra 2 series).
686 bool "PXA2xx/PXA3xx-based"
688 select ARCH_HAS_CPUFREQ
690 select ARCH_REQUIRE_GPIOLIB
691 select ARM_CPU_SUSPEND if PM
695 select GENERIC_CLOCKEVENTS
698 select MULTI_IRQ_HANDLER
699 select NEED_MACH_GPIO_H
703 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
707 select ARCH_REQUIRE_GPIOLIB
709 select GENERIC_CLOCKEVENTS
712 Support for Qualcomm MSM/QSD based systems. This runs on the
713 apps processor of the MSM/QSD and depends on a shared memory
714 interface to the modem processor which runs the baseband
715 stack and controls some vital subsystems
716 (clock and power control, etc).
719 bool "Renesas SH-Mobile / R-Mobile"
721 select GENERIC_CLOCKEVENTS
723 select HAVE_MACH_CLKDEV
725 select MIGHT_HAVE_CACHE_L2X0
726 select MULTI_IRQ_HANDLER
727 select NEED_MACH_MEMORY_H
730 select PM_GENERIC_DOMAINS if PM
733 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
738 select ARCH_MAY_HAVE_PC_FDC
739 select ARCH_SPARSEMEM_ENABLE
740 select ARCH_USES_GETTIMEOFFSET
743 select HAVE_PATA_PLATFORM
745 select NEED_MACH_IO_H
746 select NEED_MACH_MEMORY_H
750 On the Acorn Risc-PC, Linux can support the internal IDE disk and
751 CD-ROM interface, serial and parallel port, and the floppy drive.
755 select ARCH_HAS_CPUFREQ
757 select ARCH_REQUIRE_GPIOLIB
758 select ARCH_SPARSEMEM_ENABLE
763 select GENERIC_CLOCKEVENTS
766 select NEED_MACH_GPIO_H
767 select NEED_MACH_MEMORY_H
770 Support for StrongARM 11x0 based boards.
773 bool "Samsung S3C24XX SoCs"
774 select ARCH_HAS_CPUFREQ
775 select ARCH_USES_GETTIMEOFFSET
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select HAVE_S3C_RTC if RTC_CLASS
781 select NEED_MACH_GPIO_H
782 select NEED_MACH_IO_H
784 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
785 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
786 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
787 Samsung SMDK2410 development board (and derivatives).
790 bool "Samsung S3C64XX"
791 select ARCH_HAS_CPUFREQ
792 select ARCH_REQUIRE_GPIOLIB
793 select ARCH_USES_GETTIMEOFFSET
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
801 select NEED_MACH_GPIO_H
805 select S3C_GPIO_TRACK
806 select SAMSUNG_CLKSRC
807 select SAMSUNG_GPIOLIB_4BIT
808 select SAMSUNG_IRQ_VIC_TIMER
809 select USB_ARCH_HAS_OHCI
811 Samsung S3C64XX series based systems
814 bool "Samsung S5P6440 S5P6450"
818 select GENERIC_CLOCKEVENTS
820 select HAVE_S3C2410_I2C if I2C
821 select HAVE_S3C2410_WATCHDOG if WATCHDOG
822 select HAVE_S3C_RTC if RTC_CLASS
823 select NEED_MACH_GPIO_H
825 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
829 bool "Samsung S5PC100"
830 select ARCH_USES_GETTIMEOFFSET
834 select HAVE_S3C2410_I2C if I2C
835 select HAVE_S3C2410_WATCHDOG if WATCHDOG
836 select HAVE_S3C_RTC if RTC_CLASS
837 select NEED_MACH_GPIO_H
839 Samsung S5PC100 series based systems
842 bool "Samsung S5PV210/S5PC110"
843 select ARCH_HAS_CPUFREQ
844 select ARCH_HAS_HOLES_MEMORYMODEL
845 select ARCH_SPARSEMEM_ENABLE
849 select GENERIC_CLOCKEVENTS
851 select HAVE_S3C2410_I2C if I2C
852 select HAVE_S3C2410_WATCHDOG if WATCHDOG
853 select HAVE_S3C_RTC if RTC_CLASS
854 select NEED_MACH_GPIO_H
855 select NEED_MACH_MEMORY_H
857 Samsung S5PV210/S5PC110 series based systems
860 bool "Samsung EXYNOS"
861 select ARCH_HAS_CPUFREQ
862 select ARCH_HAS_HOLES_MEMORYMODEL
863 select ARCH_SPARSEMEM_ENABLE
866 select GENERIC_CLOCKEVENTS
868 select HAVE_S3C2410_I2C if I2C
869 select HAVE_S3C2410_WATCHDOG if WATCHDOG
870 select HAVE_S3C_RTC if RTC_CLASS
871 select NEED_MACH_GPIO_H
872 select NEED_MACH_MEMORY_H
874 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
878 select ARCH_USES_GETTIMEOFFSET
882 select NEED_MACH_MEMORY_H
887 Support for the StrongARM based Digital DNARD machine, also known
888 as "Shark" (<http://www.shark-linux.de/shark.html>).
891 bool "ST-Ericsson U300 Series"
893 select ARCH_REQUIRE_GPIOLIB
895 select ARM_PATCH_PHYS_VIRT
901 select GENERIC_CLOCKEVENTS
905 Support for ST-Ericsson U300 series mobile platforms.
908 bool "ST-Ericsson U8500 Series"
910 select ARCH_HAS_CPUFREQ
911 select ARCH_REQUIRE_GPIOLIB
915 select GENERIC_CLOCKEVENTS
917 select MIGHT_HAVE_CACHE_L2X0
920 Support for ST-Ericsson's Ux500 architecture
923 bool "STMicroelectronics Nomadik"
924 select ARCH_REQUIRE_GPIOLIB
927 select CLKSRC_NOMADIK_MTU
930 select GENERIC_CLOCKEVENTS
931 select MIGHT_HAVE_CACHE_L2X0
934 select PINCTRL_STN8815
937 Support for the Nomadik platform by ST-Ericsson
941 select ARCH_HAS_CPUFREQ
942 select ARCH_REQUIRE_GPIOLIB
947 select GENERIC_CLOCKEVENTS
950 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
954 select ARCH_HAS_HOLES_MEMORYMODEL
955 select ARCH_REQUIRE_GPIOLIB
957 select GENERIC_ALLOCATOR
958 select GENERIC_CLOCKEVENTS
959 select GENERIC_IRQ_CHIP
961 select NEED_MACH_GPIO_H
965 Support for TI's DaVinci platform.
970 select ARCH_HAS_CPUFREQ
971 select ARCH_HAS_HOLES_MEMORYMODEL
973 select ARCH_REQUIRE_GPIOLIB
976 select GENERIC_CLOCKEVENTS
977 select GENERIC_IRQ_CHIP
981 select NEED_MACH_IO_H if PCCARD
982 select NEED_MACH_MEMORY_H
984 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
988 menu "Multiple platform selection"
989 depends on ARCH_MULTIPLATFORM
991 comment "CPU Core family selection"
994 bool "ARMv4 based platforms (FA526, StrongARM)"
995 depends on !ARCH_MULTI_V6_V7
996 select ARCH_MULTI_V4_V5
998 config ARCH_MULTI_V4T
999 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
1000 depends on !ARCH_MULTI_V6_V7
1001 select ARCH_MULTI_V4_V5
1003 config ARCH_MULTI_V5
1004 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1005 depends on !ARCH_MULTI_V6_V7
1006 select ARCH_MULTI_V4_V5
1008 config ARCH_MULTI_V4_V5
1011 config ARCH_MULTI_V6
1012 bool "ARMv6 based platforms (ARM11)"
1013 select ARCH_MULTI_V6_V7
1016 config ARCH_MULTI_V7
1017 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
1019 select ARCH_MULTI_V6_V7
1020 select ARCH_VEXPRESS
1023 config ARCH_MULTI_V6_V7
1026 config ARCH_MULTI_CPU_AUTO
1027 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1028 select ARCH_MULTI_V5
1033 # This is sorted alphabetically by mach-* pathname. However, plat-*
1034 # Kconfigs may be included either alphabetically (according to the
1035 # plat- suffix) or along side the corresponding mach-* source.
1037 source "arch/arm/mach-mvebu/Kconfig"
1039 source "arch/arm/mach-at91/Kconfig"
1041 source "arch/arm/mach-bcm/Kconfig"
1043 source "arch/arm/mach-clps711x/Kconfig"
1045 source "arch/arm/mach-cns3xxx/Kconfig"
1047 source "arch/arm/mach-davinci/Kconfig"
1049 source "arch/arm/mach-dove/Kconfig"
1051 source "arch/arm/mach-ep93xx/Kconfig"
1053 source "arch/arm/mach-footbridge/Kconfig"
1055 source "arch/arm/mach-gemini/Kconfig"
1057 source "arch/arm/mach-h720x/Kconfig"
1059 source "arch/arm/mach-highbank/Kconfig"
1061 source "arch/arm/mach-integrator/Kconfig"
1063 source "arch/arm/mach-iop32x/Kconfig"
1065 source "arch/arm/mach-iop33x/Kconfig"
1067 source "arch/arm/mach-iop13xx/Kconfig"
1069 source "arch/arm/mach-ixp4xx/Kconfig"
1071 source "arch/arm/mach-kirkwood/Kconfig"
1073 source "arch/arm/mach-ks8695/Kconfig"
1075 source "arch/arm/mach-msm/Kconfig"
1077 source "arch/arm/mach-mv78xx0/Kconfig"
1079 source "arch/arm/mach-imx/Kconfig"
1081 source "arch/arm/mach-mxs/Kconfig"
1083 source "arch/arm/mach-netx/Kconfig"
1085 source "arch/arm/mach-nomadik/Kconfig"
1087 source "arch/arm/plat-omap/Kconfig"
1089 source "arch/arm/mach-omap1/Kconfig"
1091 source "arch/arm/mach-omap2/Kconfig"
1093 source "arch/arm/mach-orion5x/Kconfig"
1095 source "arch/arm/mach-picoxcell/Kconfig"
1097 source "arch/arm/mach-pxa/Kconfig"
1098 source "arch/arm/plat-pxa/Kconfig"
1100 source "arch/arm/mach-mmp/Kconfig"
1102 source "arch/arm/mach-realview/Kconfig"
1104 source "arch/arm/mach-sa1100/Kconfig"
1106 source "arch/arm/plat-samsung/Kconfig"
1108 source "arch/arm/mach-socfpga/Kconfig"
1110 source "arch/arm/plat-spear/Kconfig"
1112 source "arch/arm/mach-s3c24xx/Kconfig"
1115 source "arch/arm/mach-s3c64xx/Kconfig"
1118 source "arch/arm/mach-s5p64x0/Kconfig"
1120 source "arch/arm/mach-s5pc100/Kconfig"
1122 source "arch/arm/mach-s5pv210/Kconfig"
1124 source "arch/arm/mach-exynos/Kconfig"
1126 source "arch/arm/mach-shmobile/Kconfig"
1128 source "arch/arm/mach-sunxi/Kconfig"
1130 source "arch/arm/mach-prima2/Kconfig"
1132 source "arch/arm/mach-tegra/Kconfig"
1134 source "arch/arm/mach-u300/Kconfig"
1136 source "arch/arm/mach-ux500/Kconfig"
1138 source "arch/arm/mach-versatile/Kconfig"
1140 source "arch/arm/mach-vexpress/Kconfig"
1141 source "arch/arm/plat-versatile/Kconfig"
1143 source "arch/arm/mach-virt/Kconfig"
1145 source "arch/arm/mach-vt8500/Kconfig"
1147 source "arch/arm/mach-w90x900/Kconfig"
1149 source "arch/arm/mach-zynq/Kconfig"
1151 # Definitions to make life easier
1157 select GENERIC_CLOCKEVENTS
1163 select GENERIC_IRQ_CHIP
1166 config PLAT_ORION_LEGACY
1173 config PLAT_VERSATILE
1176 config ARM_TIMER_SP804
1179 select HAVE_SCHED_CLOCK
1181 source arch/arm/mm/Kconfig
1185 default 16 if ARCH_EP93XX
1189 bool "Enable iWMMXt support" if !CPU_PJ4
1190 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1191 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1193 Enable support for iWMMXt context switching at run time if
1194 running on a CPU that supports it.
1198 depends on CPU_XSCALE
1201 config MULTI_IRQ_HANDLER
1204 Allow each machine to specify it's own IRQ handler at run time.
1207 source "arch/arm/Kconfig-nommu"
1210 config ARM_ERRATA_326103
1211 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1214 Executing a SWP instruction to read-only memory does not set bit 11
1215 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1216 treat the access as a read, preventing a COW from occurring and
1217 causing the faulting task to livelock.
1219 config ARM_ERRATA_411920
1220 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1221 depends on CPU_V6 || CPU_V6K
1223 Invalidation of the Instruction Cache operation can
1224 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1225 It does not affect the MPCore. This option enables the ARM Ltd.
1226 recommended workaround.
1228 config ARM_ERRATA_430973
1229 bool "ARM errata: Stale prediction on replaced interworking branch"
1232 This option enables the workaround for the 430973 Cortex-A8
1233 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1234 interworking branch is replaced with another code sequence at the
1235 same virtual address, whether due to self-modifying code or virtual
1236 to physical address re-mapping, Cortex-A8 does not recover from the
1237 stale interworking branch prediction. This results in Cortex-A8
1238 executing the new code sequence in the incorrect ARM or Thumb state.
1239 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1240 and also flushes the branch target cache at every context switch.
1241 Note that setting specific bits in the ACTLR register may not be
1242 available in non-secure mode.
1244 config ARM_ERRATA_458693
1245 bool "ARM errata: Processor deadlock when a false hazard is created"
1247 depends on !ARCH_MULTIPLATFORM
1249 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1250 erratum. For very specific sequences of memory operations, it is
1251 possible for a hazard condition intended for a cache line to instead
1252 be incorrectly associated with a different cache line. This false
1253 hazard might then cause a processor deadlock. The workaround enables
1254 the L1 caching of the NEON accesses and disables the PLD instruction
1255 in the ACTLR register. Note that setting specific bits in the ACTLR
1256 register may not be available in non-secure mode.
1258 config ARM_ERRATA_460075
1259 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1261 depends on !ARCH_MULTIPLATFORM
1263 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1264 erratum. Any asynchronous access to the L2 cache may encounter a
1265 situation in which recent store transactions to the L2 cache are lost
1266 and overwritten with stale memory contents from external memory. The
1267 workaround disables the write-allocate mode for the L2 cache via the
1268 ACTLR register. Note that setting specific bits in the ACTLR register
1269 may not be available in non-secure mode.
1271 config ARM_ERRATA_742230
1272 bool "ARM errata: DMB operation may be faulty"
1273 depends on CPU_V7 && SMP
1274 depends on !ARCH_MULTIPLATFORM
1276 This option enables the workaround for the 742230 Cortex-A9
1277 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1278 between two write operations may not ensure the correct visibility
1279 ordering of the two writes. This workaround sets a specific bit in
1280 the diagnostic register of the Cortex-A9 which causes the DMB
1281 instruction to behave as a DSB, ensuring the correct behaviour of
1284 config ARM_ERRATA_742231
1285 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1286 depends on CPU_V7 && SMP
1287 depends on !ARCH_MULTIPLATFORM
1289 This option enables the workaround for the 742231 Cortex-A9
1290 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1291 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1292 accessing some data located in the same cache line, may get corrupted
1293 data due to bad handling of the address hazard when the line gets
1294 replaced from one of the CPUs at the same time as another CPU is
1295 accessing it. This workaround sets specific bits in the diagnostic
1296 register of the Cortex-A9 which reduces the linefill issuing
1297 capabilities of the processor.
1299 config PL310_ERRATA_588369
1300 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1301 depends on CACHE_L2X0
1303 The PL310 L2 cache controller implements three types of Clean &
1304 Invalidate maintenance operations: by Physical Address
1305 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1306 They are architecturally defined to behave as the execution of a
1307 clean operation followed immediately by an invalidate operation,
1308 both performing to the same memory location. This functionality
1309 is not correctly implemented in PL310 as clean lines are not
1310 invalidated as a result of these operations.
1312 config ARM_ERRATA_720789
1313 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1316 This option enables the workaround for the 720789 Cortex-A9 (prior to
1317 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1318 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1319 As a consequence of this erratum, some TLB entries which should be
1320 invalidated are not, resulting in an incoherency in the system page
1321 tables. The workaround changes the TLB flushing routines to invalidate
1322 entries regardless of the ASID.
1324 config PL310_ERRATA_727915
1325 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1326 depends on CACHE_L2X0
1328 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1329 operation (offset 0x7FC). This operation runs in background so that
1330 PL310 can handle normal accesses while it is in progress. Under very
1331 rare circumstances, due to this erratum, write data can be lost when
1332 PL310 treats a cacheable write transaction during a Clean &
1333 Invalidate by Way operation.
1335 config ARM_ERRATA_743622
1336 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1338 depends on !ARCH_MULTIPLATFORM
1340 This option enables the workaround for the 743622 Cortex-A9
1341 (r2p*) erratum. Under very rare conditions, a faulty
1342 optimisation in the Cortex-A9 Store Buffer may lead to data
1343 corruption. This workaround sets a specific bit in the diagnostic
1344 register of the Cortex-A9 which disables the Store Buffer
1345 optimisation, preventing the defect from occurring. This has no
1346 visible impact on the overall performance or power consumption of the
1349 config ARM_ERRATA_751472
1350 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1352 depends on !ARCH_MULTIPLATFORM
1354 This option enables the workaround for the 751472 Cortex-A9 (prior
1355 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1356 completion of a following broadcasted operation if the second
1357 operation is received by a CPU before the ICIALLUIS has completed,
1358 potentially leading to corrupted entries in the cache or TLB.
1360 config PL310_ERRATA_753970
1361 bool "PL310 errata: cache sync operation may be faulty"
1362 depends on CACHE_PL310
1364 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1366 Under some condition the effect of cache sync operation on
1367 the store buffer still remains when the operation completes.
1368 This means that the store buffer is always asked to drain and
1369 this prevents it from merging any further writes. The workaround
1370 is to replace the normal offset of cache sync operation (0x730)
1371 by another offset targeting an unmapped PL310 register 0x740.
1372 This has the same effect as the cache sync operation: store buffer
1373 drain and waiting for all buffers empty.
1375 config ARM_ERRATA_754322
1376 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1379 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1380 r3p*) erratum. A speculative memory access may cause a page table walk
1381 which starts prior to an ASID switch but completes afterwards. This
1382 can populate the micro-TLB with a stale entry which may be hit with
1383 the new ASID. This workaround places two dsb instructions in the mm
1384 switching code so that no page table walks can cross the ASID switch.
1386 config ARM_ERRATA_754327
1387 bool "ARM errata: no automatic Store Buffer drain"
1388 depends on CPU_V7 && SMP
1390 This option enables the workaround for the 754327 Cortex-A9 (prior to
1391 r2p0) erratum. The Store Buffer does not have any automatic draining
1392 mechanism and therefore a livelock may occur if an external agent
1393 continuously polls a memory location waiting to observe an update.
1394 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1395 written polling loops from denying visibility of updates to memory.
1397 config ARM_ERRATA_364296
1398 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1399 depends on CPU_V6 && !SMP
1401 This options enables the workaround for the 364296 ARM1136
1402 r0p2 erratum (possible cache data corruption with
1403 hit-under-miss enabled). It sets the undocumented bit 31 in
1404 the auxiliary control register and the FI bit in the control
1405 register, thus disabling hit-under-miss without putting the
1406 processor into full low interrupt latency mode. ARM11MPCore
1409 config ARM_ERRATA_764369
1410 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1411 depends on CPU_V7 && SMP
1413 This option enables the workaround for erratum 764369
1414 affecting Cortex-A9 MPCore with two or more processors (all
1415 current revisions). Under certain timing circumstances, a data
1416 cache line maintenance operation by MVA targeting an Inner
1417 Shareable memory region may fail to proceed up to either the
1418 Point of Coherency or to the Point of Unification of the
1419 system. This workaround adds a DSB instruction before the
1420 relevant cache maintenance functions and sets a specific bit
1421 in the diagnostic control register of the SCU.
1423 config PL310_ERRATA_769419
1424 bool "PL310 errata: no automatic Store Buffer drain"
1425 depends on CACHE_L2X0
1427 On revisions of the PL310 prior to r3p2, the Store Buffer does
1428 not automatically drain. This can cause normal, non-cacheable
1429 writes to be retained when the memory system is idle, leading
1430 to suboptimal I/O performance for drivers using coherent DMA.
1431 This option adds a write barrier to the cpu_idle loop so that,
1432 on systems with an outer cache, the store buffer is drained
1435 config ARM_ERRATA_775420
1436 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1439 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1440 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1441 operation aborts with MMU exception, it might cause the processor
1442 to deadlock. This workaround puts DSB before executing ISB if
1443 an abort may occur on cache maintenance.
1445 config ARM_ERRATA_798181
1446 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1447 depends on CPU_V7 && SMP
1449 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1450 adequately shooting down all use of the old entries. This
1451 option enables the Linux kernel workaround for this erratum
1452 which sends an IPI to the CPUs that are running the same ASID
1453 as the one being invalidated.
1457 source "arch/arm/common/Kconfig"
1467 Find out whether you have ISA slots on your motherboard. ISA is the
1468 name of a bus system, i.e. the way the CPU talks to the other stuff
1469 inside your box. Other bus systems are PCI, EISA, MicroChannel
1470 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1471 newer boards don't support it. If you have ISA, say Y, otherwise N.
1473 # Select ISA DMA controller support
1478 # Select ISA DMA interface
1483 bool "PCI support" if MIGHT_HAVE_PCI
1485 Find out whether you have a PCI motherboard. PCI is the name of a
1486 bus system, i.e. the way the CPU talks to the other stuff inside
1487 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1488 VESA. If you have PCI, say Y, otherwise N.
1494 config PCI_NANOENGINE
1495 bool "BSE nanoEngine PCI support"
1496 depends on SA1100_NANOENGINE
1498 Enable PCI on the BSE nanoEngine board.
1503 # Select the host bridge type
1504 config PCI_HOST_VIA82C505
1506 depends on PCI && ARCH_SHARK
1509 config PCI_HOST_ITE8152
1511 depends on PCI && MACH_ARMCORE
1515 source "drivers/pci/Kconfig"
1517 source "drivers/pcmcia/Kconfig"
1521 menu "Kernel Features"
1526 This option should be selected by machines which have an SMP-
1529 The only effect of this option is to make the SMP-related
1530 options available to the user for configuration.
1533 bool "Symmetric Multi-Processing"
1534 depends on CPU_V6K || CPU_V7
1535 depends on GENERIC_CLOCKEVENTS
1538 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1539 select USE_GENERIC_SMP_HELPERS
1541 This enables support for systems with more than one CPU. If you have
1542 a system with only one CPU, like most personal computers, say N. If
1543 you have a system with more than one CPU, say Y.
1545 If you say N here, the kernel will run on single and multiprocessor
1546 machines, but will use only one CPU of a multiprocessor machine. If
1547 you say Y here, the kernel will run on many, but not all, single
1548 processor machines. On a single processor machine, the kernel will
1549 run faster if you say N here.
1551 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1552 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1553 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1555 If you don't know what to do here, say N.
1558 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1559 depends on SMP && !XIP_KERNEL
1562 SMP kernels contain instructions which fail on non-SMP processors.
1563 Enabling this option allows the kernel to modify itself to make
1564 these instructions safe. Disabling it allows about 1K of space
1567 If you don't know what to do here, say Y.
1569 config ARM_CPU_TOPOLOGY
1570 bool "Support cpu topology definition"
1571 depends on SMP && CPU_V7
1574 Support ARM cpu topology definition. The MPIDR register defines
1575 affinity between processors which is then used to describe the cpu
1576 topology of an ARM System.
1579 bool "Multi-core scheduler support"
1580 depends on ARM_CPU_TOPOLOGY
1582 Multi-core scheduler support improves the CPU scheduler's decision
1583 making when dealing with multi-core CPU chips at a cost of slightly
1584 increased overhead in some places. If unsure say N here.
1587 bool "SMT scheduler support"
1588 depends on ARM_CPU_TOPOLOGY
1590 Improves the CPU scheduler's decision making when dealing with
1591 MultiThreading at a cost of slightly increased overhead in some
1592 places. If unsure say N here.
1597 This option enables support for the ARM system coherency unit
1599 config HAVE_ARM_ARCH_TIMER
1600 bool "Architected timer support"
1602 select ARM_ARCH_TIMER
1604 This option enables support for the ARM architected timer
1610 This options enables support for the ARM timer and watchdog unit
1613 prompt "Memory split"
1616 Select the desired split between kernel and user memory.
1618 If you are not absolutely sure what you are doing, leave this
1622 bool "3G/1G user/kernel split"
1624 bool "2G/2G user/kernel split"
1626 bool "1G/3G user/kernel split"
1631 default 0x40000000 if VMSPLIT_1G
1632 default 0x80000000 if VMSPLIT_2G
1636 int "Maximum number of CPUs (2-32)"
1642 bool "Support for hot-pluggable CPUs"
1643 depends on SMP && HOTPLUG
1645 Say Y here to experiment with turning CPUs off and on. CPUs
1646 can be controlled through /sys/devices/system/cpu.
1649 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1652 Say Y here if you want Linux to communicate with system firmware
1653 implementing the PSCI specification for CPU-centric power
1654 management operations described in ARM document number ARM DEN
1655 0022A ("Power State Coordination Interface System Software on
1659 bool "Use local timer interrupts"
1662 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1664 Enable support for local timers on SMP platforms, rather then the
1665 legacy IPI broadcast method. Local timers allows the system
1666 accounting to be spread across the timer interval, preventing a
1667 "thundering herd" at every timer tick.
1669 # The GPIO number here must be sorted by descending number. In case of
1670 # a multiplatform kernel, we just want the highest value required by the
1671 # selected platforms.
1674 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1675 default 512 if SOC_OMAP5
1676 default 355 if ARCH_U8500
1677 default 288 if ARCH_VT8500 || ARCH_SUNXI
1678 default 264 if MACH_H4700
1681 Maximum number of GPIOs in the system.
1683 If unsure, leave the default value.
1685 source kernel/Kconfig.preempt
1689 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1690 ARCH_S5PV210 || ARCH_EXYNOS4
1691 default AT91_TIMER_HZ if ARCH_AT91
1692 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1696 def_bool HIGH_RES_TIMERS
1698 config THUMB2_KERNEL
1699 bool "Compile the kernel in Thumb-2 mode"
1700 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1702 select ARM_ASM_UNIFIED
1705 By enabling this option, the kernel will be compiled in
1706 Thumb-2 mode. A compiler/assembler that understand the unified
1707 ARM-Thumb syntax is needed.
1711 config THUMB2_AVOID_R_ARM_THM_JUMP11
1712 bool "Work around buggy Thumb-2 short branch relocations in gas"
1713 depends on THUMB2_KERNEL && MODULES
1716 Various binutils versions can resolve Thumb-2 branches to
1717 locally-defined, preemptible global symbols as short-range "b.n"
1718 branch instructions.
1720 This is a problem, because there's no guarantee the final
1721 destination of the symbol, or any candidate locations for a
1722 trampoline, are within range of the branch. For this reason, the
1723 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1724 relocation in modules at all, and it makes little sense to add
1727 The symptom is that the kernel fails with an "unsupported
1728 relocation" error when loading some modules.
1730 Until fixed tools are available, passing
1731 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1732 code which hits this problem, at the cost of a bit of extra runtime
1733 stack usage in some cases.
1735 The problem is described in more detail at:
1736 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1738 Only Thumb-2 kernels are affected.
1740 Unless you are sure your tools don't have this problem, say Y.
1742 config ARM_ASM_UNIFIED
1746 bool "Use the ARM EABI to compile the kernel"
1748 This option allows for the kernel to be compiled using the latest
1749 ARM ABI (aka EABI). This is only useful if you are using a user
1750 space environment that is also compiled with EABI.
1752 Since there are major incompatibilities between the legacy ABI and
1753 EABI, especially with regard to structure member alignment, this
1754 option also changes the kernel syscall calling convention to
1755 disambiguate both ABIs and allow for backward compatibility support
1756 (selected with CONFIG_OABI_COMPAT).
1758 To use this you need GCC version 4.0.0 or later.
1761 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1762 depends on AEABI && !THUMB2_KERNEL
1765 This option preserves the old syscall interface along with the
1766 new (ARM EABI) one. It also provides a compatibility layer to
1767 intercept syscalls that have structure arguments which layout
1768 in memory differs between the legacy ABI and the new ARM EABI
1769 (only for non "thumb" binaries). This option adds a tiny
1770 overhead to all syscalls and produces a slightly larger kernel.
1771 If you know you'll be using only pure EABI user space then you
1772 can say N here. If this option is not selected and you attempt
1773 to execute a legacy ABI binary then the result will be
1774 UNPREDICTABLE (in fact it can be predicted that it won't work
1775 at all). If in doubt say Y.
1777 config ARCH_HAS_HOLES_MEMORYMODEL
1780 config ARCH_SPARSEMEM_ENABLE
1783 config ARCH_SPARSEMEM_DEFAULT
1784 def_bool ARCH_SPARSEMEM_ENABLE
1786 config ARCH_SELECT_MEMORY_MODEL
1787 def_bool ARCH_SPARSEMEM_ENABLE
1789 config HAVE_ARCH_PFN_VALID
1790 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1793 bool "High Memory Support"
1796 The address space of ARM processors is only 4 Gigabytes large
1797 and it has to accommodate user address space, kernel address
1798 space as well as some memory mapped IO. That means that, if you
1799 have a large amount of physical memory and/or IO, not all of the
1800 memory can be "permanently mapped" by the kernel. The physical
1801 memory that is not permanently mapped is called "high memory".
1803 Depending on the selected kernel/user memory split, minimum
1804 vmalloc space and actual amount of RAM, you may not need this
1805 option which should result in a slightly faster kernel.
1810 bool "Allocate 2nd-level pagetables from highmem"
1813 config HW_PERF_EVENTS
1814 bool "Enable hardware performance counter support for perf events"
1815 depends on PERF_EVENTS
1818 Enable hardware performance counter support for perf events. If
1819 disabled, perf events will use software events only.
1823 config FORCE_MAX_ZONEORDER
1824 int "Maximum zone order" if ARCH_SHMOBILE
1825 range 11 64 if ARCH_SHMOBILE
1826 default "12" if SOC_AM33XX
1827 default "9" if SA1111
1830 The kernel memory allocator divides physically contiguous memory
1831 blocks into "zones", where each zone is a power of two number of
1832 pages. This option selects the largest power of two that the kernel
1833 keeps in the memory allocator. If you need to allocate very large
1834 blocks of physically contiguous memory, then you may need to
1835 increase this value.
1837 This config option is actually maximum order plus one. For example,
1838 a value of 11 means that the largest free memory block is 2^10 pages.
1840 config ALIGNMENT_TRAP
1842 depends on CPU_CP15_MMU
1843 default y if !ARCH_EBSA110
1844 select HAVE_PROC_CPU if PROC_FS
1846 ARM processors cannot fetch/store information which is not
1847 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1848 address divisible by 4. On 32-bit ARM processors, these non-aligned
1849 fetch/store instructions will be emulated in software if you say
1850 here, which has a severe performance impact. This is necessary for
1851 correct operation of some network protocols. With an IP-only
1852 configuration it is safe to say N, otherwise say Y.
1854 config UACCESS_WITH_MEMCPY
1855 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1857 default y if CPU_FEROCEON
1859 Implement faster copy_to_user and clear_user methods for CPU
1860 cores where a 8-word STM instruction give significantly higher
1861 memory write throughput than a sequence of individual 32bit stores.
1863 A possible side effect is a slight increase in scheduling latency
1864 between threads sharing the same address space if they invoke
1865 such copy operations with large buffers.
1867 However, if the CPU data cache is using a write-allocate mode,
1868 this option is unlikely to provide any performance gain.
1872 prompt "Enable seccomp to safely compute untrusted bytecode"
1874 This kernel feature is useful for number crunching applications
1875 that may need to compute untrusted bytecode during their
1876 execution. By using pipes or other transports made available to
1877 the process as file descriptors supporting the read/write
1878 syscalls, it's possible to isolate those applications in
1879 their own address space using seccomp. Once seccomp is
1880 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1881 and the task is only allowed to execute a few safe syscalls
1882 defined by each seccomp mode.
1884 config CC_STACKPROTECTOR
1885 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1887 This option turns on the -fstack-protector GCC feature. This
1888 feature puts, at the beginning of functions, a canary value on
1889 the stack just before the return address, and validates
1890 the value just before actually returning. Stack based buffer
1891 overflows (that need to overwrite this return address) now also
1892 overwrite the canary, which gets detected and the attack is then
1893 neutralized via a kernel panic.
1894 This feature requires gcc version 4.2 or above.
1901 bool "Xen guest support on ARM (EXPERIMENTAL)"
1902 depends on ARM && AEABI && OF
1903 depends on CPU_V7 && !CPU_V6
1904 depends on !GENERIC_ATOMIC64
1906 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1913 bool "Flattened Device Tree support"
1916 select OF_EARLY_FLATTREE
1918 Include support for flattened device tree machine descriptions.
1921 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1924 This is the traditional way of passing data to the kernel at boot
1925 time. If you are solely relying on the flattened device tree (or
1926 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1927 to remove ATAGS support from your kernel binary. If unsure,
1930 config DEPRECATED_PARAM_STRUCT
1931 bool "Provide old way to pass kernel parameters"
1934 This was deprecated in 2001 and announced to live on for 5 years.
1935 Some old boot loaders still use this way.
1937 # Compressed boot loader in ROM. Yes, we really want to ask about
1938 # TEXT and BSS so we preserve their values in the config files.
1939 config ZBOOT_ROM_TEXT
1940 hex "Compressed ROM boot loader base address"
1943 The physical address at which the ROM-able zImage is to be
1944 placed in the target. Platforms which normally make use of
1945 ROM-able zImage formats normally set this to a suitable
1946 value in their defconfig file.
1948 If ZBOOT_ROM is not enabled, this has no effect.
1950 config ZBOOT_ROM_BSS
1951 hex "Compressed ROM boot loader BSS address"
1954 The base address of an area of read/write memory in the target
1955 for the ROM-able zImage which must be available while the
1956 decompressor is running. It must be large enough to hold the
1957 entire decompressed kernel plus an additional 128 KiB.
1958 Platforms which normally make use of ROM-able zImage formats
1959 normally set this to a suitable value in their defconfig file.
1961 If ZBOOT_ROM is not enabled, this has no effect.
1964 bool "Compressed boot loader in ROM/flash"
1965 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1967 Say Y here if you intend to execute your compressed kernel image
1968 (zImage) directly from ROM or flash. If unsure, say N.
1971 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1972 depends on ZBOOT_ROM && ARCH_SH7372
1973 default ZBOOT_ROM_NONE
1975 Include experimental SD/MMC loading code in the ROM-able zImage.
1976 With this enabled it is possible to write the ROM-able zImage
1977 kernel image to an MMC or SD card and boot the kernel straight
1978 from the reset vector. At reset the processor Mask ROM will load
1979 the first part of the ROM-able zImage which in turn loads the
1980 rest the kernel image to RAM.
1982 config ZBOOT_ROM_NONE
1983 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1985 Do not load image from SD or MMC
1987 config ZBOOT_ROM_MMCIF
1988 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1990 Load image from MMCIF hardware block.
1992 config ZBOOT_ROM_SH_MOBILE_SDHI
1993 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1995 Load image from SDHI hardware block
1999 config ARM_APPENDED_DTB
2000 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2001 depends on OF && !ZBOOT_ROM
2003 With this option, the boot code will look for a device tree binary
2004 (DTB) appended to zImage
2005 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2007 This is meant as a backward compatibility convenience for those
2008 systems with a bootloader that can't be upgraded to accommodate
2009 the documented boot protocol using a device tree.
2011 Beware that there is very little in terms of protection against
2012 this option being confused by leftover garbage in memory that might
2013 look like a DTB header after a reboot if no actual DTB is appended
2014 to zImage. Do not leave this option active in a production kernel
2015 if you don't intend to always append a DTB. Proper passing of the
2016 location into r2 of a bootloader provided DTB is always preferable
2019 config ARM_ATAG_DTB_COMPAT
2020 bool "Supplement the appended DTB with traditional ATAG information"
2021 depends on ARM_APPENDED_DTB
2023 Some old bootloaders can't be updated to a DTB capable one, yet
2024 they provide ATAGs with memory configuration, the ramdisk address,
2025 the kernel cmdline string, etc. Such information is dynamically
2026 provided by the bootloader and can't always be stored in a static
2027 DTB. To allow a device tree enabled kernel to be used with such
2028 bootloaders, this option allows zImage to extract the information
2029 from the ATAG list and store it at run time into the appended DTB.
2032 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2033 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2035 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2036 bool "Use bootloader kernel arguments if available"
2038 Uses the command-line options passed by the boot loader instead of
2039 the device tree bootargs property. If the boot loader doesn't provide
2040 any, the device tree bootargs property will be used.
2042 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2043 bool "Extend with bootloader kernel arguments"
2045 The command-line arguments provided by the boot loader will be
2046 appended to the the device tree bootargs property.
2051 string "Default kernel command string"
2054 On some architectures (EBSA110 and CATS), there is currently no way
2055 for the boot loader to pass arguments to the kernel. For these
2056 architectures, you should supply some command-line options at build
2057 time by entering them here. As a minimum, you should specify the
2058 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2061 prompt "Kernel command line type" if CMDLINE != ""
2062 default CMDLINE_FROM_BOOTLOADER
2065 config CMDLINE_FROM_BOOTLOADER
2066 bool "Use bootloader kernel arguments if available"
2068 Uses the command-line options passed by the boot loader. If
2069 the boot loader doesn't provide any, the default kernel command
2070 string provided in CMDLINE will be used.
2072 config CMDLINE_EXTEND
2073 bool "Extend bootloader kernel arguments"
2075 The command-line arguments provided by the boot loader will be
2076 appended to the default kernel command string.
2078 config CMDLINE_FORCE
2079 bool "Always use the default kernel command string"
2081 Always use the default kernel command string, even if the boot
2082 loader passes other arguments to the kernel.
2083 This is useful if you cannot or don't want to change the
2084 command-line options your boot loader passes to the kernel.
2088 bool "Kernel Execute-In-Place from ROM"
2089 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2091 Execute-In-Place allows the kernel to run from non-volatile storage
2092 directly addressable by the CPU, such as NOR flash. This saves RAM
2093 space since the text section of the kernel is not loaded from flash
2094 to RAM. Read-write sections, such as the data section and stack,
2095 are still copied to RAM. The XIP kernel is not compressed since
2096 it has to run directly from flash, so it will take more space to
2097 store it. The flash address used to link the kernel object files,
2098 and for storing it, is configuration dependent. Therefore, if you
2099 say Y here, you must know the proper physical address where to
2100 store the kernel image depending on your own flash memory usage.
2102 Also note that the make target becomes "make xipImage" rather than
2103 "make zImage" or "make Image". The final kernel binary to put in
2104 ROM memory will be arch/arm/boot/xipImage.
2108 config XIP_PHYS_ADDR
2109 hex "XIP Kernel Physical Location"
2110 depends on XIP_KERNEL
2111 default "0x00080000"
2113 This is the physical address in your flash memory the kernel will
2114 be linked for and stored to. This address is dependent on your
2118 bool "Kexec system call (EXPERIMENTAL)"
2119 depends on (!SMP || HOTPLUG_CPU)
2121 kexec is a system call that implements the ability to shutdown your
2122 current kernel, and to start another kernel. It is like a reboot
2123 but it is independent of the system firmware. And like a reboot
2124 you can start any kernel with it, not just Linux.
2126 It is an ongoing process to be certain the hardware in a machine
2127 is properly shutdown, so do not be surprised if this code does not
2128 initially work for you. It may help to enable device hotplugging
2132 bool "Export atags in procfs"
2133 depends on ATAGS && KEXEC
2136 Should the atags used to boot the kernel be exported in an "atags"
2137 file in procfs. Useful with kexec.
2140 bool "Build kdump crash kernel (EXPERIMENTAL)"
2142 Generate crash dump after being started by kexec. This should
2143 be normally only set in special crash dump kernels which are
2144 loaded in the main kernel with kexec-tools into a specially
2145 reserved region and then later executed after a crash by
2146 kdump/kexec. The crash dump kernel must be compiled to a
2147 memory address not used by the main kernel
2149 For more details see Documentation/kdump/kdump.txt
2151 config AUTO_ZRELADDR
2152 bool "Auto calculation of the decompressed kernel image address"
2153 depends on !ZBOOT_ROM && !ARCH_U300
2155 ZRELADDR is the physical address where the decompressed kernel
2156 image will be placed. If AUTO_ZRELADDR is selected, the address
2157 will be determined at run-time by masking the current IP with
2158 0xf8000000. This assumes the zImage being placed in the first 128MB
2159 from start of memory.
2163 menu "CPU Power Management"
2166 source "drivers/cpufreq/Kconfig"
2169 tristate "CPUfreq driver for i.MX CPUs"
2170 depends on ARCH_MXC && CPU_FREQ
2171 select CPU_FREQ_TABLE
2173 This enables the CPUfreq driver for i.MX CPUs.
2178 Internal configuration node for common cpufreq on Samsung SoC
2180 config CPU_FREQ_S3C24XX
2181 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2182 depends on ARCH_S3C24XX && CPU_FREQ
2185 This enables the CPUfreq driver for the Samsung S3C24XX family
2188 For details, take a look at <file:Documentation/cpu-freq>.
2192 config CPU_FREQ_S3C24XX_PLL
2193 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2194 depends on CPU_FREQ_S3C24XX
2196 Compile in support for changing the PLL frequency from the
2197 S3C24XX series CPUfreq driver. The PLL takes time to settle
2198 after a frequency change, so by default it is not enabled.
2200 This also means that the PLL tables for the selected CPU(s) will
2201 be built which may increase the size of the kernel image.
2203 config CPU_FREQ_S3C24XX_DEBUG
2204 bool "Debug CPUfreq Samsung driver core"
2205 depends on CPU_FREQ_S3C24XX
2207 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2209 config CPU_FREQ_S3C24XX_IODEBUG
2210 bool "Debug CPUfreq Samsung driver IO timing"
2211 depends on CPU_FREQ_S3C24XX
2213 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2215 config CPU_FREQ_S3C24XX_DEBUGFS
2216 bool "Export debugfs for CPUFreq"
2217 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2219 Export status information via debugfs.
2223 source "drivers/cpuidle/Kconfig"
2227 menu "Floating point emulation"
2229 comment "At least one emulation must be selected"
2232 bool "NWFPE math emulation"
2233 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2235 Say Y to include the NWFPE floating point emulator in the kernel.
2236 This is necessary to run most binaries. Linux does not currently
2237 support floating point hardware so you need to say Y here even if
2238 your machine has an FPA or floating point co-processor podule.
2240 You may say N here if you are going to load the Acorn FPEmulator
2241 early in the bootup.
2244 bool "Support extended precision"
2245 depends on FPE_NWFPE
2247 Say Y to include 80-bit support in the kernel floating-point
2248 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2249 Note that gcc does not generate 80-bit operations by default,
2250 so in most cases this option only enlarges the size of the
2251 floating point emulator without any good reason.
2253 You almost surely want to say N here.
2256 bool "FastFPE math emulation (EXPERIMENTAL)"
2257 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2259 Say Y here to include the FAST floating point emulator in the kernel.
2260 This is an experimental much faster emulator which now also has full
2261 precision for the mantissa. It does not support any exceptions.
2262 It is very simple, and approximately 3-6 times faster than NWFPE.
2264 It should be sufficient for most programs. It may be not suitable
2265 for scientific calculations, but you have to check this for yourself.
2266 If you do not feel you need a faster FP emulation you should better
2270 bool "VFP-format floating point maths"
2271 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2273 Say Y to include VFP support code in the kernel. This is needed
2274 if your hardware includes a VFP unit.
2276 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2277 release notes and additional status information.
2279 Say N if your target does not have VFP hardware.
2287 bool "Advanced SIMD (NEON) Extension support"
2288 depends on VFPv3 && CPU_V7
2290 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2295 menu "Userspace binary formats"
2297 source "fs/Kconfig.binfmt"
2300 tristate "RISC OS personality"
2303 Say Y here to include the kernel code necessary if you want to run
2304 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2305 experimental; if this sounds frightening, say N and sleep in peace.
2306 You can also say M here to compile this support as a module (which
2307 will be called arthur).
2311 menu "Power management options"
2313 source "kernel/power/Kconfig"
2315 config ARCH_SUSPEND_POSSIBLE
2316 depends on !ARCH_S5PC100
2317 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2318 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2321 config ARM_CPU_SUSPEND
2326 source "net/Kconfig"
2328 source "drivers/Kconfig"
2332 source "arch/arm/Kconfig.debug"
2334 source "security/Kconfig"
2336 source "crypto/Kconfig"
2338 source "lib/Kconfig"
2340 source "arch/arm/kvm/Kconfig"