4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_CMPXCHG_LOCKREF
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CLONE_BACKWARDS
13 select CPU_PM if (SUSPEND || CPU_IDLE)
14 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
15 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
16 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
17 select GENERIC_IDLE_POLL_SETUP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_SCHED_CLOCK
22 select GENERIC_SMP_IDLE_THREAD
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select HARDIRQS_SW_RESEND
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
28 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_TRACEHOOK
31 select HAVE_CONTEXT_TRACKING
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_DMA_API_DEBUG
36 select HAVE_DMA_CONTIGUOUS if MMU
37 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
38 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
39 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
40 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
41 select HAVE_GENERIC_DMA_COHERENT
42 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
43 select HAVE_IDE if PCI || ISA || PCMCIA
44 select HAVE_IRQ_TIME_ACCOUNTING
45 select HAVE_KERNEL_GZIP
46 select HAVE_KERNEL_LZ4
47 select HAVE_KERNEL_LZMA
48 select HAVE_KERNEL_LZO
50 select HAVE_KPROBES if !XIP_KERNEL
51 select HAVE_KRETPROBES if (HAVE_KPROBES)
53 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
54 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
55 select HAVE_PERF_EVENTS
57 select HAVE_PERF_USER_STACK_DUMP
58 select HAVE_REGS_AND_STACK_ACCESS_API
59 select HAVE_SYSCALL_TRACEPOINTS
61 select HAVE_VIRT_CPU_ACCOUNTING_GEN
62 select IRQ_FORCED_THREADING
64 select MODULES_USE_ELF_REL
66 select OLD_SIGSUSPEND3
67 select PERF_USE_VMALLOC
69 select SYS_SUPPORTS_APM_EMULATION
70 # Above selects are sorted alphabetically; please add new ones
71 # according to that. Thanks.
73 The ARM series is a line of low-power-consumption RISC chip designs
74 licensed by ARM Ltd and targeted at embedded applications and
75 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
76 manufactured, but legacy ARM-based PC hardware remains popular in
77 Europe. There is an ARM Linux project with a web page at
78 <http://www.arm.linux.org.uk/>.
80 config ARM_HAS_SG_CHAIN
83 config NEED_SG_DMA_LENGTH
86 config ARM_DMA_USE_IOMMU
88 select ARM_HAS_SG_CHAIN
89 select NEED_SG_DMA_LENGTH
93 config ARM_DMA_IOMMU_ALIGNMENT
94 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
98 DMA mapping framework by default aligns all buffers to the smallest
99 PAGE_SIZE order which is greater than or equal to the requested buffer
100 size. This works well for buffers up to a few hundreds kilobytes, but
101 for larger buffers it just a waste of address space. Drivers which has
102 relatively small addressing window (like 64Mib) might run out of
103 virtual space with just a few allocations.
105 With this parameter you can specify the maximum PAGE_SIZE order for
106 DMA IOMMU buffers. Larger buffers will be aligned only to this
107 specified order. The order is expressed as a power of two multiplied
115 config MIGHT_HAVE_PCI
118 config SYS_SUPPORTS_APM_EMULATION
123 select GENERIC_ALLOCATOR
134 The Extended Industry Standard Architecture (EISA) bus was
135 developed as an open alternative to the IBM MicroChannel bus.
137 The EISA bus provided some of the features of the IBM MicroChannel
138 bus while maintaining backward compatibility with cards made for
139 the older ISA bus. The EISA bus saw limited use between 1988 and
140 1995 when it was made obsolete by the PCI bus.
142 Say Y here if you are building a kernel for an EISA-based machine.
149 config STACKTRACE_SUPPORT
153 config HAVE_LATENCYTOP_SUPPORT
158 config LOCKDEP_SUPPORT
162 config TRACE_IRQFLAGS_SUPPORT
166 config RWSEM_GENERIC_SPINLOCK
170 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_CPUFREQ
182 Internal node to signify that the ARCH has CPUFREQ support
183 and that the relevant menu configurations are displayed for
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_HAS_DMA_SET_COHERENT_MASK
209 config GENERIC_ISA_DMA
215 config NEED_RET_TO_USER
223 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
224 default DRAM_BASE if REMAP_VECTORS_TO_RAM
227 The base address of exception vectors. This must be two pages
230 config ARM_PATCH_PHYS_VIRT
231 bool "Patch physical to virtual translations at runtime" if EMBEDDED
233 depends on !XIP_KERNEL && MMU
234 depends on !ARCH_REALVIEW || !SPARSEMEM
236 Patch phys-to-virt and virt-to-phys translation functions at
237 boot and module load time according to the position of the
238 kernel in system memory.
240 This can only be used with non-XIP MMU kernels where the base
241 of physical memory is at a 16MB boundary.
243 Only disable this option if you know that you do not require
244 this feature (eg, building a kernel for a single machine) and
245 you need to shrink the kernel to the minimal size.
247 config NEED_MACH_GPIO_H
250 Select this when mach/gpio.h is required to provide special
251 definitions for this platform. The need for mach/gpio.h should
252 be avoided when possible.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
271 default DRAM_BASE if !MMU
273 Please provide the physical address corresponding to the
274 location of main memory in your system.
280 source "init/Kconfig"
282 source "kernel/Kconfig.freezer"
287 bool "MMU-based Paged Memory Management Support"
290 Select if you want MMU-based virtualised addressing space
291 support by paged memory management. If unsure, say 'Y'.
294 # The "ARM system type" choice list is ordered alphabetically by option
295 # text. Please add new entries in the option alphabetic order.
298 prompt "ARM system type"
299 default ARCH_VERSATILE if !MMU
300 default ARCH_MULTIPLATFORM if MMU
302 config ARCH_MULTIPLATFORM
303 bool "Allow multiple platforms to be selected"
305 select ARM_PATCH_PHYS_VIRT
308 select MULTI_IRQ_HANDLER
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
314 select ARCH_HAS_CPUFREQ
317 select COMMON_CLK_VERSATILE
318 select GENERIC_CLOCKEVENTS
321 select MULTI_IRQ_HANDLER
322 select NEED_MACH_MEMORY_H
323 select PLAT_VERSATILE
326 select VERSATILE_FPGA_IRQ
328 Support for ARM's Integrator platform.
331 bool "ARM Ltd. RealView family"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_TIMER_SP804
336 select COMMON_CLK_VERSATILE
337 select GENERIC_CLOCKEVENTS
338 select GPIO_PL061 if GPIOLIB
340 select NEED_MACH_MEMORY_H
341 select PLAT_VERSATILE
342 select PLAT_VERSATILE_CLCD
344 This enables support for ARM Ltd RealView boards.
346 config ARCH_VERSATILE
347 bool "ARM Ltd. Versatile family"
348 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
354 select HAVE_MACH_CLKDEV
356 select PLAT_VERSATILE
357 select PLAT_VERSATILE_CLCD
358 select PLAT_VERSATILE_CLOCK
359 select VERSATILE_FPGA_IRQ
361 This enables support for ARM Ltd Versatile board.
365 select ARCH_REQUIRE_GPIOLIB
368 select NEED_MACH_GPIO_H
369 select NEED_MACH_IO_H if PCCARD
371 select PINCTRL_AT91 if USE_OF
373 This enables support for systems based on Atmel
374 AT91RM9200 and AT91SAM9* processors.
377 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
378 select ARCH_REQUIRE_GPIOLIB
383 select GENERIC_CLOCKEVENTS
385 select MULTI_IRQ_HANDLER
388 Support for Cirrus Logic 711x/721x/731x based boards.
391 bool "Cortina Systems Gemini"
392 select ARCH_REQUIRE_GPIOLIB
395 select GENERIC_CLOCKEVENTS
397 Support for the Cortina Systems Gemini family SoCs
401 select ARCH_USES_GETTIMEOFFSET
404 select NEED_MACH_IO_H
405 select NEED_MACH_MEMORY_H
408 This is an evaluation board for the StrongARM processor available
409 from Digital. It has limited hardware on-board, including an
410 Ethernet interface, two PCMCIA sockets, two serial ports and a
415 select ARCH_HAS_HOLES_MEMORYMODEL
416 select ARCH_REQUIRE_GPIOLIB
417 select ARCH_USES_GETTIMEOFFSET
422 select NEED_MACH_MEMORY_H
424 This enables support for the Cirrus EP93xx series of CPUs.
426 config ARCH_FOOTBRIDGE
430 select GENERIC_CLOCKEVENTS
432 select NEED_MACH_IO_H if !MMU
433 select NEED_MACH_MEMORY_H
435 Support for systems based on the DC21285 companion chip
436 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
439 bool "Hilscher NetX based"
443 select GENERIC_CLOCKEVENTS
445 This enables support for systems based on the Hilscher NetX Soc
451 select NEED_MACH_MEMORY_H
452 select NEED_RET_TO_USER
457 Support for Intel's IOP13XX (XScale) family of processors.
462 select ARCH_REQUIRE_GPIOLIB
465 select NEED_RET_TO_USER
469 Support for Intel's 80219 and IOP32X (XScale) family of
475 select ARCH_REQUIRE_GPIOLIB
478 select NEED_RET_TO_USER
482 Support for Intel's IOP33X (XScale) family of processors.
487 select ARCH_HAS_DMA_SET_COHERENT_MASK
488 select ARCH_SUPPORTS_BIG_ENDIAN
489 select ARCH_REQUIRE_GPIOLIB
492 select DMABOUNCE if PCI
493 select GENERIC_CLOCKEVENTS
494 select MIGHT_HAVE_PCI
495 select NEED_MACH_IO_H
496 select USB_EHCI_BIG_ENDIAN_DESC
497 select USB_EHCI_BIG_ENDIAN_MMIO
499 Support for Intel's IXP4XX (XScale) family of processors.
503 select ARCH_REQUIRE_GPIOLIB
505 select GENERIC_CLOCKEVENTS
506 select MIGHT_HAVE_PCI
510 select PLAT_ORION_LEGACY
511 select USB_ARCH_HAS_EHCI
513 Support for the Marvell Dove SoC 88AP510
516 bool "Marvell Kirkwood"
517 select ARCH_HAS_CPUFREQ
518 select ARCH_REQUIRE_GPIOLIB
520 select GENERIC_CLOCKEVENTS
525 select PINCTRL_KIRKWOOD
526 select PLAT_ORION_LEGACY
528 Support for the following Marvell Kirkwood series SoCs:
529 88F6180, 88F6192 and 88F6281.
532 bool "Marvell MV78xx0"
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
538 select PLAT_ORION_LEGACY
540 Support for the following Marvell MV78xx0 series SoCs:
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
551 select PLAT_ORION_LEGACY
553 Support for the following Marvell Orion 5x series SoCs:
554 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
555 Orion-2 (5281), Orion-1-90 (6183).
558 bool "Marvell PXA168/910/MMP2"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_ALLOCATOR
563 select GENERIC_CLOCKEVENTS
566 select MULTI_IRQ_HANDLER
571 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
574 bool "Micrel/Kendin KS8695"
575 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
579 select NEED_MACH_MEMORY_H
581 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
582 System-on-Chip devices.
585 bool "Nuvoton W90X900 CPU"
586 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
592 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
593 At present, the w90x900 has been renamed nuc900, regarding
594 the ARM series product line, you can login the following
595 link address to know more.
597 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
598 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
602 select ARCH_REQUIRE_GPIOLIB
607 select GENERIC_CLOCKEVENTS
610 select USB_ARCH_HAS_OHCI
613 Support for the NXP LPC32XX family of processors
616 bool "PXA2xx/PXA3xx-based"
618 select ARCH_HAS_CPUFREQ
620 select ARCH_REQUIRE_GPIOLIB
621 select ARM_CPU_SUSPEND if PM
625 select GENERIC_CLOCKEVENTS
628 select MULTI_IRQ_HANDLER
632 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
636 select ARCH_REQUIRE_GPIOLIB
637 select CLKSRC_OF if OF
639 select GENERIC_CLOCKEVENTS
641 Support for Qualcomm MSM/QSD based systems. This runs on the
642 apps processor of the MSM/QSD and depends on a shared memory
643 interface to the modem processor which runs the baseband
644 stack and controls some vital subsystems
645 (clock and power control, etc).
648 bool "Renesas SH-Mobile / R-Mobile"
649 select ARM_PATCH_PHYS_VIRT
651 select GENERIC_CLOCKEVENTS
652 select HAVE_ARM_SCU if SMP
653 select HAVE_ARM_TWD if SMP
654 select HAVE_MACH_CLKDEV
656 select MIGHT_HAVE_CACHE_L2X0
657 select MULTI_IRQ_HANDLER
660 select PM_GENERIC_DOMAINS if PM
663 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
668 select ARCH_MAY_HAVE_PC_FDC
669 select ARCH_SPARSEMEM_ENABLE
670 select ARCH_USES_GETTIMEOFFSET
673 select HAVE_PATA_PLATFORM
675 select NEED_MACH_IO_H
676 select NEED_MACH_MEMORY_H
680 On the Acorn Risc-PC, Linux can support the internal IDE disk and
681 CD-ROM interface, serial and parallel port, and the floppy drive.
685 select ARCH_HAS_CPUFREQ
687 select ARCH_REQUIRE_GPIOLIB
688 select ARCH_SPARSEMEM_ENABLE
693 select GENERIC_CLOCKEVENTS
696 select NEED_MACH_MEMORY_H
699 Support for StrongARM 11x0 based boards.
702 bool "Samsung S3C24XX SoCs"
703 select ARCH_HAS_CPUFREQ
704 select ARCH_REQUIRE_GPIOLIB
706 select CLKSRC_SAMSUNG_PWM
707 select GENERIC_CLOCKEVENTS
709 select HAVE_S3C2410_I2C if I2C
710 select HAVE_S3C2410_WATCHDOG if WATCHDOG
711 select HAVE_S3C_RTC if RTC_CLASS
712 select MULTI_IRQ_HANDLER
713 select NEED_MACH_IO_H
716 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
717 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
718 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
719 Samsung SMDK2410 development board (and derivatives).
722 bool "Samsung S3C64XX"
723 select ARCH_HAS_CPUFREQ
724 select ARCH_REQUIRE_GPIOLIB
727 select CLKSRC_SAMSUNG_PWM
730 select GENERIC_CLOCKEVENTS
732 select HAVE_S3C2410_I2C if I2C
733 select HAVE_S3C2410_WATCHDOG if WATCHDOG
737 select PM_GENERIC_DOMAINS
739 select S3C_GPIO_TRACK
741 select SAMSUNG_GPIOLIB_4BIT
742 select SAMSUNG_WAKEMASK
743 select SAMSUNG_WDT_RESET
744 select USB_ARCH_HAS_OHCI
746 Samsung S3C64XX series based systems
749 bool "Samsung S5P6440 S5P6450"
751 select CLKSRC_SAMSUNG_PWM
753 select GENERIC_CLOCKEVENTS
755 select HAVE_S3C2410_I2C if I2C
756 select HAVE_S3C2410_WATCHDOG if WATCHDOG
757 select HAVE_S3C_RTC if RTC_CLASS
758 select NEED_MACH_GPIO_H
760 select SAMSUNG_WDT_RESET
762 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
766 bool "Samsung S5PC100"
767 select ARCH_REQUIRE_GPIOLIB
769 select CLKSRC_SAMSUNG_PWM
771 select GENERIC_CLOCKEVENTS
773 select HAVE_S3C2410_I2C if I2C
774 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 select HAVE_S3C_RTC if RTC_CLASS
776 select NEED_MACH_GPIO_H
778 select SAMSUNG_WDT_RESET
780 Samsung S5PC100 series based systems
783 bool "Samsung S5PV210/S5PC110"
784 select ARCH_HAS_CPUFREQ
785 select ARCH_HAS_HOLES_MEMORYMODEL
786 select ARCH_SPARSEMEM_ENABLE
788 select CLKSRC_SAMSUNG_PWM
790 select GENERIC_CLOCKEVENTS
792 select HAVE_S3C2410_I2C if I2C
793 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 select HAVE_S3C_RTC if RTC_CLASS
795 select NEED_MACH_GPIO_H
796 select NEED_MACH_MEMORY_H
799 Samsung S5PV210/S5PC110 series based systems
802 bool "Samsung EXYNOS"
803 select ARCH_HAS_CPUFREQ
804 select ARCH_HAS_HOLES_MEMORYMODEL
805 select ARCH_REQUIRE_GPIOLIB
806 select ARCH_SPARSEMEM_ENABLE
810 select GENERIC_CLOCKEVENTS
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C2410_WATCHDOG if WATCHDOG
813 select HAVE_S3C_RTC if RTC_CLASS
814 select NEED_MACH_MEMORY_H
818 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
822 select ARCH_HAS_HOLES_MEMORYMODEL
823 select ARCH_REQUIRE_GPIOLIB
825 select GENERIC_ALLOCATOR
826 select GENERIC_CLOCKEVENTS
827 select GENERIC_IRQ_CHIP
833 Support for TI's DaVinci platform.
838 select ARCH_HAS_CPUFREQ
839 select ARCH_HAS_HOLES_MEMORYMODEL
841 select ARCH_REQUIRE_GPIOLIB
844 select GENERIC_CLOCKEVENTS
845 select GENERIC_IRQ_CHIP
848 select NEED_MACH_IO_H if PCCARD
849 select NEED_MACH_MEMORY_H
851 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
855 menu "Multiple platform selection"
856 depends on ARCH_MULTIPLATFORM
858 comment "CPU Core family selection"
860 config ARCH_MULTI_V4T
861 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
862 depends on !ARCH_MULTI_V6_V7
863 select ARCH_MULTI_V4_V5
864 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
865 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
866 CPU_ARM925T || CPU_ARM940T)
869 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
870 depends on !ARCH_MULTI_V6_V7
871 select ARCH_MULTI_V4_V5
872 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
873 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
874 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
876 config ARCH_MULTI_V4_V5
880 bool "ARMv6 based platforms (ARM11)"
881 select ARCH_MULTI_V6_V7
885 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
887 select ARCH_MULTI_V6_V7
890 config ARCH_MULTI_V6_V7
893 config ARCH_MULTI_CPU_AUTO
894 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
900 # This is sorted alphabetically by mach-* pathname. However, plat-*
901 # Kconfigs may be included either alphabetically (according to the
902 # plat- suffix) or along side the corresponding mach-* source.
904 source "arch/arm/mach-mvebu/Kconfig"
906 source "arch/arm/mach-at91/Kconfig"
908 source "arch/arm/mach-bcm/Kconfig"
910 source "arch/arm/mach-bcm2835/Kconfig"
912 source "arch/arm/mach-clps711x/Kconfig"
914 source "arch/arm/mach-cns3xxx/Kconfig"
916 source "arch/arm/mach-davinci/Kconfig"
918 source "arch/arm/mach-dove/Kconfig"
920 source "arch/arm/mach-ep93xx/Kconfig"
922 source "arch/arm/mach-footbridge/Kconfig"
924 source "arch/arm/mach-gemini/Kconfig"
926 source "arch/arm/mach-highbank/Kconfig"
928 source "arch/arm/mach-integrator/Kconfig"
930 source "arch/arm/mach-iop32x/Kconfig"
932 source "arch/arm/mach-iop33x/Kconfig"
934 source "arch/arm/mach-iop13xx/Kconfig"
936 source "arch/arm/mach-ixp4xx/Kconfig"
938 source "arch/arm/mach-keystone/Kconfig"
940 source "arch/arm/mach-kirkwood/Kconfig"
942 source "arch/arm/mach-ks8695/Kconfig"
944 source "arch/arm/mach-msm/Kconfig"
946 source "arch/arm/mach-mv78xx0/Kconfig"
948 source "arch/arm/mach-imx/Kconfig"
950 source "arch/arm/mach-mxs/Kconfig"
952 source "arch/arm/mach-netx/Kconfig"
954 source "arch/arm/mach-nomadik/Kconfig"
956 source "arch/arm/mach-nspire/Kconfig"
958 source "arch/arm/plat-omap/Kconfig"
960 source "arch/arm/mach-omap1/Kconfig"
962 source "arch/arm/mach-omap2/Kconfig"
964 source "arch/arm/mach-orion5x/Kconfig"
966 source "arch/arm/mach-picoxcell/Kconfig"
968 source "arch/arm/mach-pxa/Kconfig"
969 source "arch/arm/plat-pxa/Kconfig"
971 source "arch/arm/mach-mmp/Kconfig"
973 source "arch/arm/mach-realview/Kconfig"
975 source "arch/arm/mach-rockchip/Kconfig"
977 source "arch/arm/mach-sa1100/Kconfig"
979 source "arch/arm/plat-samsung/Kconfig"
981 source "arch/arm/mach-socfpga/Kconfig"
983 source "arch/arm/mach-spear/Kconfig"
985 source "arch/arm/mach-sti/Kconfig"
987 source "arch/arm/mach-s3c24xx/Kconfig"
989 source "arch/arm/mach-s3c64xx/Kconfig"
991 source "arch/arm/mach-s5p64x0/Kconfig"
993 source "arch/arm/mach-s5pc100/Kconfig"
995 source "arch/arm/mach-s5pv210/Kconfig"
997 source "arch/arm/mach-exynos/Kconfig"
999 source "arch/arm/mach-shmobile/Kconfig"
1001 source "arch/arm/mach-sunxi/Kconfig"
1003 source "arch/arm/mach-prima2/Kconfig"
1005 source "arch/arm/mach-tegra/Kconfig"
1007 source "arch/arm/mach-u300/Kconfig"
1009 source "arch/arm/mach-ux500/Kconfig"
1011 source "arch/arm/mach-versatile/Kconfig"
1013 source "arch/arm/mach-vexpress/Kconfig"
1014 source "arch/arm/plat-versatile/Kconfig"
1016 source "arch/arm/mach-virt/Kconfig"
1018 source "arch/arm/mach-vt8500/Kconfig"
1020 source "arch/arm/mach-w90x900/Kconfig"
1022 source "arch/arm/mach-zynq/Kconfig"
1024 # Definitions to make life easier
1030 select GENERIC_CLOCKEVENTS
1036 select GENERIC_IRQ_CHIP
1039 config PLAT_ORION_LEGACY
1046 config PLAT_VERSATILE
1049 config ARM_TIMER_SP804
1052 select CLKSRC_OF if OF
1054 source arch/arm/mm/Kconfig
1058 default 16 if ARCH_EP93XX
1062 bool "Enable iWMMXt support" if !CPU_PJ4
1063 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1064 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1066 Enable support for iWMMXt context switching at run time if
1067 running on a CPU that supports it.
1069 config MULTI_IRQ_HANDLER
1072 Allow each machine to specify it's own IRQ handler at run time.
1075 source "arch/arm/Kconfig-nommu"
1078 config PJ4B_ERRATA_4742
1079 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1080 depends on CPU_PJ4B && MACH_ARMADA_370
1083 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1084 Event (WFE) IDLE states, a specific timing sensitivity exists between
1085 the retiring WFI/WFE instructions and the newly issued subsequent
1086 instructions. This sensitivity can result in a CPU hang scenario.
1088 The software must insert either a Data Synchronization Barrier (DSB)
1089 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1092 config ARM_ERRATA_326103
1093 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1096 Executing a SWP instruction to read-only memory does not set bit 11
1097 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1098 treat the access as a read, preventing a COW from occurring and
1099 causing the faulting task to livelock.
1101 config ARM_ERRATA_411920
1102 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1103 depends on CPU_V6 || CPU_V6K
1105 Invalidation of the Instruction Cache operation can
1106 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1107 It does not affect the MPCore. This option enables the ARM Ltd.
1108 recommended workaround.
1110 config ARM_ERRATA_430973
1111 bool "ARM errata: Stale prediction on replaced interworking branch"
1114 This option enables the workaround for the 430973 Cortex-A8
1115 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1116 interworking branch is replaced with another code sequence at the
1117 same virtual address, whether due to self-modifying code or virtual
1118 to physical address re-mapping, Cortex-A8 does not recover from the
1119 stale interworking branch prediction. This results in Cortex-A8
1120 executing the new code sequence in the incorrect ARM or Thumb state.
1121 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1122 and also flushes the branch target cache at every context switch.
1123 Note that setting specific bits in the ACTLR register may not be
1124 available in non-secure mode.
1126 config ARM_ERRATA_458693
1127 bool "ARM errata: Processor deadlock when a false hazard is created"
1129 depends on !ARCH_MULTIPLATFORM
1131 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1132 erratum. For very specific sequences of memory operations, it is
1133 possible for a hazard condition intended for a cache line to instead
1134 be incorrectly associated with a different cache line. This false
1135 hazard might then cause a processor deadlock. The workaround enables
1136 the L1 caching of the NEON accesses and disables the PLD instruction
1137 in the ACTLR register. Note that setting specific bits in the ACTLR
1138 register may not be available in non-secure mode.
1140 config ARM_ERRATA_460075
1141 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1143 depends on !ARCH_MULTIPLATFORM
1145 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1146 erratum. Any asynchronous access to the L2 cache may encounter a
1147 situation in which recent store transactions to the L2 cache are lost
1148 and overwritten with stale memory contents from external memory. The
1149 workaround disables the write-allocate mode for the L2 cache via the
1150 ACTLR register. Note that setting specific bits in the ACTLR register
1151 may not be available in non-secure mode.
1153 config ARM_ERRATA_742230
1154 bool "ARM errata: DMB operation may be faulty"
1155 depends on CPU_V7 && SMP
1156 depends on !ARCH_MULTIPLATFORM
1158 This option enables the workaround for the 742230 Cortex-A9
1159 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1160 between two write operations may not ensure the correct visibility
1161 ordering of the two writes. This workaround sets a specific bit in
1162 the diagnostic register of the Cortex-A9 which causes the DMB
1163 instruction to behave as a DSB, ensuring the correct behaviour of
1166 config ARM_ERRATA_742231
1167 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1168 depends on CPU_V7 && SMP
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 742231 Cortex-A9
1172 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1173 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1174 accessing some data located in the same cache line, may get corrupted
1175 data due to bad handling of the address hazard when the line gets
1176 replaced from one of the CPUs at the same time as another CPU is
1177 accessing it. This workaround sets specific bits in the diagnostic
1178 register of the Cortex-A9 which reduces the linefill issuing
1179 capabilities of the processor.
1181 config PL310_ERRATA_588369
1182 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1183 depends on CACHE_L2X0
1185 The PL310 L2 cache controller implements three types of Clean &
1186 Invalidate maintenance operations: by Physical Address
1187 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1188 They are architecturally defined to behave as the execution of a
1189 clean operation followed immediately by an invalidate operation,
1190 both performing to the same memory location. This functionality
1191 is not correctly implemented in PL310 as clean lines are not
1192 invalidated as a result of these operations.
1194 config ARM_ERRATA_643719
1195 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1196 depends on CPU_V7 && SMP
1198 This option enables the workaround for the 643719 Cortex-A9 (prior to
1199 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1200 register returns zero when it should return one. The workaround
1201 corrects this value, ensuring cache maintenance operations which use
1202 it behave as intended and avoiding data corruption.
1204 config ARM_ERRATA_720789
1205 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1208 This option enables the workaround for the 720789 Cortex-A9 (prior to
1209 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1210 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1211 As a consequence of this erratum, some TLB entries which should be
1212 invalidated are not, resulting in an incoherency in the system page
1213 tables. The workaround changes the TLB flushing routines to invalidate
1214 entries regardless of the ASID.
1216 config PL310_ERRATA_727915
1217 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1218 depends on CACHE_L2X0
1220 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1221 operation (offset 0x7FC). This operation runs in background so that
1222 PL310 can handle normal accesses while it is in progress. Under very
1223 rare circumstances, due to this erratum, write data can be lost when
1224 PL310 treats a cacheable write transaction during a Clean &
1225 Invalidate by Way operation.
1227 config ARM_ERRATA_743622
1228 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1230 depends on !ARCH_MULTIPLATFORM
1232 This option enables the workaround for the 743622 Cortex-A9
1233 (r2p*) erratum. Under very rare conditions, a faulty
1234 optimisation in the Cortex-A9 Store Buffer may lead to data
1235 corruption. This workaround sets a specific bit in the diagnostic
1236 register of the Cortex-A9 which disables the Store Buffer
1237 optimisation, preventing the defect from occurring. This has no
1238 visible impact on the overall performance or power consumption of the
1241 config ARM_ERRATA_751472
1242 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1244 depends on !ARCH_MULTIPLATFORM
1246 This option enables the workaround for the 751472 Cortex-A9 (prior
1247 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1248 completion of a following broadcasted operation if the second
1249 operation is received by a CPU before the ICIALLUIS has completed,
1250 potentially leading to corrupted entries in the cache or TLB.
1252 config PL310_ERRATA_753970
1253 bool "PL310 errata: cache sync operation may be faulty"
1254 depends on CACHE_PL310
1256 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1258 Under some condition the effect of cache sync operation on
1259 the store buffer still remains when the operation completes.
1260 This means that the store buffer is always asked to drain and
1261 this prevents it from merging any further writes. The workaround
1262 is to replace the normal offset of cache sync operation (0x730)
1263 by another offset targeting an unmapped PL310 register 0x740.
1264 This has the same effect as the cache sync operation: store buffer
1265 drain and waiting for all buffers empty.
1267 config ARM_ERRATA_754322
1268 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1271 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1272 r3p*) erratum. A speculative memory access may cause a page table walk
1273 which starts prior to an ASID switch but completes afterwards. This
1274 can populate the micro-TLB with a stale entry which may be hit with
1275 the new ASID. This workaround places two dsb instructions in the mm
1276 switching code so that no page table walks can cross the ASID switch.
1278 config ARM_ERRATA_754327
1279 bool "ARM errata: no automatic Store Buffer drain"
1280 depends on CPU_V7 && SMP
1282 This option enables the workaround for the 754327 Cortex-A9 (prior to
1283 r2p0) erratum. The Store Buffer does not have any automatic draining
1284 mechanism and therefore a livelock may occur if an external agent
1285 continuously polls a memory location waiting to observe an update.
1286 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1287 written polling loops from denying visibility of updates to memory.
1289 config ARM_ERRATA_364296
1290 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1293 This options enables the workaround for the 364296 ARM1136
1294 r0p2 erratum (possible cache data corruption with
1295 hit-under-miss enabled). It sets the undocumented bit 31 in
1296 the auxiliary control register and the FI bit in the control
1297 register, thus disabling hit-under-miss without putting the
1298 processor into full low interrupt latency mode. ARM11MPCore
1301 config ARM_ERRATA_764369
1302 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1303 depends on CPU_V7 && SMP
1305 This option enables the workaround for erratum 764369
1306 affecting Cortex-A9 MPCore with two or more processors (all
1307 current revisions). Under certain timing circumstances, a data
1308 cache line maintenance operation by MVA targeting an Inner
1309 Shareable memory region may fail to proceed up to either the
1310 Point of Coherency or to the Point of Unification of the
1311 system. This workaround adds a DSB instruction before the
1312 relevant cache maintenance functions and sets a specific bit
1313 in the diagnostic control register of the SCU.
1315 config PL310_ERRATA_769419
1316 bool "PL310 errata: no automatic Store Buffer drain"
1317 depends on CACHE_L2X0
1319 On revisions of the PL310 prior to r3p2, the Store Buffer does
1320 not automatically drain. This can cause normal, non-cacheable
1321 writes to be retained when the memory system is idle, leading
1322 to suboptimal I/O performance for drivers using coherent DMA.
1323 This option adds a write barrier to the cpu_idle loop so that,
1324 on systems with an outer cache, the store buffer is drained
1327 config ARM_ERRATA_775420
1328 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1331 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1332 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1333 operation aborts with MMU exception, it might cause the processor
1334 to deadlock. This workaround puts DSB before executing ISB if
1335 an abort may occur on cache maintenance.
1337 config ARM_ERRATA_798181
1338 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1339 depends on CPU_V7 && SMP
1341 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1342 adequately shooting down all use of the old entries. This
1343 option enables the Linux kernel workaround for this erratum
1344 which sends an IPI to the CPUs that are running the same ASID
1345 as the one being invalidated.
1347 config ARM_ERRATA_773022
1348 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1351 This option enables the workaround for the 773022 Cortex-A15
1352 (up to r0p4) erratum. In certain rare sequences of code, the
1353 loop buffer may deliver incorrect instructions. This
1354 workaround disables the loop buffer to avoid the erratum.
1358 source "arch/arm/common/Kconfig"
1368 Find out whether you have ISA slots on your motherboard. ISA is the
1369 name of a bus system, i.e. the way the CPU talks to the other stuff
1370 inside your box. Other bus systems are PCI, EISA, MicroChannel
1371 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1372 newer boards don't support it. If you have ISA, say Y, otherwise N.
1374 # Select ISA DMA controller support
1379 # Select ISA DMA interface
1384 bool "PCI support" if MIGHT_HAVE_PCI
1386 Find out whether you have a PCI motherboard. PCI is the name of a
1387 bus system, i.e. the way the CPU talks to the other stuff inside
1388 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1389 VESA. If you have PCI, say Y, otherwise N.
1395 config PCI_NANOENGINE
1396 bool "BSE nanoEngine PCI support"
1397 depends on SA1100_NANOENGINE
1399 Enable PCI on the BSE nanoEngine board.
1404 config PCI_HOST_ITE8152
1406 depends on PCI && MACH_ARMCORE
1410 source "drivers/pci/Kconfig"
1411 source "drivers/pci/pcie/Kconfig"
1413 source "drivers/pcmcia/Kconfig"
1417 menu "Kernel Features"
1422 This option should be selected by machines which have an SMP-
1425 The only effect of this option is to make the SMP-related
1426 options available to the user for configuration.
1429 bool "Symmetric Multi-Processing"
1430 depends on CPU_V6K || CPU_V7
1431 depends on GENERIC_CLOCKEVENTS
1433 depends on MMU || ARM_MPU
1435 This enables support for systems with more than one CPU. If you have
1436 a system with only one CPU, like most personal computers, say N. If
1437 you have a system with more than one CPU, say Y.
1439 If you say N here, the kernel will run on single and multiprocessor
1440 machines, but will use only one CPU of a multiprocessor machine. If
1441 you say Y here, the kernel will run on many, but not all, single
1442 processor machines. On a single processor machine, the kernel will
1443 run faster if you say N here.
1445 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1446 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1447 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1449 If you don't know what to do here, say N.
1452 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1453 depends on SMP && !XIP_KERNEL && MMU
1456 SMP kernels contain instructions which fail on non-SMP processors.
1457 Enabling this option allows the kernel to modify itself to make
1458 these instructions safe. Disabling it allows about 1K of space
1461 If you don't know what to do here, say Y.
1463 config ARM_CPU_TOPOLOGY
1464 bool "Support cpu topology definition"
1465 depends on SMP && CPU_V7
1468 Support ARM cpu topology definition. The MPIDR register defines
1469 affinity between processors which is then used to describe the cpu
1470 topology of an ARM System.
1473 bool "Multi-core scheduler support"
1474 depends on ARM_CPU_TOPOLOGY
1476 Multi-core scheduler support improves the CPU scheduler's decision
1477 making when dealing with multi-core CPU chips at a cost of slightly
1478 increased overhead in some places. If unsure say N here.
1481 bool "SMT scheduler support"
1482 depends on ARM_CPU_TOPOLOGY
1484 Improves the CPU scheduler's decision making when dealing with
1485 MultiThreading at a cost of slightly increased overhead in some
1486 places. If unsure say N here.
1491 This option enables support for the ARM system coherency unit
1493 config HAVE_ARM_ARCH_TIMER
1494 bool "Architected timer support"
1496 select ARM_ARCH_TIMER
1497 select GENERIC_CLOCKEVENTS
1499 This option enables support for the ARM architected timer
1504 select CLKSRC_OF if OF
1506 This options enables support for the ARM timer and watchdog unit
1509 bool "Multi-Cluster Power Management"
1510 depends on CPU_V7 && SMP
1512 This option provides the common power management infrastructure
1513 for (multi-)cluster based systems, such as big.LITTLE based
1517 bool "big.LITTLE support (Experimental)"
1518 depends on CPU_V7 && SMP
1521 This option enables support selections for the big.LITTLE
1522 system architecture.
1525 bool "big.LITTLE switcher support"
1526 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1528 select ARM_CPU_SUSPEND
1530 The big.LITTLE "switcher" provides the core functionality to
1531 transparently handle transition between a cluster of A15's
1532 and a cluster of A7's in a big.LITTLE system.
1534 config BL_SWITCHER_DUMMY_IF
1535 tristate "Simple big.LITTLE switcher user interface"
1536 depends on BL_SWITCHER && DEBUG_KERNEL
1538 This is a simple and dummy char dev interface to control
1539 the big.LITTLE switcher core code. It is meant for
1540 debugging purposes only.
1543 prompt "Memory split"
1546 Select the desired split between kernel and user memory.
1548 If you are not absolutely sure what you are doing, leave this
1552 bool "3G/1G user/kernel split"
1554 bool "2G/2G user/kernel split"
1556 bool "1G/3G user/kernel split"
1561 default 0x40000000 if VMSPLIT_1G
1562 default 0x80000000 if VMSPLIT_2G
1566 int "Maximum number of CPUs (2-32)"
1572 bool "Support for hot-pluggable CPUs"
1575 Say Y here to experiment with turning CPUs off and on. CPUs
1576 can be controlled through /sys/devices/system/cpu.
1579 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1582 Say Y here if you want Linux to communicate with system firmware
1583 implementing the PSCI specification for CPU-centric power
1584 management operations described in ARM document number ARM DEN
1585 0022A ("Power State Coordination Interface System Software on
1588 # The GPIO number here must be sorted by descending number. In case of
1589 # a multiplatform kernel, we just want the highest value required by the
1590 # selected platforms.
1593 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1594 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1595 default 392 if ARCH_U8500
1596 default 352 if ARCH_VT8500
1597 default 288 if ARCH_SUNXI
1598 default 264 if MACH_H4700
1601 Maximum number of GPIOs in the system.
1603 If unsure, leave the default value.
1605 source kernel/Kconfig.preempt
1609 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1610 ARCH_S5PV210 || ARCH_EXYNOS4
1611 default AT91_TIMER_HZ if ARCH_AT91
1612 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1616 depends on HZ_FIXED = 0
1617 prompt "Timer frequency"
1641 default HZ_FIXED if HZ_FIXED != 0
1642 default 100 if HZ_100
1643 default 200 if HZ_200
1644 default 250 if HZ_250
1645 default 300 if HZ_300
1646 default 500 if HZ_500
1650 def_bool HIGH_RES_TIMERS
1653 def_bool HIGH_RES_TIMERS
1655 config THUMB2_KERNEL
1656 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1657 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1658 default y if CPU_THUMBONLY
1660 select ARM_ASM_UNIFIED
1663 By enabling this option, the kernel will be compiled in
1664 Thumb-2 mode. A compiler/assembler that understand the unified
1665 ARM-Thumb syntax is needed.
1669 config THUMB2_AVOID_R_ARM_THM_JUMP11
1670 bool "Work around buggy Thumb-2 short branch relocations in gas"
1671 depends on THUMB2_KERNEL && MODULES
1674 Various binutils versions can resolve Thumb-2 branches to
1675 locally-defined, preemptible global symbols as short-range "b.n"
1676 branch instructions.
1678 This is a problem, because there's no guarantee the final
1679 destination of the symbol, or any candidate locations for a
1680 trampoline, are within range of the branch. For this reason, the
1681 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1682 relocation in modules at all, and it makes little sense to add
1685 The symptom is that the kernel fails with an "unsupported
1686 relocation" error when loading some modules.
1688 Until fixed tools are available, passing
1689 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1690 code which hits this problem, at the cost of a bit of extra runtime
1691 stack usage in some cases.
1693 The problem is described in more detail at:
1694 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1696 Only Thumb-2 kernels are affected.
1698 Unless you are sure your tools don't have this problem, say Y.
1700 config ARM_ASM_UNIFIED
1704 bool "Use the ARM EABI to compile the kernel"
1706 This option allows for the kernel to be compiled using the latest
1707 ARM ABI (aka EABI). This is only useful if you are using a user
1708 space environment that is also compiled with EABI.
1710 Since there are major incompatibilities between the legacy ABI and
1711 EABI, especially with regard to structure member alignment, this
1712 option also changes the kernel syscall calling convention to
1713 disambiguate both ABIs and allow for backward compatibility support
1714 (selected with CONFIG_OABI_COMPAT).
1716 To use this you need GCC version 4.0.0 or later.
1719 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1720 depends on AEABI && !THUMB2_KERNEL
1722 This option preserves the old syscall interface along with the
1723 new (ARM EABI) one. It also provides a compatibility layer to
1724 intercept syscalls that have structure arguments which layout
1725 in memory differs between the legacy ABI and the new ARM EABI
1726 (only for non "thumb" binaries). This option adds a tiny
1727 overhead to all syscalls and produces a slightly larger kernel.
1729 The seccomp filter system will not be available when this is
1730 selected, since there is no way yet to sensibly distinguish
1731 between calling conventions during filtering.
1733 If you know you'll be using only pure EABI user space then you
1734 can say N here. If this option is not selected and you attempt
1735 to execute a legacy ABI binary then the result will be
1736 UNPREDICTABLE (in fact it can be predicted that it won't work
1737 at all). If in doubt say N.
1739 config ARCH_HAS_HOLES_MEMORYMODEL
1742 config ARCH_SPARSEMEM_ENABLE
1745 config ARCH_SPARSEMEM_DEFAULT
1746 def_bool ARCH_SPARSEMEM_ENABLE
1748 config ARCH_SELECT_MEMORY_MODEL
1749 def_bool ARCH_SPARSEMEM_ENABLE
1751 config HAVE_ARCH_PFN_VALID
1752 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1755 bool "High Memory Support"
1758 The address space of ARM processors is only 4 Gigabytes large
1759 and it has to accommodate user address space, kernel address
1760 space as well as some memory mapped IO. That means that, if you
1761 have a large amount of physical memory and/or IO, not all of the
1762 memory can be "permanently mapped" by the kernel. The physical
1763 memory that is not permanently mapped is called "high memory".
1765 Depending on the selected kernel/user memory split, minimum
1766 vmalloc space and actual amount of RAM, you may not need this
1767 option which should result in a slightly faster kernel.
1772 bool "Allocate 2nd-level pagetables from highmem"
1775 config HW_PERF_EVENTS
1776 bool "Enable hardware performance counter support for perf events"
1777 depends on PERF_EVENTS
1780 Enable hardware performance counter support for perf events. If
1781 disabled, perf events will use software events only.
1783 config SYS_SUPPORTS_HUGETLBFS
1787 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1791 config ARCH_WANT_GENERAL_HUGETLB
1796 config FORCE_MAX_ZONEORDER
1797 int "Maximum zone order" if ARCH_SHMOBILE
1798 range 11 64 if ARCH_SHMOBILE
1799 default "12" if SOC_AM33XX
1800 default "9" if SA1111
1803 The kernel memory allocator divides physically contiguous memory
1804 blocks into "zones", where each zone is a power of two number of
1805 pages. This option selects the largest power of two that the kernel
1806 keeps in the memory allocator. If you need to allocate very large
1807 blocks of physically contiguous memory, then you may need to
1808 increase this value.
1810 This config option is actually maximum order plus one. For example,
1811 a value of 11 means that the largest free memory block is 2^10 pages.
1813 config ALIGNMENT_TRAP
1815 depends on CPU_CP15_MMU
1816 default y if !ARCH_EBSA110
1817 select HAVE_PROC_CPU if PROC_FS
1819 ARM processors cannot fetch/store information which is not
1820 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1821 address divisible by 4. On 32-bit ARM processors, these non-aligned
1822 fetch/store instructions will be emulated in software if you say
1823 here, which has a severe performance impact. This is necessary for
1824 correct operation of some network protocols. With an IP-only
1825 configuration it is safe to say N, otherwise say Y.
1827 config UACCESS_WITH_MEMCPY
1828 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1830 default y if CPU_FEROCEON
1832 Implement faster copy_to_user and clear_user methods for CPU
1833 cores where a 8-word STM instruction give significantly higher
1834 memory write throughput than a sequence of individual 32bit stores.
1836 A possible side effect is a slight increase in scheduling latency
1837 between threads sharing the same address space if they invoke
1838 such copy operations with large buffers.
1840 However, if the CPU data cache is using a write-allocate mode,
1841 this option is unlikely to provide any performance gain.
1845 prompt "Enable seccomp to safely compute untrusted bytecode"
1847 This kernel feature is useful for number crunching applications
1848 that may need to compute untrusted bytecode during their
1849 execution. By using pipes or other transports made available to
1850 the process as file descriptors supporting the read/write
1851 syscalls, it's possible to isolate those applications in
1852 their own address space using seccomp. Once seccomp is
1853 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1854 and the task is only allowed to execute a few safe syscalls
1855 defined by each seccomp mode.
1857 config CC_STACKPROTECTOR
1858 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1860 This option turns on the -fstack-protector GCC feature. This
1861 feature puts, at the beginning of functions, a canary value on
1862 the stack just before the return address, and validates
1863 the value just before actually returning. Stack based buffer
1864 overflows (that need to overwrite this return address) now also
1865 overwrite the canary, which gets detected and the attack is then
1866 neutralized via a kernel panic.
1867 This feature requires gcc version 4.2 or above.
1880 bool "Xen guest support on ARM (EXPERIMENTAL)"
1881 depends on ARM && AEABI && OF
1882 depends on CPU_V7 && !CPU_V6
1883 depends on !GENERIC_ATOMIC64
1887 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1894 bool "Flattened Device Tree support"
1897 select OF_EARLY_FLATTREE
1899 Include support for flattened device tree machine descriptions.
1902 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1905 This is the traditional way of passing data to the kernel at boot
1906 time. If you are solely relying on the flattened device tree (or
1907 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1908 to remove ATAGS support from your kernel binary. If unsure,
1911 config DEPRECATED_PARAM_STRUCT
1912 bool "Provide old way to pass kernel parameters"
1915 This was deprecated in 2001 and announced to live on for 5 years.
1916 Some old boot loaders still use this way.
1918 # Compressed boot loader in ROM. Yes, we really want to ask about
1919 # TEXT and BSS so we preserve their values in the config files.
1920 config ZBOOT_ROM_TEXT
1921 hex "Compressed ROM boot loader base address"
1924 The physical address at which the ROM-able zImage is to be
1925 placed in the target. Platforms which normally make use of
1926 ROM-able zImage formats normally set this to a suitable
1927 value in their defconfig file.
1929 If ZBOOT_ROM is not enabled, this has no effect.
1931 config ZBOOT_ROM_BSS
1932 hex "Compressed ROM boot loader BSS address"
1935 The base address of an area of read/write memory in the target
1936 for the ROM-able zImage which must be available while the
1937 decompressor is running. It must be large enough to hold the
1938 entire decompressed kernel plus an additional 128 KiB.
1939 Platforms which normally make use of ROM-able zImage formats
1940 normally set this to a suitable value in their defconfig file.
1942 If ZBOOT_ROM is not enabled, this has no effect.
1945 bool "Compressed boot loader in ROM/flash"
1946 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1948 Say Y here if you intend to execute your compressed kernel image
1949 (zImage) directly from ROM or flash. If unsure, say N.
1952 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1953 depends on ZBOOT_ROM && ARCH_SH7372
1954 default ZBOOT_ROM_NONE
1956 Include experimental SD/MMC loading code in the ROM-able zImage.
1957 With this enabled it is possible to write the ROM-able zImage
1958 kernel image to an MMC or SD card and boot the kernel straight
1959 from the reset vector. At reset the processor Mask ROM will load
1960 the first part of the ROM-able zImage which in turn loads the
1961 rest the kernel image to RAM.
1963 config ZBOOT_ROM_NONE
1964 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1966 Do not load image from SD or MMC
1968 config ZBOOT_ROM_MMCIF
1969 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1971 Load image from MMCIF hardware block.
1973 config ZBOOT_ROM_SH_MOBILE_SDHI
1974 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1976 Load image from SDHI hardware block
1980 config ARM_APPENDED_DTB
1981 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1982 depends on OF && !ZBOOT_ROM
1984 With this option, the boot code will look for a device tree binary
1985 (DTB) appended to zImage
1986 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1988 This is meant as a backward compatibility convenience for those
1989 systems with a bootloader that can't be upgraded to accommodate
1990 the documented boot protocol using a device tree.
1992 Beware that there is very little in terms of protection against
1993 this option being confused by leftover garbage in memory that might
1994 look like a DTB header after a reboot if no actual DTB is appended
1995 to zImage. Do not leave this option active in a production kernel
1996 if you don't intend to always append a DTB. Proper passing of the
1997 location into r2 of a bootloader provided DTB is always preferable
2000 config ARM_ATAG_DTB_COMPAT
2001 bool "Supplement the appended DTB with traditional ATAG information"
2002 depends on ARM_APPENDED_DTB
2004 Some old bootloaders can't be updated to a DTB capable one, yet
2005 they provide ATAGs with memory configuration, the ramdisk address,
2006 the kernel cmdline string, etc. Such information is dynamically
2007 provided by the bootloader and can't always be stored in a static
2008 DTB. To allow a device tree enabled kernel to be used with such
2009 bootloaders, this option allows zImage to extract the information
2010 from the ATAG list and store it at run time into the appended DTB.
2013 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2014 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2016 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2017 bool "Use bootloader kernel arguments if available"
2019 Uses the command-line options passed by the boot loader instead of
2020 the device tree bootargs property. If the boot loader doesn't provide
2021 any, the device tree bootargs property will be used.
2023 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2024 bool "Extend with bootloader kernel arguments"
2026 The command-line arguments provided by the boot loader will be
2027 appended to the the device tree bootargs property.
2032 string "Default kernel command string"
2035 On some architectures (EBSA110 and CATS), there is currently no way
2036 for the boot loader to pass arguments to the kernel. For these
2037 architectures, you should supply some command-line options at build
2038 time by entering them here. As a minimum, you should specify the
2039 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2042 prompt "Kernel command line type" if CMDLINE != ""
2043 default CMDLINE_FROM_BOOTLOADER
2046 config CMDLINE_FROM_BOOTLOADER
2047 bool "Use bootloader kernel arguments if available"
2049 Uses the command-line options passed by the boot loader. If
2050 the boot loader doesn't provide any, the default kernel command
2051 string provided in CMDLINE will be used.
2053 config CMDLINE_EXTEND
2054 bool "Extend bootloader kernel arguments"
2056 The command-line arguments provided by the boot loader will be
2057 appended to the default kernel command string.
2059 config CMDLINE_FORCE
2060 bool "Always use the default kernel command string"
2062 Always use the default kernel command string, even if the boot
2063 loader passes other arguments to the kernel.
2064 This is useful if you cannot or don't want to change the
2065 command-line options your boot loader passes to the kernel.
2069 bool "Kernel Execute-In-Place from ROM"
2070 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2072 Execute-In-Place allows the kernel to run from non-volatile storage
2073 directly addressable by the CPU, such as NOR flash. This saves RAM
2074 space since the text section of the kernel is not loaded from flash
2075 to RAM. Read-write sections, such as the data section and stack,
2076 are still copied to RAM. The XIP kernel is not compressed since
2077 it has to run directly from flash, so it will take more space to
2078 store it. The flash address used to link the kernel object files,
2079 and for storing it, is configuration dependent. Therefore, if you
2080 say Y here, you must know the proper physical address where to
2081 store the kernel image depending on your own flash memory usage.
2083 Also note that the make target becomes "make xipImage" rather than
2084 "make zImage" or "make Image". The final kernel binary to put in
2085 ROM memory will be arch/arm/boot/xipImage.
2089 config XIP_PHYS_ADDR
2090 hex "XIP Kernel Physical Location"
2091 depends on XIP_KERNEL
2092 default "0x00080000"
2094 This is the physical address in your flash memory the kernel will
2095 be linked for and stored to. This address is dependent on your
2099 bool "Kexec system call (EXPERIMENTAL)"
2100 depends on (!SMP || PM_SLEEP_SMP)
2102 kexec is a system call that implements the ability to shutdown your
2103 current kernel, and to start another kernel. It is like a reboot
2104 but it is independent of the system firmware. And like a reboot
2105 you can start any kernel with it, not just Linux.
2107 It is an ongoing process to be certain the hardware in a machine
2108 is properly shutdown, so do not be surprised if this code does not
2109 initially work for you.
2112 bool "Export atags in procfs"
2113 depends on ATAGS && KEXEC
2116 Should the atags used to boot the kernel be exported in an "atags"
2117 file in procfs. Useful with kexec.
2120 bool "Build kdump crash kernel (EXPERIMENTAL)"
2122 Generate crash dump after being started by kexec. This should
2123 be normally only set in special crash dump kernels which are
2124 loaded in the main kernel with kexec-tools into a specially
2125 reserved region and then later executed after a crash by
2126 kdump/kexec. The crash dump kernel must be compiled to a
2127 memory address not used by the main kernel
2129 For more details see Documentation/kdump/kdump.txt
2131 config AUTO_ZRELADDR
2132 bool "Auto calculation of the decompressed kernel image address"
2133 depends on !ZBOOT_ROM
2135 ZRELADDR is the physical address where the decompressed kernel
2136 image will be placed. If AUTO_ZRELADDR is selected, the address
2137 will be determined at run-time by masking the current IP with
2138 0xf8000000. This assumes the zImage being placed in the first 128MB
2139 from start of memory.
2143 menu "CPU Power Management"
2146 source "drivers/cpufreq/Kconfig"
2149 source "drivers/cpuidle/Kconfig"
2153 menu "Floating point emulation"
2155 comment "At least one emulation must be selected"
2158 bool "NWFPE math emulation"
2159 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2161 Say Y to include the NWFPE floating point emulator in the kernel.
2162 This is necessary to run most binaries. Linux does not currently
2163 support floating point hardware so you need to say Y here even if
2164 your machine has an FPA or floating point co-processor podule.
2166 You may say N here if you are going to load the Acorn FPEmulator
2167 early in the bootup.
2170 bool "Support extended precision"
2171 depends on FPE_NWFPE
2173 Say Y to include 80-bit support in the kernel floating-point
2174 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2175 Note that gcc does not generate 80-bit operations by default,
2176 so in most cases this option only enlarges the size of the
2177 floating point emulator without any good reason.
2179 You almost surely want to say N here.
2182 bool "FastFPE math emulation (EXPERIMENTAL)"
2183 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2185 Say Y here to include the FAST floating point emulator in the kernel.
2186 This is an experimental much faster emulator which now also has full
2187 precision for the mantissa. It does not support any exceptions.
2188 It is very simple, and approximately 3-6 times faster than NWFPE.
2190 It should be sufficient for most programs. It may be not suitable
2191 for scientific calculations, but you have to check this for yourself.
2192 If you do not feel you need a faster FP emulation you should better
2196 bool "VFP-format floating point maths"
2197 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2199 Say Y to include VFP support code in the kernel. This is needed
2200 if your hardware includes a VFP unit.
2202 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2203 release notes and additional status information.
2205 Say N if your target does not have VFP hardware.
2213 bool "Advanced SIMD (NEON) Extension support"
2214 depends on VFPv3 && CPU_V7
2216 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2219 config KERNEL_MODE_NEON
2220 bool "Support for NEON in kernel mode"
2221 depends on NEON && AEABI
2223 Say Y to include support for NEON in kernel mode.
2227 menu "Userspace binary formats"
2229 source "fs/Kconfig.binfmt"
2232 tristate "RISC OS personality"
2235 Say Y here to include the kernel code necessary if you want to run
2236 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2237 experimental; if this sounds frightening, say N and sleep in peace.
2238 You can also say M here to compile this support as a module (which
2239 will be called arthur).
2243 menu "Power management options"
2245 source "kernel/power/Kconfig"
2247 config ARCH_SUSPEND_POSSIBLE
2248 depends on !ARCH_S5PC100
2249 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2250 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2253 config ARM_CPU_SUSPEND
2258 source "net/Kconfig"
2260 source "drivers/Kconfig"
2264 source "arch/arm/Kconfig.debug"
2266 source "security/Kconfig"
2268 source "crypto/Kconfig"
2270 source "lib/Kconfig"
2272 source "arch/arm/kvm/Kconfig"