4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
10 select SYS_SUPPORTS_APM_EMULATION
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
15 select HAVE_ARCH_TRACEHOOK
16 select HAVE_KPROBES if !XIP_KERNEL
17 select HAVE_KRETPROBES if (HAVE_KPROBES)
18 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
19 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
20 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
21 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
22 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
23 select HAVE_GENERIC_DMA_COHERENT
24 select HAVE_KERNEL_GZIP
25 select HAVE_KERNEL_LZO
26 select HAVE_KERNEL_LZMA
29 select HAVE_PERF_EVENTS
30 select PERF_USE_VMALLOC
31 select HAVE_REGS_AND_STACK_ACCESS_API
32 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
33 select HAVE_C_RECORDMCOUNT
34 select HAVE_GENERIC_HARDIRQS
35 select HARDIRQS_SW_RESEND
36 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
38 select GENERIC_IRQ_PROBE
39 select HARDIRQS_SW_RESEND
40 select CPU_PM if (SUSPEND || CPU_IDLE)
41 select GENERIC_PCI_IOMAP
43 select GENERIC_SMP_IDLE_THREAD
45 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
47 The ARM series is a line of low-power-consumption RISC chip designs
48 licensed by ARM Ltd and targeted at embedded applications and
49 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
50 manufactured, but legacy ARM-based PC hardware remains popular in
51 Europe. There is an ARM Linux project with a web page at
52 <http://www.arm.linux.org.uk/>.
54 config ARM_HAS_SG_CHAIN
63 config SYS_SUPPORTS_APM_EMULATION
71 select GENERIC_ALLOCATOR
82 The Extended Industry Standard Architecture (EISA) bus was
83 developed as an open alternative to the IBM MicroChannel bus.
85 The EISA bus provided some of the features of the IBM MicroChannel
86 bus while maintaining backward compatibility with cards made for
87 the older ISA bus. The EISA bus saw limited use between 1988 and
88 1995 when it was made obsolete by the PCI bus.
90 Say Y here if you are building a kernel for an EISA-based machine.
97 config STACKTRACE_SUPPORT
101 config HAVE_LATENCYTOP_SUPPORT
106 config LOCKDEP_SUPPORT
110 config TRACE_IRQFLAGS_SUPPORT
114 config GENERIC_LOCKBREAK
117 depends on SMP && PREEMPT
119 config RWSEM_GENERIC_SPINLOCK
123 config RWSEM_XCHGADD_ALGORITHM
126 config ARCH_HAS_ILOG2_U32
129 config ARCH_HAS_ILOG2_U64
132 config ARCH_HAS_CPUFREQ
135 Internal node to signify that the ARCH has CPUFREQ support
136 and that the relevant menu configurations are displayed for
139 config GENERIC_HWEIGHT
143 config GENERIC_CALIBRATE_DELAY
147 config ARCH_MAY_HAVE_PC_FDC
153 config NEED_DMA_MAP_STATE
156 config ARCH_HAS_DMA_SET_COHERENT_MASK
159 config GENERIC_ISA_DMA
165 config NEED_RET_TO_USER
173 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
174 default DRAM_BASE if REMAP_VECTORS_TO_RAM
177 The base address of exception vectors.
179 config ARM_PATCH_PHYS_VIRT
180 bool "Patch physical to virtual translations at runtime" if EMBEDDED
182 depends on !XIP_KERNEL && MMU
183 depends on !ARCH_REALVIEW || !SPARSEMEM
185 Patch phys-to-virt and virt-to-phys translation functions at
186 boot and module load time according to the position of the
187 kernel in system memory.
189 This can only be used with non-XIP MMU kernels where the base
190 of physical memory is at a 16MB boundary.
192 Only disable this option if you know that you do not require
193 this feature (eg, building a kernel for a single machine) and
194 you need to shrink the kernel to the minimal size.
196 config NEED_MACH_IO_H
199 Select this when mach/io.h is required to provide special
200 definitions for this platform. The need for mach/io.h should
201 be avoided when possible.
203 config NEED_MACH_MEMORY_H
206 Select this when mach/memory.h is required to provide special
207 definitions for this platform. The need for mach/memory.h should
208 be avoided when possible.
211 hex "Physical address of main memory" if MMU
212 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
213 default DRAM_BASE if !MMU
215 Please provide the physical address corresponding to the
216 location of main memory in your system.
222 source "init/Kconfig"
224 source "kernel/Kconfig.freezer"
229 bool "MMU-based Paged Memory Management Support"
232 Select if you want MMU-based virtualised addressing space
233 support by paged memory management. If unsure, say 'Y'.
236 # The "ARM system type" choice list is ordered alphabetically by option
237 # text. Please add new entries in the option alphabetic order.
240 prompt "ARM system type"
241 default ARCH_VERSATILE
243 config ARCH_INTEGRATOR
244 bool "ARM Ltd. Integrator family"
246 select ARCH_HAS_CPUFREQ
248 select HAVE_MACH_CLKDEV
251 select GENERIC_CLOCKEVENTS
252 select PLAT_VERSATILE
253 select PLAT_VERSATILE_FPGA_IRQ
254 select NEED_MACH_IO_H
255 select NEED_MACH_MEMORY_H
257 select MULTI_IRQ_HANDLER
259 Support for ARM's Integrator platform.
262 bool "ARM Ltd. RealView family"
265 select HAVE_MACH_CLKDEV
267 select GENERIC_CLOCKEVENTS
268 select ARCH_WANT_OPTIONAL_GPIOLIB
269 select PLAT_VERSATILE
270 select PLAT_VERSATILE_CLCD
271 select ARM_TIMER_SP804
272 select GPIO_PL061 if GPIOLIB
273 select NEED_MACH_MEMORY_H
275 This enables support for ARM Ltd RealView boards.
277 config ARCH_VERSATILE
278 bool "ARM Ltd. Versatile family"
282 select HAVE_MACH_CLKDEV
284 select GENERIC_CLOCKEVENTS
285 select ARCH_WANT_OPTIONAL_GPIOLIB
286 select PLAT_VERSATILE
287 select PLAT_VERSATILE_CLCD
288 select PLAT_VERSATILE_FPGA_IRQ
289 select ARM_TIMER_SP804
291 This enables support for ARM Ltd Versatile board.
294 bool "ARM Ltd. Versatile Express family"
295 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select ARM_TIMER_SP804
299 select HAVE_MACH_CLKDEV
300 select GENERIC_CLOCKEVENTS
302 select HAVE_PATA_PLATFORM
305 select PLAT_VERSATILE
306 select PLAT_VERSATILE_CLCD
308 This enables support for the ARM Ltd Versatile Express boards.
312 select ARCH_REQUIRE_GPIOLIB
316 select NEED_MACH_IO_H if PCCARD
318 This enables support for systems based on Atmel
319 AT91RM9200 and AT91SAM9* processors.
322 bool "Broadcom BCMRING"
326 select ARM_TIMER_SP804
328 select GENERIC_CLOCKEVENTS
329 select ARCH_WANT_OPTIONAL_GPIOLIB
331 Support for Broadcom's BCMRing platform.
334 bool "Calxeda Highbank-based"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
342 select GENERIC_CLOCKEVENTS
348 Support for the Calxeda Highbank SoC based boards.
351 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
353 select ARCH_USES_GETTIMEOFFSET
354 select NEED_MACH_MEMORY_H
356 Support for Cirrus Logic 711x/721x/731x based boards.
359 bool "Cavium Networks CNS3XXX family"
361 select GENERIC_CLOCKEVENTS
363 select MIGHT_HAVE_CACHE_L2X0
364 select MIGHT_HAVE_PCI
365 select PCI_DOMAINS if PCI
367 Support for Cavium Networks CNS3XXX platform.
370 bool "Cortina Systems Gemini"
372 select ARCH_REQUIRE_GPIOLIB
373 select ARCH_USES_GETTIMEOFFSET
375 Support for the Cortina Systems Gemini family SoCs
378 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
381 select GENERIC_CLOCKEVENTS
383 select GENERIC_IRQ_CHIP
384 select MIGHT_HAVE_CACHE_L2X0
390 Support for CSR SiRFSoC ARM Cortex A9 Platform
397 select ARCH_USES_GETTIMEOFFSET
398 select NEED_MACH_IO_H
399 select NEED_MACH_MEMORY_H
401 This is an evaluation board for the StrongARM processor available
402 from Digital. It has limited hardware on-board, including an
403 Ethernet interface, two PCMCIA sockets, two serial ports and a
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_HAS_HOLES_MEMORYMODEL
414 select ARCH_USES_GETTIMEOFFSET
415 select NEED_MACH_MEMORY_H
417 This enables support for the Cirrus EP93xx series of CPUs.
419 config ARCH_FOOTBRIDGE
423 select GENERIC_CLOCKEVENTS
425 select NEED_MACH_IO_H
426 select NEED_MACH_MEMORY_H
428 Support for systems based on the DC21285 companion chip
429 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
432 bool "Freescale MXC/iMX-based"
433 select GENERIC_CLOCKEVENTS
434 select ARCH_REQUIRE_GPIOLIB
437 select GENERIC_IRQ_CHIP
438 select MULTI_IRQ_HANDLER
440 Support for Freescale MXC/iMX-based family of processors
443 bool "Freescale MXS-based"
444 select GENERIC_CLOCKEVENTS
445 select ARCH_REQUIRE_GPIOLIB
448 select HAVE_CLK_PREPARE
451 Support for Freescale MXS-based family of processors
454 bool "Hilscher NetX based"
458 select GENERIC_CLOCKEVENTS
460 This enables support for systems based on the Hilscher NetX Soc
463 bool "Hynix HMS720x-based"
466 select ARCH_USES_GETTIMEOFFSET
468 This enables support for systems based on the Hynix HMS720x
476 select ARCH_SUPPORTS_MSI
478 select NEED_MACH_IO_H
479 select NEED_MACH_MEMORY_H
480 select NEED_RET_TO_USER
482 Support for Intel's IOP13XX (XScale) family of processors.
488 select NEED_MACH_IO_H
489 select NEED_RET_TO_USER
492 select ARCH_REQUIRE_GPIOLIB
494 Support for Intel's 80219 and IOP32X (XScale) family of
501 select NEED_MACH_IO_H
502 select NEED_RET_TO_USER
505 select ARCH_REQUIRE_GPIOLIB
507 Support for Intel's IOP33X (XScale) family of processors.
512 select ARCH_HAS_DMA_SET_COHERENT_MASK
516 select GENERIC_CLOCKEVENTS
517 select MIGHT_HAVE_PCI
518 select NEED_MACH_IO_H
519 select DMABOUNCE if PCI
521 Support for Intel's IXP4XX (XScale) family of processors.
527 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
529 select NEED_MACH_IO_H
532 Support for the Marvell Dove SoC 88AP510
535 bool "Marvell Kirkwood"
538 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
540 select NEED_MACH_IO_H
543 Support for the following Marvell Kirkwood series SoCs:
544 88F6180, 88F6192 and 88F6281.
550 select ARCH_REQUIRE_GPIOLIB
553 select USB_ARCH_HAS_OHCI
555 select GENERIC_CLOCKEVENTS
558 Support for the NXP LPC32XX family of processors
561 bool "Marvell MV78xx0"
564 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_CLOCKEVENTS
566 select NEED_MACH_IO_H
569 Support for the following Marvell MV78xx0 series SoCs:
577 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
581 Support for the following Marvell Orion 5x series SoCs:
582 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
583 Orion-2 (5281), Orion-1-90 (6183).
586 bool "Marvell PXA168/910/MMP2"
588 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
595 select GENERIC_ALLOCATOR
597 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
600 bool "Micrel/Kendin KS8695"
602 select ARCH_REQUIRE_GPIOLIB
603 select ARCH_USES_GETTIMEOFFSET
604 select NEED_MACH_MEMORY_H
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
610 bool "Nuvoton W90X900 CPU"
612 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
629 select GENERIC_CLOCKEVENTS
633 select MIGHT_HAVE_CACHE_L2X0
634 select NEED_MACH_IO_H if PCI
635 select ARCH_HAS_CPUFREQ
637 This enables support for NVIDIA Tegra based systems (Tegra APX,
638 Tegra 6xx and Tegra 2 series).
640 config ARCH_PICOXCELL
641 bool "Picochip picoXcell"
642 select ARCH_REQUIRE_GPIOLIB
643 select ARM_PATCH_PHYS_VIRT
647 select GENERIC_CLOCKEVENTS
654 This enables support for systems based on the Picochip picoXcell
655 family of Femtocell devices. The picoxcell support requires device tree
659 bool "Philips Nexperia PNX4008 Mobile"
662 select ARCH_USES_GETTIMEOFFSET
664 This enables support for Philips PNX4008 mobile platform.
667 bool "PXA2xx/PXA3xx-based"
670 select ARCH_HAS_CPUFREQ
673 select ARCH_REQUIRE_GPIOLIB
674 select GENERIC_CLOCKEVENTS
679 select MULTI_IRQ_HANDLER
680 select ARM_CPU_SUSPEND if PM
683 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
688 select GENERIC_CLOCKEVENTS
689 select ARCH_REQUIRE_GPIOLIB
692 Support for Qualcomm MSM/QSD based systems. This runs on the
693 apps processor of the MSM/QSD and depends on a shared memory
694 interface to the modem processor which runs the baseband
695 stack and controls some vital subsystems
696 (clock and power control, etc).
699 bool "Renesas SH-Mobile / R-Mobile"
702 select HAVE_MACH_CLKDEV
704 select GENERIC_CLOCKEVENTS
705 select MIGHT_HAVE_CACHE_L2X0
708 select MULTI_IRQ_HANDLER
709 select PM_GENERIC_DOMAINS if PM
710 select NEED_MACH_MEMORY_H
712 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
718 select ARCH_MAY_HAVE_PC_FDC
719 select HAVE_PATA_PLATFORM
722 select ARCH_SPARSEMEM_ENABLE
723 select ARCH_USES_GETTIMEOFFSET
725 select NEED_MACH_IO_H
726 select NEED_MACH_MEMORY_H
728 On the Acorn Risc-PC, Linux can support the internal IDE disk and
729 CD-ROM interface, serial and parallel port, and the floppy drive.
736 select ARCH_SPARSEMEM_ENABLE
738 select ARCH_HAS_CPUFREQ
740 select GENERIC_CLOCKEVENTS
742 select ARCH_REQUIRE_GPIOLIB
744 select NEED_MACH_MEMORY_H
747 Support for StrongARM 11x0 based boards.
750 bool "Samsung S3C24XX SoCs"
752 select ARCH_HAS_CPUFREQ
755 select ARCH_USES_GETTIMEOFFSET
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C_RTC if RTC_CLASS
758 select HAVE_S3C2410_WATCHDOG if WATCHDOG
759 select NEED_MACH_IO_H
761 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
762 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
763 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
764 Samsung SMDK2410 development board (and derivatives).
767 bool "Samsung S3C64XX"
775 select ARCH_USES_GETTIMEOFFSET
776 select ARCH_HAS_CPUFREQ
777 select ARCH_REQUIRE_GPIOLIB
778 select SAMSUNG_CLKSRC
779 select SAMSUNG_IRQ_VIC_TIMER
780 select S3C_GPIO_TRACK
782 select USB_ARCH_HAS_OHCI
783 select SAMSUNG_GPIOLIB_4BIT
784 select HAVE_S3C2410_I2C if I2C
785 select HAVE_S3C2410_WATCHDOG if WATCHDOG
787 Samsung S3C64XX series based systems
790 bool "Samsung S5P6440 S5P6450"
796 select HAVE_S3C2410_WATCHDOG if WATCHDOG
797 select GENERIC_CLOCKEVENTS
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C_RTC if RTC_CLASS
801 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
805 bool "Samsung S5PC100"
810 select ARCH_USES_GETTIMEOFFSET
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C_RTC if RTC_CLASS
813 select HAVE_S3C2410_WATCHDOG if WATCHDOG
815 Samsung S5PC100 series based systems
818 bool "Samsung S5PV210/S5PC110"
820 select ARCH_SPARSEMEM_ENABLE
821 select ARCH_HAS_HOLES_MEMORYMODEL
826 select ARCH_HAS_CPUFREQ
827 select GENERIC_CLOCKEVENTS
828 select HAVE_S3C2410_I2C if I2C
829 select HAVE_S3C_RTC if RTC_CLASS
830 select HAVE_S3C2410_WATCHDOG if WATCHDOG
831 select NEED_MACH_MEMORY_H
833 Samsung S5PV210/S5PC110 series based systems
836 bool "SAMSUNG EXYNOS"
838 select ARCH_SPARSEMEM_ENABLE
839 select ARCH_HAS_HOLES_MEMORYMODEL
843 select ARCH_HAS_CPUFREQ
844 select GENERIC_CLOCKEVENTS
845 select HAVE_S3C_RTC if RTC_CLASS
846 select HAVE_S3C2410_I2C if I2C
847 select HAVE_S3C2410_WATCHDOG if WATCHDOG
848 select NEED_MACH_MEMORY_H
850 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
859 select ARCH_USES_GETTIMEOFFSET
860 select NEED_MACH_MEMORY_H
861 select NEED_MACH_IO_H
863 Support for the StrongARM based Digital DNARD machine, also known
864 as "Shark" (<http://www.shark-linux.de/shark.html>).
867 bool "ST-Ericsson U300 Series"
873 select ARM_PATCH_PHYS_VIRT
875 select GENERIC_CLOCKEVENTS
877 select HAVE_MACH_CLKDEV
879 select ARCH_REQUIRE_GPIOLIB
881 Support for ST-Ericsson U300 series mobile platforms.
884 bool "ST-Ericsson U8500 Series"
888 select GENERIC_CLOCKEVENTS
890 select ARCH_REQUIRE_GPIOLIB
891 select ARCH_HAS_CPUFREQ
893 select MIGHT_HAVE_CACHE_L2X0
895 Support for ST-Ericsson's Ux500 architecture
898 bool "STMicroelectronics Nomadik"
903 select GENERIC_CLOCKEVENTS
905 select MIGHT_HAVE_CACHE_L2X0
906 select ARCH_REQUIRE_GPIOLIB
908 Support for the Nomadik platform by ST-Ericsson
912 select GENERIC_CLOCKEVENTS
913 select ARCH_REQUIRE_GPIOLIB
917 select GENERIC_ALLOCATOR
918 select GENERIC_IRQ_CHIP
919 select ARCH_HAS_HOLES_MEMORYMODEL
921 Support for TI's DaVinci platform.
926 select ARCH_REQUIRE_GPIOLIB
927 select ARCH_HAS_CPUFREQ
929 select GENERIC_CLOCKEVENTS
930 select ARCH_HAS_HOLES_MEMORYMODEL
932 Support for TI's OMAP platform (OMAP1/2/3/4).
937 select ARCH_REQUIRE_GPIOLIB
940 select GENERIC_CLOCKEVENTS
943 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
946 bool "VIA/WonderMedia 85xx"
949 select ARCH_HAS_CPUFREQ
950 select GENERIC_CLOCKEVENTS
951 select ARCH_REQUIRE_GPIOLIB
954 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
957 bool "Xilinx Zynq ARM Cortex A9 Platform"
959 select GENERIC_CLOCKEVENTS
964 select MIGHT_HAVE_CACHE_L2X0
967 Support for Xilinx Zynq ARM Cortex A9 Platform
971 # This is sorted alphabetically by mach-* pathname. However, plat-*
972 # Kconfigs may be included either alphabetically (according to the
973 # plat- suffix) or along side the corresponding mach-* source.
975 source "arch/arm/mach-at91/Kconfig"
977 source "arch/arm/mach-bcmring/Kconfig"
979 source "arch/arm/mach-clps711x/Kconfig"
981 source "arch/arm/mach-cns3xxx/Kconfig"
983 source "arch/arm/mach-davinci/Kconfig"
985 source "arch/arm/mach-dove/Kconfig"
987 source "arch/arm/mach-ep93xx/Kconfig"
989 source "arch/arm/mach-footbridge/Kconfig"
991 source "arch/arm/mach-gemini/Kconfig"
993 source "arch/arm/mach-h720x/Kconfig"
995 source "arch/arm/mach-integrator/Kconfig"
997 source "arch/arm/mach-iop32x/Kconfig"
999 source "arch/arm/mach-iop33x/Kconfig"
1001 source "arch/arm/mach-iop13xx/Kconfig"
1003 source "arch/arm/mach-ixp4xx/Kconfig"
1005 source "arch/arm/mach-kirkwood/Kconfig"
1007 source "arch/arm/mach-ks8695/Kconfig"
1009 source "arch/arm/mach-lpc32xx/Kconfig"
1011 source "arch/arm/mach-msm/Kconfig"
1013 source "arch/arm/mach-mv78xx0/Kconfig"
1015 source "arch/arm/plat-mxc/Kconfig"
1017 source "arch/arm/mach-mxs/Kconfig"
1019 source "arch/arm/mach-netx/Kconfig"
1021 source "arch/arm/mach-nomadik/Kconfig"
1022 source "arch/arm/plat-nomadik/Kconfig"
1024 source "arch/arm/plat-omap/Kconfig"
1026 source "arch/arm/mach-omap1/Kconfig"
1028 source "arch/arm/mach-omap2/Kconfig"
1030 source "arch/arm/mach-orion5x/Kconfig"
1032 source "arch/arm/mach-pxa/Kconfig"
1033 source "arch/arm/plat-pxa/Kconfig"
1035 source "arch/arm/mach-mmp/Kconfig"
1037 source "arch/arm/mach-realview/Kconfig"
1039 source "arch/arm/mach-sa1100/Kconfig"
1041 source "arch/arm/plat-samsung/Kconfig"
1042 source "arch/arm/plat-s3c24xx/Kconfig"
1043 source "arch/arm/plat-s5p/Kconfig"
1045 source "arch/arm/plat-spear/Kconfig"
1047 source "arch/arm/mach-s3c24xx/Kconfig"
1049 source "arch/arm/mach-s3c2412/Kconfig"
1050 source "arch/arm/mach-s3c2440/Kconfig"
1054 source "arch/arm/mach-s3c64xx/Kconfig"
1057 source "arch/arm/mach-s5p64x0/Kconfig"
1059 source "arch/arm/mach-s5pc100/Kconfig"
1061 source "arch/arm/mach-s5pv210/Kconfig"
1063 source "arch/arm/mach-exynos/Kconfig"
1065 source "arch/arm/mach-shmobile/Kconfig"
1067 source "arch/arm/mach-tegra/Kconfig"
1069 source "arch/arm/mach-u300/Kconfig"
1071 source "arch/arm/mach-ux500/Kconfig"
1073 source "arch/arm/mach-versatile/Kconfig"
1075 source "arch/arm/mach-vexpress/Kconfig"
1076 source "arch/arm/plat-versatile/Kconfig"
1078 source "arch/arm/mach-vt8500/Kconfig"
1080 source "arch/arm/mach-w90x900/Kconfig"
1082 # Definitions to make life easier
1088 select GENERIC_CLOCKEVENTS
1093 select GENERIC_IRQ_CHIP
1098 config PLAT_VERSATILE
1101 config ARM_TIMER_SP804
1104 select HAVE_SCHED_CLOCK
1106 source arch/arm/mm/Kconfig
1110 default 16 if ARCH_EP93XX
1114 bool "Enable iWMMXt support"
1115 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1116 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1118 Enable support for iWMMXt context switching at run time if
1119 running on a CPU that supports it.
1123 depends on CPU_XSCALE
1127 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1128 (!ARCH_OMAP3 || OMAP3_EMU)
1132 config MULTI_IRQ_HANDLER
1135 Allow each machine to specify it's own IRQ handler at run time.
1138 source "arch/arm/Kconfig-nommu"
1141 config ARM_ERRATA_326103
1142 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1145 Executing a SWP instruction to read-only memory does not set bit 11
1146 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1147 treat the access as a read, preventing a COW from occurring and
1148 causing the faulting task to livelock.
1150 config ARM_ERRATA_411920
1151 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1152 depends on CPU_V6 || CPU_V6K
1154 Invalidation of the Instruction Cache operation can
1155 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1156 It does not affect the MPCore. This option enables the ARM Ltd.
1157 recommended workaround.
1159 config ARM_ERRATA_430973
1160 bool "ARM errata: Stale prediction on replaced interworking branch"
1163 This option enables the workaround for the 430973 Cortex-A8
1164 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1165 interworking branch is replaced with another code sequence at the
1166 same virtual address, whether due to self-modifying code or virtual
1167 to physical address re-mapping, Cortex-A8 does not recover from the
1168 stale interworking branch prediction. This results in Cortex-A8
1169 executing the new code sequence in the incorrect ARM or Thumb state.
1170 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1171 and also flushes the branch target cache at every context switch.
1172 Note that setting specific bits in the ACTLR register may not be
1173 available in non-secure mode.
1175 config ARM_ERRATA_458693
1176 bool "ARM errata: Processor deadlock when a false hazard is created"
1179 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1180 erratum. For very specific sequences of memory operations, it is
1181 possible for a hazard condition intended for a cache line to instead
1182 be incorrectly associated with a different cache line. This false
1183 hazard might then cause a processor deadlock. The workaround enables
1184 the L1 caching of the NEON accesses and disables the PLD instruction
1185 in the ACTLR register. Note that setting specific bits in the ACTLR
1186 register may not be available in non-secure mode.
1188 config ARM_ERRATA_460075
1189 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1192 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1193 erratum. Any asynchronous access to the L2 cache may encounter a
1194 situation in which recent store transactions to the L2 cache are lost
1195 and overwritten with stale memory contents from external memory. The
1196 workaround disables the write-allocate mode for the L2 cache via the
1197 ACTLR register. Note that setting specific bits in the ACTLR register
1198 may not be available in non-secure mode.
1200 config ARM_ERRATA_742230
1201 bool "ARM errata: DMB operation may be faulty"
1202 depends on CPU_V7 && SMP
1204 This option enables the workaround for the 742230 Cortex-A9
1205 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1206 between two write operations may not ensure the correct visibility
1207 ordering of the two writes. This workaround sets a specific bit in
1208 the diagnostic register of the Cortex-A9 which causes the DMB
1209 instruction to behave as a DSB, ensuring the correct behaviour of
1212 config ARM_ERRATA_742231
1213 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1214 depends on CPU_V7 && SMP
1216 This option enables the workaround for the 742231 Cortex-A9
1217 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1218 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1219 accessing some data located in the same cache line, may get corrupted
1220 data due to bad handling of the address hazard when the line gets
1221 replaced from one of the CPUs at the same time as another CPU is
1222 accessing it. This workaround sets specific bits in the diagnostic
1223 register of the Cortex-A9 which reduces the linefill issuing
1224 capabilities of the processor.
1226 config PL310_ERRATA_588369
1227 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1228 depends on CACHE_L2X0
1230 The PL310 L2 cache controller implements three types of Clean &
1231 Invalidate maintenance operations: by Physical Address
1232 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1233 They are architecturally defined to behave as the execution of a
1234 clean operation followed immediately by an invalidate operation,
1235 both performing to the same memory location. This functionality
1236 is not correctly implemented in PL310 as clean lines are not
1237 invalidated as a result of these operations.
1239 config ARM_ERRATA_720789
1240 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1243 This option enables the workaround for the 720789 Cortex-A9 (prior to
1244 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1245 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1246 As a consequence of this erratum, some TLB entries which should be
1247 invalidated are not, resulting in an incoherency in the system page
1248 tables. The workaround changes the TLB flushing routines to invalidate
1249 entries regardless of the ASID.
1251 config PL310_ERRATA_727915
1252 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1253 depends on CACHE_L2X0
1255 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1256 operation (offset 0x7FC). This operation runs in background so that
1257 PL310 can handle normal accesses while it is in progress. Under very
1258 rare circumstances, due to this erratum, write data can be lost when
1259 PL310 treats a cacheable write transaction during a Clean &
1260 Invalidate by Way operation.
1262 config ARM_ERRATA_743622
1263 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1266 This option enables the workaround for the 743622 Cortex-A9
1267 (r2p*) erratum. Under very rare conditions, a faulty
1268 optimisation in the Cortex-A9 Store Buffer may lead to data
1269 corruption. This workaround sets a specific bit in the diagnostic
1270 register of the Cortex-A9 which disables the Store Buffer
1271 optimisation, preventing the defect from occurring. This has no
1272 visible impact on the overall performance or power consumption of the
1275 config ARM_ERRATA_751472
1276 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1279 This option enables the workaround for the 751472 Cortex-A9 (prior
1280 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1281 completion of a following broadcasted operation if the second
1282 operation is received by a CPU before the ICIALLUIS has completed,
1283 potentially leading to corrupted entries in the cache or TLB.
1285 config PL310_ERRATA_753970
1286 bool "PL310 errata: cache sync operation may be faulty"
1287 depends on CACHE_PL310
1289 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1291 Under some condition the effect of cache sync operation on
1292 the store buffer still remains when the operation completes.
1293 This means that the store buffer is always asked to drain and
1294 this prevents it from merging any further writes. The workaround
1295 is to replace the normal offset of cache sync operation (0x730)
1296 by another offset targeting an unmapped PL310 register 0x740.
1297 This has the same effect as the cache sync operation: store buffer
1298 drain and waiting for all buffers empty.
1300 config ARM_ERRATA_754322
1301 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1304 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1305 r3p*) erratum. A speculative memory access may cause a page table walk
1306 which starts prior to an ASID switch but completes afterwards. This
1307 can populate the micro-TLB with a stale entry which may be hit with
1308 the new ASID. This workaround places two dsb instructions in the mm
1309 switching code so that no page table walks can cross the ASID switch.
1311 config ARM_ERRATA_754327
1312 bool "ARM errata: no automatic Store Buffer drain"
1313 depends on CPU_V7 && SMP
1315 This option enables the workaround for the 754327 Cortex-A9 (prior to
1316 r2p0) erratum. The Store Buffer does not have any automatic draining
1317 mechanism and therefore a livelock may occur if an external agent
1318 continuously polls a memory location waiting to observe an update.
1319 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1320 written polling loops from denying visibility of updates to memory.
1322 config ARM_ERRATA_364296
1323 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1324 depends on CPU_V6 && !SMP
1326 This options enables the workaround for the 364296 ARM1136
1327 r0p2 erratum (possible cache data corruption with
1328 hit-under-miss enabled). It sets the undocumented bit 31 in
1329 the auxiliary control register and the FI bit in the control
1330 register, thus disabling hit-under-miss without putting the
1331 processor into full low interrupt latency mode. ARM11MPCore
1334 config ARM_ERRATA_764369
1335 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1336 depends on CPU_V7 && SMP
1338 This option enables the workaround for erratum 764369
1339 affecting Cortex-A9 MPCore with two or more processors (all
1340 current revisions). Under certain timing circumstances, a data
1341 cache line maintenance operation by MVA targeting an Inner
1342 Shareable memory region may fail to proceed up to either the
1343 Point of Coherency or to the Point of Unification of the
1344 system. This workaround adds a DSB instruction before the
1345 relevant cache maintenance functions and sets a specific bit
1346 in the diagnostic control register of the SCU.
1348 config PL310_ERRATA_769419
1349 bool "PL310 errata: no automatic Store Buffer drain"
1350 depends on CACHE_L2X0
1352 On revisions of the PL310 prior to r3p2, the Store Buffer does
1353 not automatically drain. This can cause normal, non-cacheable
1354 writes to be retained when the memory system is idle, leading
1355 to suboptimal I/O performance for drivers using coherent DMA.
1356 This option adds a write barrier to the cpu_idle loop so that,
1357 on systems with an outer cache, the store buffer is drained
1362 source "arch/arm/common/Kconfig"
1372 Find out whether you have ISA slots on your motherboard. ISA is the
1373 name of a bus system, i.e. the way the CPU talks to the other stuff
1374 inside your box. Other bus systems are PCI, EISA, MicroChannel
1375 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1376 newer boards don't support it. If you have ISA, say Y, otherwise N.
1378 # Select ISA DMA controller support
1383 # Select ISA DMA interface
1388 bool "PCI support" if MIGHT_HAVE_PCI
1390 Find out whether you have a PCI motherboard. PCI is the name of a
1391 bus system, i.e. the way the CPU talks to the other stuff inside
1392 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1393 VESA. If you have PCI, say Y, otherwise N.
1399 config PCI_NANOENGINE
1400 bool "BSE nanoEngine PCI support"
1401 depends on SA1100_NANOENGINE
1403 Enable PCI on the BSE nanoEngine board.
1408 # Select the host bridge type
1409 config PCI_HOST_VIA82C505
1411 depends on PCI && ARCH_SHARK
1414 config PCI_HOST_ITE8152
1416 depends on PCI && MACH_ARMCORE
1420 source "drivers/pci/Kconfig"
1422 source "drivers/pcmcia/Kconfig"
1426 menu "Kernel Features"
1431 This option should be selected by machines which have an SMP-
1434 The only effect of this option is to make the SMP-related
1435 options available to the user for configuration.
1438 bool "Symmetric Multi-Processing"
1439 depends on CPU_V6K || CPU_V7
1440 depends on GENERIC_CLOCKEVENTS
1443 select USE_GENERIC_SMP_HELPERS
1444 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1446 This enables support for systems with more than one CPU. If you have
1447 a system with only one CPU, like most personal computers, say N. If
1448 you have a system with more than one CPU, say Y.
1450 If you say N here, the kernel will run on single and multiprocessor
1451 machines, but will use only one CPU of a multiprocessor machine. If
1452 you say Y here, the kernel will run on many, but not all, single
1453 processor machines. On a single processor machine, the kernel will
1454 run faster if you say N here.
1456 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1457 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1458 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1460 If you don't know what to do here, say N.
1463 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1464 depends on EXPERIMENTAL
1465 depends on SMP && !XIP_KERNEL
1468 SMP kernels contain instructions which fail on non-SMP processors.
1469 Enabling this option allows the kernel to modify itself to make
1470 these instructions safe. Disabling it allows about 1K of space
1473 If you don't know what to do here, say Y.
1475 config ARM_CPU_TOPOLOGY
1476 bool "Support cpu topology definition"
1477 depends on SMP && CPU_V7
1480 Support ARM cpu topology definition. The MPIDR register defines
1481 affinity between processors which is then used to describe the cpu
1482 topology of an ARM System.
1485 bool "Multi-core scheduler support"
1486 depends on ARM_CPU_TOPOLOGY
1488 Multi-core scheduler support improves the CPU scheduler's decision
1489 making when dealing with multi-core CPU chips at a cost of slightly
1490 increased overhead in some places. If unsure say N here.
1493 bool "SMT scheduler support"
1494 depends on ARM_CPU_TOPOLOGY
1496 Improves the CPU scheduler's decision making when dealing with
1497 MultiThreading at a cost of slightly increased overhead in some
1498 places. If unsure say N here.
1503 This option enables support for the ARM system coherency unit
1505 config ARM_ARCH_TIMER
1506 bool "Architected timer support"
1509 This option enables support for the ARM architected timer
1515 This options enables support for the ARM timer and watchdog unit
1518 prompt "Memory split"
1521 Select the desired split between kernel and user memory.
1523 If you are not absolutely sure what you are doing, leave this
1527 bool "3G/1G user/kernel split"
1529 bool "2G/2G user/kernel split"
1531 bool "1G/3G user/kernel split"
1536 default 0x40000000 if VMSPLIT_1G
1537 default 0x80000000 if VMSPLIT_2G
1541 int "Maximum number of CPUs (2-32)"
1547 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1548 depends on SMP && HOTPLUG && EXPERIMENTAL
1550 Say Y here to experiment with turning CPUs off and on. CPUs
1551 can be controlled through /sys/devices/system/cpu.
1554 bool "Use local timer interrupts"
1557 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1559 Enable support for local timers on SMP platforms, rather then the
1560 legacy IPI broadcast method. Local timers allows the system
1561 accounting to be spread across the timer interval, preventing a
1562 "thundering herd" at every timer tick.
1566 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1567 default 355 if ARCH_U8500
1568 default 264 if MACH_H4700
1571 Maximum number of GPIOs in the system.
1573 If unsure, leave the default value.
1575 source kernel/Kconfig.preempt
1579 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1580 ARCH_S5PV210 || ARCH_EXYNOS4
1581 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1582 default AT91_TIMER_HZ if ARCH_AT91
1583 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1586 config THUMB2_KERNEL
1587 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1588 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1590 select ARM_ASM_UNIFIED
1593 By enabling this option, the kernel will be compiled in
1594 Thumb-2 mode. A compiler/assembler that understand the unified
1595 ARM-Thumb syntax is needed.
1599 config THUMB2_AVOID_R_ARM_THM_JUMP11
1600 bool "Work around buggy Thumb-2 short branch relocations in gas"
1601 depends on THUMB2_KERNEL && MODULES
1604 Various binutils versions can resolve Thumb-2 branches to
1605 locally-defined, preemptible global symbols as short-range "b.n"
1606 branch instructions.
1608 This is a problem, because there's no guarantee the final
1609 destination of the symbol, or any candidate locations for a
1610 trampoline, are within range of the branch. For this reason, the
1611 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1612 relocation in modules at all, and it makes little sense to add
1615 The symptom is that the kernel fails with an "unsupported
1616 relocation" error when loading some modules.
1618 Until fixed tools are available, passing
1619 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1620 code which hits this problem, at the cost of a bit of extra runtime
1621 stack usage in some cases.
1623 The problem is described in more detail at:
1624 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1626 Only Thumb-2 kernels are affected.
1628 Unless you are sure your tools don't have this problem, say Y.
1630 config ARM_ASM_UNIFIED
1634 bool "Use the ARM EABI to compile the kernel"
1636 This option allows for the kernel to be compiled using the latest
1637 ARM ABI (aka EABI). This is only useful if you are using a user
1638 space environment that is also compiled with EABI.
1640 Since there are major incompatibilities between the legacy ABI and
1641 EABI, especially with regard to structure member alignment, this
1642 option also changes the kernel syscall calling convention to
1643 disambiguate both ABIs and allow for backward compatibility support
1644 (selected with CONFIG_OABI_COMPAT).
1646 To use this you need GCC version 4.0.0 or later.
1649 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1650 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1653 This option preserves the old syscall interface along with the
1654 new (ARM EABI) one. It also provides a compatibility layer to
1655 intercept syscalls that have structure arguments which layout
1656 in memory differs between the legacy ABI and the new ARM EABI
1657 (only for non "thumb" binaries). This option adds a tiny
1658 overhead to all syscalls and produces a slightly larger kernel.
1659 If you know you'll be using only pure EABI user space then you
1660 can say N here. If this option is not selected and you attempt
1661 to execute a legacy ABI binary then the result will be
1662 UNPREDICTABLE (in fact it can be predicted that it won't work
1663 at all). If in doubt say Y.
1665 config ARCH_HAS_HOLES_MEMORYMODEL
1668 config ARCH_SPARSEMEM_ENABLE
1671 config ARCH_SPARSEMEM_DEFAULT
1672 def_bool ARCH_SPARSEMEM_ENABLE
1674 config ARCH_SELECT_MEMORY_MODEL
1675 def_bool ARCH_SPARSEMEM_ENABLE
1677 config HAVE_ARCH_PFN_VALID
1678 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1681 bool "High Memory Support"
1684 The address space of ARM processors is only 4 Gigabytes large
1685 and it has to accommodate user address space, kernel address
1686 space as well as some memory mapped IO. That means that, if you
1687 have a large amount of physical memory and/or IO, not all of the
1688 memory can be "permanently mapped" by the kernel. The physical
1689 memory that is not permanently mapped is called "high memory".
1691 Depending on the selected kernel/user memory split, minimum
1692 vmalloc space and actual amount of RAM, you may not need this
1693 option which should result in a slightly faster kernel.
1698 bool "Allocate 2nd-level pagetables from highmem"
1701 config HW_PERF_EVENTS
1702 bool "Enable hardware performance counter support for perf events"
1703 depends on PERF_EVENTS && CPU_HAS_PMU
1706 Enable hardware performance counter support for perf events. If
1707 disabled, perf events will use software events only.
1711 config FORCE_MAX_ZONEORDER
1712 int "Maximum zone order" if ARCH_SHMOBILE
1713 range 11 64 if ARCH_SHMOBILE
1714 default "9" if SA1111
1717 The kernel memory allocator divides physically contiguous memory
1718 blocks into "zones", where each zone is a power of two number of
1719 pages. This option selects the largest power of two that the kernel
1720 keeps in the memory allocator. If you need to allocate very large
1721 blocks of physically contiguous memory, then you may need to
1722 increase this value.
1724 This config option is actually maximum order plus one. For example,
1725 a value of 11 means that the largest free memory block is 2^10 pages.
1728 bool "Timer and CPU usage LEDs"
1729 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1730 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1731 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1732 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1733 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1734 ARCH_AT91 || ARCH_DAVINCI || \
1735 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1737 If you say Y here, the LEDs on your machine will be used
1738 to provide useful information about your current system status.
1740 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1741 be able to select which LEDs are active using the options below. If
1742 you are compiling a kernel for the EBSA-110 or the LART however, the
1743 red LED will simply flash regularly to indicate that the system is
1744 still functional. It is safe to say Y here if you have a CATS
1745 system, but the driver will do nothing.
1748 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1749 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1750 || MACH_OMAP_PERSEUS2
1752 depends on !GENERIC_CLOCKEVENTS
1753 default y if ARCH_EBSA110
1755 If you say Y here, one of the system LEDs (the green one on the
1756 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1757 will flash regularly to indicate that the system is still
1758 operational. This is mainly useful to kernel hackers who are
1759 debugging unstable kernels.
1761 The LART uses the same LED for both Timer LED and CPU usage LED
1762 functions. You may choose to use both, but the Timer LED function
1763 will overrule the CPU usage LED.
1766 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1768 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1769 || MACH_OMAP_PERSEUS2
1772 If you say Y here, the red LED will be used to give a good real
1773 time indication of CPU usage, by lighting whenever the idle task
1774 is not currently executing.
1776 The LART uses the same LED for both Timer LED and CPU usage LED
1777 functions. You may choose to use both, but the Timer LED function
1778 will overrule the CPU usage LED.
1780 config ALIGNMENT_TRAP
1782 depends on CPU_CP15_MMU
1783 default y if !ARCH_EBSA110
1784 select HAVE_PROC_CPU if PROC_FS
1786 ARM processors cannot fetch/store information which is not
1787 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1788 address divisible by 4. On 32-bit ARM processors, these non-aligned
1789 fetch/store instructions will be emulated in software if you say
1790 here, which has a severe performance impact. This is necessary for
1791 correct operation of some network protocols. With an IP-only
1792 configuration it is safe to say N, otherwise say Y.
1794 config UACCESS_WITH_MEMCPY
1795 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1796 depends on MMU && EXPERIMENTAL
1797 default y if CPU_FEROCEON
1799 Implement faster copy_to_user and clear_user methods for CPU
1800 cores where a 8-word STM instruction give significantly higher
1801 memory write throughput than a sequence of individual 32bit stores.
1803 A possible side effect is a slight increase in scheduling latency
1804 between threads sharing the same address space if they invoke
1805 such copy operations with large buffers.
1807 However, if the CPU data cache is using a write-allocate mode,
1808 this option is unlikely to provide any performance gain.
1812 prompt "Enable seccomp to safely compute untrusted bytecode"
1814 This kernel feature is useful for number crunching applications
1815 that may need to compute untrusted bytecode during their
1816 execution. By using pipes or other transports made available to
1817 the process as file descriptors supporting the read/write
1818 syscalls, it's possible to isolate those applications in
1819 their own address space using seccomp. Once seccomp is
1820 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1821 and the task is only allowed to execute a few safe syscalls
1822 defined by each seccomp mode.
1824 config CC_STACKPROTECTOR
1825 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1826 depends on EXPERIMENTAL
1828 This option turns on the -fstack-protector GCC feature. This
1829 feature puts, at the beginning of functions, a canary value on
1830 the stack just before the return address, and validates
1831 the value just before actually returning. Stack based buffer
1832 overflows (that need to overwrite this return address) now also
1833 overwrite the canary, which gets detected and the attack is then
1834 neutralized via a kernel panic.
1835 This feature requires gcc version 4.2 or above.
1837 config DEPRECATED_PARAM_STRUCT
1838 bool "Provide old way to pass kernel parameters"
1840 This was deprecated in 2001 and announced to live on for 5 years.
1841 Some old boot loaders still use this way.
1848 bool "Flattened Device Tree support"
1850 select OF_EARLY_FLATTREE
1853 Include support for flattened device tree machine descriptions.
1855 # Compressed boot loader in ROM. Yes, we really want to ask about
1856 # TEXT and BSS so we preserve their values in the config files.
1857 config ZBOOT_ROM_TEXT
1858 hex "Compressed ROM boot loader base address"
1861 The physical address at which the ROM-able zImage is to be
1862 placed in the target. Platforms which normally make use of
1863 ROM-able zImage formats normally set this to a suitable
1864 value in their defconfig file.
1866 If ZBOOT_ROM is not enabled, this has no effect.
1868 config ZBOOT_ROM_BSS
1869 hex "Compressed ROM boot loader BSS address"
1872 The base address of an area of read/write memory in the target
1873 for the ROM-able zImage which must be available while the
1874 decompressor is running. It must be large enough to hold the
1875 entire decompressed kernel plus an additional 128 KiB.
1876 Platforms which normally make use of ROM-able zImage formats
1877 normally set this to a suitable value in their defconfig file.
1879 If ZBOOT_ROM is not enabled, this has no effect.
1882 bool "Compressed boot loader in ROM/flash"
1883 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1885 Say Y here if you intend to execute your compressed kernel image
1886 (zImage) directly from ROM or flash. If unsure, say N.
1889 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1890 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1891 default ZBOOT_ROM_NONE
1893 Include experimental SD/MMC loading code in the ROM-able zImage.
1894 With this enabled it is possible to write the ROM-able zImage
1895 kernel image to an MMC or SD card and boot the kernel straight
1896 from the reset vector. At reset the processor Mask ROM will load
1897 the first part of the ROM-able zImage which in turn loads the
1898 rest the kernel image to RAM.
1900 config ZBOOT_ROM_NONE
1901 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1903 Do not load image from SD or MMC
1905 config ZBOOT_ROM_MMCIF
1906 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1908 Load image from MMCIF hardware block.
1910 config ZBOOT_ROM_SH_MOBILE_SDHI
1911 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1913 Load image from SDHI hardware block
1917 config ARM_APPENDED_DTB
1918 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1919 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1921 With this option, the boot code will look for a device tree binary
1922 (DTB) appended to zImage
1923 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1925 This is meant as a backward compatibility convenience for those
1926 systems with a bootloader that can't be upgraded to accommodate
1927 the documented boot protocol using a device tree.
1929 Beware that there is very little in terms of protection against
1930 this option being confused by leftover garbage in memory that might
1931 look like a DTB header after a reboot if no actual DTB is appended
1932 to zImage. Do not leave this option active in a production kernel
1933 if you don't intend to always append a DTB. Proper passing of the
1934 location into r2 of a bootloader provided DTB is always preferable
1937 config ARM_ATAG_DTB_COMPAT
1938 bool "Supplement the appended DTB with traditional ATAG information"
1939 depends on ARM_APPENDED_DTB
1941 Some old bootloaders can't be updated to a DTB capable one, yet
1942 they provide ATAGs with memory configuration, the ramdisk address,
1943 the kernel cmdline string, etc. Such information is dynamically
1944 provided by the bootloader and can't always be stored in a static
1945 DTB. To allow a device tree enabled kernel to be used with such
1946 bootloaders, this option allows zImage to extract the information
1947 from the ATAG list and store it at run time into the appended DTB.
1950 string "Default kernel command string"
1953 On some architectures (EBSA110 and CATS), there is currently no way
1954 for the boot loader to pass arguments to the kernel. For these
1955 architectures, you should supply some command-line options at build
1956 time by entering them here. As a minimum, you should specify the
1957 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1960 prompt "Kernel command line type" if CMDLINE != ""
1961 default CMDLINE_FROM_BOOTLOADER
1963 config CMDLINE_FROM_BOOTLOADER
1964 bool "Use bootloader kernel arguments if available"
1966 Uses the command-line options passed by the boot loader. If
1967 the boot loader doesn't provide any, the default kernel command
1968 string provided in CMDLINE will be used.
1970 config CMDLINE_EXTEND
1971 bool "Extend bootloader kernel arguments"
1973 The command-line arguments provided by the boot loader will be
1974 appended to the default kernel command string.
1976 config CMDLINE_FORCE
1977 bool "Always use the default kernel command string"
1979 Always use the default kernel command string, even if the boot
1980 loader passes other arguments to the kernel.
1981 This is useful if you cannot or don't want to change the
1982 command-line options your boot loader passes to the kernel.
1986 bool "Kernel Execute-In-Place from ROM"
1987 depends on !ZBOOT_ROM && !ARM_LPAE
1989 Execute-In-Place allows the kernel to run from non-volatile storage
1990 directly addressable by the CPU, such as NOR flash. This saves RAM
1991 space since the text section of the kernel is not loaded from flash
1992 to RAM. Read-write sections, such as the data section and stack,
1993 are still copied to RAM. The XIP kernel is not compressed since
1994 it has to run directly from flash, so it will take more space to
1995 store it. The flash address used to link the kernel object files,
1996 and for storing it, is configuration dependent. Therefore, if you
1997 say Y here, you must know the proper physical address where to
1998 store the kernel image depending on your own flash memory usage.
2000 Also note that the make target becomes "make xipImage" rather than
2001 "make zImage" or "make Image". The final kernel binary to put in
2002 ROM memory will be arch/arm/boot/xipImage.
2006 config XIP_PHYS_ADDR
2007 hex "XIP Kernel Physical Location"
2008 depends on XIP_KERNEL
2009 default "0x00080000"
2011 This is the physical address in your flash memory the kernel will
2012 be linked for and stored to. This address is dependent on your
2016 bool "Kexec system call (EXPERIMENTAL)"
2017 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2019 kexec is a system call that implements the ability to shutdown your
2020 current kernel, and to start another kernel. It is like a reboot
2021 but it is independent of the system firmware. And like a reboot
2022 you can start any kernel with it, not just Linux.
2024 It is an ongoing process to be certain the hardware in a machine
2025 is properly shutdown, so do not be surprised if this code does not
2026 initially work for you. It may help to enable device hotplugging
2030 bool "Export atags in procfs"
2034 Should the atags used to boot the kernel be exported in an "atags"
2035 file in procfs. Useful with kexec.
2038 bool "Build kdump crash kernel (EXPERIMENTAL)"
2039 depends on EXPERIMENTAL
2041 Generate crash dump after being started by kexec. This should
2042 be normally only set in special crash dump kernels which are
2043 loaded in the main kernel with kexec-tools into a specially
2044 reserved region and then later executed after a crash by
2045 kdump/kexec. The crash dump kernel must be compiled to a
2046 memory address not used by the main kernel
2048 For more details see Documentation/kdump/kdump.txt
2050 config AUTO_ZRELADDR
2051 bool "Auto calculation of the decompressed kernel image address"
2052 depends on !ZBOOT_ROM && !ARCH_U300
2054 ZRELADDR is the physical address where the decompressed kernel
2055 image will be placed. If AUTO_ZRELADDR is selected, the address
2056 will be determined at run-time by masking the current IP with
2057 0xf8000000. This assumes the zImage being placed in the first 128MB
2058 from start of memory.
2062 menu "CPU Power Management"
2066 source "drivers/cpufreq/Kconfig"
2069 tristate "CPUfreq driver for i.MX CPUs"
2070 depends on ARCH_MXC && CPU_FREQ
2072 This enables the CPUfreq driver for i.MX CPUs.
2074 config CPU_FREQ_SA1100
2077 config CPU_FREQ_SA1110
2080 config CPU_FREQ_INTEGRATOR
2081 tristate "CPUfreq driver for ARM Integrator CPUs"
2082 depends on ARCH_INTEGRATOR && CPU_FREQ
2085 This enables the CPUfreq driver for ARM Integrator CPUs.
2087 For details, take a look at <file:Documentation/cpu-freq>.
2093 depends on CPU_FREQ && ARCH_PXA && PXA25x
2095 select CPU_FREQ_TABLE
2096 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2101 Internal configuration node for common cpufreq on Samsung SoC
2103 config CPU_FREQ_S3C24XX
2104 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2105 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2108 This enables the CPUfreq driver for the Samsung S3C24XX family
2111 For details, take a look at <file:Documentation/cpu-freq>.
2115 config CPU_FREQ_S3C24XX_PLL
2116 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2117 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2119 Compile in support for changing the PLL frequency from the
2120 S3C24XX series CPUfreq driver. The PLL takes time to settle
2121 after a frequency change, so by default it is not enabled.
2123 This also means that the PLL tables for the selected CPU(s) will
2124 be built which may increase the size of the kernel image.
2126 config CPU_FREQ_S3C24XX_DEBUG
2127 bool "Debug CPUfreq Samsung driver core"
2128 depends on CPU_FREQ_S3C24XX
2130 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2132 config CPU_FREQ_S3C24XX_IODEBUG
2133 bool "Debug CPUfreq Samsung driver IO timing"
2134 depends on CPU_FREQ_S3C24XX
2136 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2138 config CPU_FREQ_S3C24XX_DEBUGFS
2139 bool "Export debugfs for CPUFreq"
2140 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2142 Export status information via debugfs.
2146 source "drivers/cpuidle/Kconfig"
2150 menu "Floating point emulation"
2152 comment "At least one emulation must be selected"
2155 bool "NWFPE math emulation"
2156 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2158 Say Y to include the NWFPE floating point emulator in the kernel.
2159 This is necessary to run most binaries. Linux does not currently
2160 support floating point hardware so you need to say Y here even if
2161 your machine has an FPA or floating point co-processor podule.
2163 You may say N here if you are going to load the Acorn FPEmulator
2164 early in the bootup.
2167 bool "Support extended precision"
2168 depends on FPE_NWFPE
2170 Say Y to include 80-bit support in the kernel floating-point
2171 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2172 Note that gcc does not generate 80-bit operations by default,
2173 so in most cases this option only enlarges the size of the
2174 floating point emulator without any good reason.
2176 You almost surely want to say N here.
2179 bool "FastFPE math emulation (EXPERIMENTAL)"
2180 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2182 Say Y here to include the FAST floating point emulator in the kernel.
2183 This is an experimental much faster emulator which now also has full
2184 precision for the mantissa. It does not support any exceptions.
2185 It is very simple, and approximately 3-6 times faster than NWFPE.
2187 It should be sufficient for most programs. It may be not suitable
2188 for scientific calculations, but you have to check this for yourself.
2189 If you do not feel you need a faster FP emulation you should better
2193 bool "VFP-format floating point maths"
2194 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2196 Say Y to include VFP support code in the kernel. This is needed
2197 if your hardware includes a VFP unit.
2199 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2200 release notes and additional status information.
2202 Say N if your target does not have VFP hardware.
2210 bool "Advanced SIMD (NEON) Extension support"
2211 depends on VFPv3 && CPU_V7
2213 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2218 menu "Userspace binary formats"
2220 source "fs/Kconfig.binfmt"
2223 tristate "RISC OS personality"
2226 Say Y here to include the kernel code necessary if you want to run
2227 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2228 experimental; if this sounds frightening, say N and sleep in peace.
2229 You can also say M here to compile this support as a module (which
2230 will be called arthur).
2234 menu "Power management options"
2236 source "kernel/power/Kconfig"
2238 config ARCH_SUSPEND_POSSIBLE
2239 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2240 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2241 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2244 config ARM_CPU_SUSPEND
2249 source "net/Kconfig"
2251 source "drivers/Kconfig"
2255 source "arch/arm/Kconfig.debug"
2257 source "security/Kconfig"
2259 source "crypto/Kconfig"
2261 source "lib/Kconfig"