5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
47 config SYS_SUPPORTS_APM_EMULATION
50 config HAVE_SCHED_CLOCK
56 config ARCH_USES_GETTIMEOFFSET
60 config GENERIC_CLOCKEVENTS
63 config GENERIC_CLOCKEVENTS_BROADCAST
65 depends on GENERIC_CLOCKEVENTS
74 select GENERIC_ALLOCATOR
85 The Extended Industry Standard Architecture (EISA) bus was
86 developed as an open alternative to the IBM MicroChannel bus.
88 The EISA bus provided some of the features of the IBM MicroChannel
89 bus while maintaining backward compatibility with cards made for
90 the older ISA bus. The EISA bus saw limited use between 1988 and
91 1995 when it was made obsolete by the PCI bus.
93 Say Y here if you are building a kernel for an EISA-based machine.
103 MicroChannel Architecture is found in some IBM PS/2 machines and
104 laptops. It is a bus system similar to PCI or ISA. See
105 <file:Documentation/mca.txt> (and especially the web page given
106 there) before attempting to build an MCA bus kernel.
108 config STACKTRACE_SUPPORT
112 config HAVE_LATENCYTOP_SUPPORT
117 config LOCKDEP_SUPPORT
121 config TRACE_IRQFLAGS_SUPPORT
125 config HARDIRQS_SW_RESEND
129 config GENERIC_IRQ_PROBE
133 config GENERIC_LOCKBREAK
136 depends on SMP && PREEMPT
138 config RWSEM_GENERIC_SPINLOCK
142 config RWSEM_XCHGADD_ALGORITHM
145 config ARCH_HAS_ILOG2_U32
148 config ARCH_HAS_ILOG2_U64
151 config ARCH_HAS_CPUFREQ
154 Internal node to signify that the ARCH has CPUFREQ support
155 and that the relevant menu configurations are displayed for
158 config ARCH_HAS_CPU_IDLE_WAIT
161 config GENERIC_HWEIGHT
165 config GENERIC_CALIBRATE_DELAY
169 config ARCH_MAY_HAVE_PC_FDC
175 config NEED_DMA_MAP_STATE
178 config GENERIC_ISA_DMA
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
197 depends on EXPERIMENTAL
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary, or theoretically 64K
207 for the MSM machine class.
209 config ARM_PATCH_PHYS_VIRT_16BIT
211 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
213 This option extends the physical to virtual translation patching
214 to allow physical memory down to a theoretical minimum of 64K
217 source "init/Kconfig"
219 source "kernel/Kconfig.freezer"
224 bool "MMU-based Paged Memory Management Support"
227 Select if you want MMU-based virtualised addressing space
228 support by paged memory management. If unsure, say 'Y'.
231 # The "ARM system type" choice list is ordered alphabetically by option
232 # text. Please add new entries in the option alphabetic order.
235 prompt "ARM system type"
236 default ARCH_VERSATILE
238 config ARCH_INTEGRATOR
239 bool "ARM Ltd. Integrator family"
241 select ARCH_HAS_CPUFREQ
244 select GENERIC_CLOCKEVENTS
245 select PLAT_VERSATILE
246 select PLAT_VERSATILE_FPGA_IRQ
248 Support for ARM's Integrator platform.
251 bool "ARM Ltd. RealView family"
255 select GENERIC_CLOCKEVENTS
256 select ARCH_WANT_OPTIONAL_GPIOLIB
257 select PLAT_VERSATILE
258 select PLAT_VERSATILE_CLCD
259 select ARM_TIMER_SP804
260 select GPIO_PL061 if GPIOLIB
262 This enables support for ARM Ltd RealView boards.
264 config ARCH_VERSATILE
265 bool "ARM Ltd. Versatile family"
270 select GENERIC_CLOCKEVENTS
271 select ARCH_WANT_OPTIONAL_GPIOLIB
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_CLCD
274 select PLAT_VERSATILE_FPGA_IRQ
275 select ARM_TIMER_SP804
277 This enables support for ARM Ltd Versatile board.
280 bool "ARM Ltd. Versatile Express family"
281 select ARCH_WANT_OPTIONAL_GPIOLIB
283 select ARM_TIMER_SP804
285 select GENERIC_CLOCKEVENTS
287 select HAVE_PATA_PLATFORM
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
292 This enables support for the ARM Ltd Versatile Express boards.
296 select ARCH_REQUIRE_GPIOLIB
299 select ARM_PATCH_PHYS_VIRT if MMU
301 This enables support for systems based on the Atmel AT91RM9200,
302 AT91SAM9 and AT91CAP9 processors.
305 bool "Broadcom BCMRING"
309 select ARM_TIMER_SP804
311 select GENERIC_CLOCKEVENTS
312 select ARCH_WANT_OPTIONAL_GPIOLIB
314 Support for Broadcom's BCMRing platform.
317 bool "Cirrus Logic CLPS711x/EP721x-based"
319 select ARCH_USES_GETTIMEOFFSET
321 Support for Cirrus Logic 711x/721x based boards.
324 bool "Cavium Networks CNS3XXX family"
326 select GENERIC_CLOCKEVENTS
328 select MIGHT_HAVE_PCI
329 select PCI_DOMAINS if PCI
331 Support for Cavium Networks CNS3XXX platform.
334 bool "Cortina Systems Gemini"
336 select ARCH_REQUIRE_GPIOLIB
337 select ARCH_USES_GETTIMEOFFSET
339 Support for the Cortina Systems Gemini family SoCs
346 select ARCH_USES_GETTIMEOFFSET
348 This is an evaluation board for the StrongARM processor available
349 from Digital. It has limited hardware on-board, including an
350 Ethernet interface, two PCMCIA sockets, two serial ports and a
359 select ARCH_REQUIRE_GPIOLIB
360 select ARCH_HAS_HOLES_MEMORYMODEL
361 select ARCH_USES_GETTIMEOFFSET
363 This enables support for the Cirrus EP93xx series of CPUs.
365 config ARCH_FOOTBRIDGE
369 select GENERIC_CLOCKEVENTS
371 Support for systems based on the DC21285 companion chip
372 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
375 bool "Freescale MXC/iMX-based"
376 select GENERIC_CLOCKEVENTS
377 select ARCH_REQUIRE_GPIOLIB
380 select HAVE_SCHED_CLOCK
382 Support for Freescale MXC/iMX-based family of processors
385 bool "Freescale MXS-based"
386 select GENERIC_CLOCKEVENTS
387 select ARCH_REQUIRE_GPIOLIB
391 Support for Freescale MXS-based family of processors
394 bool "Hilscher NetX based"
398 select GENERIC_CLOCKEVENTS
400 This enables support for systems based on the Hilscher NetX Soc
403 bool "Hynix HMS720x-based"
406 select ARCH_USES_GETTIMEOFFSET
408 This enables support for systems based on the Hynix HMS720x
416 select ARCH_SUPPORTS_MSI
419 Support for Intel's IOP13XX (XScale) family of processors.
427 select ARCH_REQUIRE_GPIOLIB
429 Support for Intel's 80219 and IOP32X (XScale) family of
438 select ARCH_REQUIRE_GPIOLIB
440 Support for Intel's IOP33X (XScale) family of processors.
447 select ARCH_USES_GETTIMEOFFSET
449 Support for Intel's IXP23xx (XScale) family of processors.
452 bool "IXP2400/2800-based"
456 select ARCH_USES_GETTIMEOFFSET
458 Support for Intel's IXP2400/2800 (XScale) family of processors.
466 select GENERIC_CLOCKEVENTS
467 select HAVE_SCHED_CLOCK
468 select MIGHT_HAVE_PCI
469 select DMABOUNCE if PCI
471 Support for Intel's IXP4XX (XScale) family of processors.
477 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
481 Support for the Marvell Dove SoC 88AP510
484 bool "Marvell Kirkwood"
487 select ARCH_REQUIRE_GPIOLIB
488 select GENERIC_CLOCKEVENTS
491 Support for the following Marvell Kirkwood series SoCs:
492 88F6180, 88F6192 and 88F6281.
495 bool "Marvell Loki (88RC8480)"
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Loki (88RC8480) SoC.
506 select ARCH_REQUIRE_GPIOLIB
509 select USB_ARCH_HAS_OHCI
512 select GENERIC_CLOCKEVENTS
514 Support for the NXP LPC32XX family of processors
517 bool "Marvell MV78xx0"
520 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
524 Support for the following Marvell MV78xx0 series SoCs:
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
536 Support for the following Marvell Orion 5x series SoCs:
537 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
538 Orion-2 (5281), Orion-1-90 (6183).
541 bool "Marvell PXA168/910/MMP2"
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
546 select HAVE_SCHED_CLOCK
551 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
554 bool "Micrel/Kendin KS8695"
556 select ARCH_REQUIRE_GPIOLIB
557 select ARCH_USES_GETTIMEOFFSET
559 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
560 System-on-Chip devices.
563 bool "Nuvoton W90X900 CPU"
565 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
570 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
571 At present, the w90x900 has been renamed nuc900, regarding
572 the ARM series product line, you can login the following
573 link address to know more.
575 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
576 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
579 bool "Nuvoton NUC93X CPU"
583 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
584 low-power and high performance MPEG-4/JPEG multimedia controller chip.
591 select GENERIC_CLOCKEVENTS
594 select HAVE_SCHED_CLOCK
595 select ARCH_HAS_BARRIERS if CACHE_L2X0
596 select ARCH_HAS_CPUFREQ
598 This enables support for NVIDIA Tegra based systems (Tegra APX,
599 Tegra 6xx and Tegra 2 series).
602 bool "Philips Nexperia PNX4008 Mobile"
605 select ARCH_USES_GETTIMEOFFSET
607 This enables support for Philips PNX4008 mobile platform.
610 bool "PXA2xx/PXA3xx-based"
613 select ARCH_HAS_CPUFREQ
616 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
618 select HAVE_SCHED_CLOCK
623 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
628 select GENERIC_CLOCKEVENTS
629 select ARCH_REQUIRE_GPIOLIB
632 Support for Qualcomm MSM/QSD based systems. This runs on the
633 apps processor of the MSM/QSD and depends on a shared memory
634 interface to the modem processor which runs the baseband
635 stack and controls some vital subsystems
636 (clock and power control, etc).
639 bool "Renesas SH-Mobile / R-Mobile"
642 select GENERIC_CLOCKEVENTS
645 select MULTI_IRQ_HANDLER
647 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
654 select ARCH_MAY_HAVE_PC_FDC
655 select HAVE_PATA_PLATFORM
658 select ARCH_SPARSEMEM_ENABLE
659 select ARCH_USES_GETTIMEOFFSET
661 On the Acorn Risc-PC, Linux can support the internal IDE disk and
662 CD-ROM interface, serial and parallel port, and the floppy drive.
669 select ARCH_SPARSEMEM_ENABLE
671 select ARCH_HAS_CPUFREQ
673 select GENERIC_CLOCKEVENTS
675 select HAVE_SCHED_CLOCK
677 select ARCH_REQUIRE_GPIOLIB
679 Support for StrongARM 11x0 based boards.
682 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
684 select ARCH_HAS_CPUFREQ
686 select ARCH_USES_GETTIMEOFFSET
687 select HAVE_S3C2410_I2C if I2C
689 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
690 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
691 the Samsung SMDK2410 development board (and derivatives).
693 Note, the S3C2416 and the S3C2450 are so close that they even share
694 the same SoC ID code. This means that there is no separate machine
695 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
698 bool "Samsung S3C64XX"
704 select ARCH_USES_GETTIMEOFFSET
705 select ARCH_HAS_CPUFREQ
706 select ARCH_REQUIRE_GPIOLIB
707 select SAMSUNG_CLKSRC
708 select SAMSUNG_IRQ_VIC_TIMER
709 select SAMSUNG_IRQ_UART
710 select S3C_GPIO_TRACK
711 select S3C_GPIO_PULL_UPDOWN
712 select S3C_GPIO_CFG_S3C24XX
713 select S3C_GPIO_CFG_S3C64XX
715 select USB_ARCH_HAS_OHCI
716 select SAMSUNG_GPIOLIB_4BIT
717 select HAVE_S3C2410_I2C if I2C
718 select HAVE_S3C2410_WATCHDOG if WATCHDOG
720 Samsung S3C64XX series based systems
723 bool "Samsung S5P6440 S5P6450"
727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
728 select GENERIC_CLOCKEVENTS
729 select HAVE_SCHED_CLOCK
730 select HAVE_S3C2410_I2C if I2C
731 select HAVE_S3C_RTC if RTC_CLASS
733 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
737 bool "Samsung S5PC100"
741 select ARM_L1_CACHE_SHIFT_6
742 select ARCH_USES_GETTIMEOFFSET
743 select HAVE_S3C2410_I2C if I2C
744 select HAVE_S3C_RTC if RTC_CLASS
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 Samsung S5PC100 series based systems
750 bool "Samsung S5PV210/S5PC110"
752 select ARCH_SPARSEMEM_ENABLE
755 select ARM_L1_CACHE_SHIFT_6
756 select ARCH_HAS_CPUFREQ
757 select GENERIC_CLOCKEVENTS
758 select HAVE_SCHED_CLOCK
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C_RTC if RTC_CLASS
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 Samsung S5PV210/S5PC110 series based systems
766 bool "Samsung EXYNOS4"
768 select ARCH_SPARSEMEM_ENABLE
771 select ARCH_HAS_CPUFREQ
772 select GENERIC_CLOCKEVENTS
773 select HAVE_S3C_RTC if RTC_CLASS
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 Samsung EXYNOS4 series based systems
786 select ARCH_USES_GETTIMEOFFSET
788 Support for the StrongARM based Digital DNARD machine, also known
789 as "Shark" (<http://www.shark-linux.de/shark.html>).
792 bool "Telechips TCC ARM926-based systems"
797 select GENERIC_CLOCKEVENTS
799 Support for Telechips TCC ARM926-based systems.
802 bool "ST-Ericsson U300 Series"
806 select HAVE_SCHED_CLOCK
810 select GENERIC_CLOCKEVENTS
814 Support for ST-Ericsson U300 series mobile platforms.
817 bool "ST-Ericsson U8500 Series"
820 select GENERIC_CLOCKEVENTS
822 select ARCH_REQUIRE_GPIOLIB
823 select ARCH_HAS_CPUFREQ
825 Support for ST-Ericsson's Ux500 architecture
828 bool "STMicroelectronics Nomadik"
833 select GENERIC_CLOCKEVENTS
834 select ARCH_REQUIRE_GPIOLIB
836 Support for the Nomadik platform by ST-Ericsson
840 select GENERIC_CLOCKEVENTS
841 select ARCH_REQUIRE_GPIOLIB
845 select GENERIC_ALLOCATOR
846 select GENERIC_IRQ_CHIP
847 select ARCH_HAS_HOLES_MEMORYMODEL
849 Support for TI's DaVinci platform.
854 select ARCH_REQUIRE_GPIOLIB
855 select ARCH_HAS_CPUFREQ
856 select GENERIC_CLOCKEVENTS
857 select HAVE_SCHED_CLOCK
858 select ARCH_HAS_HOLES_MEMORYMODEL
860 Support for TI's OMAP platform (OMAP1/2/3/4).
863 bool "Rockchip RK29xx"
865 select HAVE_SCHED_CLOCK
871 select ARM_L1_CACHE_SHIFT_6
873 Support for Rockchip's RK29xx SoCs.
876 bool "Rockchip RK2928"
878 select HAVE_SCHED_CLOCK
882 select MIGHT_HAVE_CACHE_L2X0
883 select ARM_ERRATA_754322
884 select ARM_ERRATA_775420
886 Support for Rockchip's RK2928 SoCs.
889 bool "Rockchip RK30xx/RK3108/RK3168"
891 select HAVE_SCHED_CLOCK
896 select MIGHT_HAVE_CACHE_L2X0
897 select ARM_ERRATA_764369
898 select ARM_ERRATA_754322
899 select ARM_ERRATA_775420
901 Support for Rockchip's RK30xx/RK3108/RK3168 SoCs.
904 bool "Rockchip RK3188"
911 select MIGHT_HAVE_CACHE_L2X0
912 select ARM_ERRATA_764369
913 select ARM_ERRATA_754322
914 select ARM_ERRATA_775420
916 Support for Rockchip's RK3188 SoCs.
921 select ARCH_REQUIRE_GPIOLIB
924 select GENERIC_CLOCKEVENTS
927 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
930 bool "VIA/WonderMedia 85xx"
933 select ARCH_HAS_CPUFREQ
934 select GENERIC_CLOCKEVENTS
935 select ARCH_REQUIRE_GPIOLIB
938 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
942 # This is sorted alphabetically by mach-* pathname. However, plat-*
943 # Kconfigs may be included either alphabetically (according to the
944 # plat- suffix) or along side the corresponding mach-* source.
946 source "arch/arm/mach-at91/Kconfig"
948 source "arch/arm/mach-bcmring/Kconfig"
950 source "arch/arm/mach-clps711x/Kconfig"
952 source "arch/arm/mach-cns3xxx/Kconfig"
954 source "arch/arm/mach-davinci/Kconfig"
956 source "arch/arm/mach-dove/Kconfig"
958 source "arch/arm/mach-ep93xx/Kconfig"
960 source "arch/arm/mach-footbridge/Kconfig"
962 source "arch/arm/mach-gemini/Kconfig"
964 source "arch/arm/mach-h720x/Kconfig"
966 source "arch/arm/mach-integrator/Kconfig"
968 source "arch/arm/mach-iop32x/Kconfig"
970 source "arch/arm/mach-iop33x/Kconfig"
972 source "arch/arm/mach-iop13xx/Kconfig"
974 source "arch/arm/mach-ixp4xx/Kconfig"
976 source "arch/arm/mach-ixp2000/Kconfig"
978 source "arch/arm/mach-ixp23xx/Kconfig"
980 source "arch/arm/mach-kirkwood/Kconfig"
982 source "arch/arm/mach-ks8695/Kconfig"
984 source "arch/arm/mach-loki/Kconfig"
986 source "arch/arm/mach-lpc32xx/Kconfig"
988 source "arch/arm/mach-msm/Kconfig"
990 source "arch/arm/mach-mv78xx0/Kconfig"
992 source "arch/arm/plat-mxc/Kconfig"
994 source "arch/arm/mach-mxs/Kconfig"
996 source "arch/arm/mach-netx/Kconfig"
998 source "arch/arm/mach-nomadik/Kconfig"
999 source "arch/arm/plat-nomadik/Kconfig"
1001 source "arch/arm/mach-nuc93x/Kconfig"
1003 source "arch/arm/plat-omap/Kconfig"
1005 source "arch/arm/mach-omap1/Kconfig"
1007 source "arch/arm/mach-omap2/Kconfig"
1009 source "arch/arm/mach-orion5x/Kconfig"
1011 source "arch/arm/mach-pxa/Kconfig"
1012 source "arch/arm/plat-pxa/Kconfig"
1014 source "arch/arm/mach-mmp/Kconfig"
1016 source "arch/arm/mach-realview/Kconfig"
1018 source "arch/arm/plat-rk/Kconfig"
1019 source "arch/arm/mach-rk29/Kconfig"
1020 source "arch/arm/mach-rk2928/Kconfig"
1021 source "arch/arm/mach-rk30/Kconfig"
1022 source "arch/arm/mach-rk3188/Kconfig"
1024 source "arch/arm/mach-sa1100/Kconfig"
1026 source "arch/arm/plat-samsung/Kconfig"
1027 source "arch/arm/plat-s3c24xx/Kconfig"
1028 source "arch/arm/plat-s5p/Kconfig"
1030 source "arch/arm/plat-spear/Kconfig"
1032 source "arch/arm/plat-tcc/Kconfig"
1035 source "arch/arm/mach-s3c2400/Kconfig"
1036 source "arch/arm/mach-s3c2410/Kconfig"
1037 source "arch/arm/mach-s3c2412/Kconfig"
1038 source "arch/arm/mach-s3c2416/Kconfig"
1039 source "arch/arm/mach-s3c2440/Kconfig"
1040 source "arch/arm/mach-s3c2443/Kconfig"
1044 source "arch/arm/mach-s3c64xx/Kconfig"
1047 source "arch/arm/mach-s5p64x0/Kconfig"
1049 source "arch/arm/mach-s5pc100/Kconfig"
1051 source "arch/arm/mach-s5pv210/Kconfig"
1053 source "arch/arm/mach-exynos4/Kconfig"
1055 source "arch/arm/mach-shmobile/Kconfig"
1057 source "arch/arm/mach-tegra/Kconfig"
1059 source "arch/arm/mach-u300/Kconfig"
1061 source "arch/arm/mach-ux500/Kconfig"
1063 source "arch/arm/mach-versatile/Kconfig"
1065 source "arch/arm/mach-vexpress/Kconfig"
1066 source "arch/arm/plat-versatile/Kconfig"
1068 source "arch/arm/mach-vt8500/Kconfig"
1070 source "arch/arm/mach-w90x900/Kconfig"
1072 # Definitions to make life easier
1078 select GENERIC_CLOCKEVENTS
1079 select HAVE_SCHED_CLOCK
1084 select GENERIC_IRQ_CHIP
1085 select HAVE_SCHED_CLOCK
1092 select CLKDEV_LOOKUP
1093 select ARCH_HAS_CPUFREQ
1094 select GENERIC_CLOCKEVENTS
1095 select ARCH_REQUIRE_GPIOLIB
1097 config PLAT_VERSATILE
1100 config ARM_TIMER_SP804
1104 source arch/arm/mm/Kconfig
1107 bool "Enable iWMMXt support"
1108 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1109 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1111 Enable support for iWMMXt context switching at run time if
1112 running on a CPU that supports it.
1114 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1117 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1121 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1122 (!ARCH_OMAP3 || OMAP3_EMU)
1126 config MULTI_IRQ_HANDLER
1129 Allow each machine to specify it's own IRQ handler at run time.
1132 source "arch/arm/Kconfig-nommu"
1135 config ARM_ERRATA_411920
1136 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1137 depends on CPU_V6 || CPU_V6K
1139 Invalidation of the Instruction Cache operation can
1140 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1141 It does not affect the MPCore. This option enables the ARM Ltd.
1142 recommended workaround.
1144 config ARM_ERRATA_430973
1145 bool "ARM errata: Stale prediction on replaced interworking branch"
1148 This option enables the workaround for the 430973 Cortex-A8
1149 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1150 interworking branch is replaced with another code sequence at the
1151 same virtual address, whether due to self-modifying code or virtual
1152 to physical address re-mapping, Cortex-A8 does not recover from the
1153 stale interworking branch prediction. This results in Cortex-A8
1154 executing the new code sequence in the incorrect ARM or Thumb state.
1155 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1156 and also flushes the branch target cache at every context switch.
1157 Note that setting specific bits in the ACTLR register may not be
1158 available in non-secure mode.
1160 config ARM_ERRATA_458693
1161 bool "ARM errata: Processor deadlock when a false hazard is created"
1164 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1165 erratum. For very specific sequences of memory operations, it is
1166 possible for a hazard condition intended for a cache line to instead
1167 be incorrectly associated with a different cache line. This false
1168 hazard might then cause a processor deadlock. The workaround enables
1169 the L1 caching of the NEON accesses and disables the PLD instruction
1170 in the ACTLR register. Note that setting specific bits in the ACTLR
1171 register may not be available in non-secure mode.
1173 config ARM_ERRATA_460075
1174 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1177 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1178 erratum. Any asynchronous access to the L2 cache may encounter a
1179 situation in which recent store transactions to the L2 cache are lost
1180 and overwritten with stale memory contents from external memory. The
1181 workaround disables the write-allocate mode for the L2 cache via the
1182 ACTLR register. Note that setting specific bits in the ACTLR register
1183 may not be available in non-secure mode.
1185 config ARM_ERRATA_742230
1186 bool "ARM errata: DMB operation may be faulty"
1187 depends on CPU_V7 && SMP
1189 This option enables the workaround for the 742230 Cortex-A9
1190 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1191 between two write operations may not ensure the correct visibility
1192 ordering of the two writes. This workaround sets a specific bit in
1193 the diagnostic register of the Cortex-A9 which causes the DMB
1194 instruction to behave as a DSB, ensuring the correct behaviour of
1197 config ARM_ERRATA_742231
1198 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1199 depends on CPU_V7 && SMP
1201 This option enables the workaround for the 742231 Cortex-A9
1202 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1203 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1204 accessing some data located in the same cache line, may get corrupted
1205 data due to bad handling of the address hazard when the line gets
1206 replaced from one of the CPUs at the same time as another CPU is
1207 accessing it. This workaround sets specific bits in the diagnostic
1208 register of the Cortex-A9 which reduces the linefill issuing
1209 capabilities of the processor.
1211 config PL310_ERRATA_588369
1212 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1213 depends on CACHE_L2X0
1215 The PL310 L2 cache controller implements three types of Clean &
1216 Invalidate maintenance operations: by Physical Address
1217 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1218 They are architecturally defined to behave as the execution of a
1219 clean operation followed immediately by an invalidate operation,
1220 both performing to the same memory location. This functionality
1221 is not correctly implemented in PL310 as clean lines are not
1222 invalidated as a result of these operations.
1224 config ARM_ERRATA_720789
1225 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1226 depends on CPU_V7 && SMP
1228 This option enables the workaround for the 720789 Cortex-A9 (prior to
1229 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1230 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1231 As a consequence of this erratum, some TLB entries which should be
1232 invalidated are not, resulting in an incoherency in the system page
1233 tables. The workaround changes the TLB flushing routines to invalidate
1234 entries regardless of the ASID.
1236 config PL310_ERRATA_727915
1237 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1238 depends on CACHE_L2X0
1240 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1241 operation (offset 0x7FC). This operation runs in background so that
1242 PL310 can handle normal accesses while it is in progress. Under very
1243 rare circumstances, due to this erratum, write data can be lost when
1244 PL310 treats a cacheable write transaction during a Clean &
1245 Invalidate by Way operation.
1247 config ARM_ERRATA_743622
1248 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1251 This option enables the workaround for the 743622 Cortex-A9
1252 (r2p*) erratum. Under very rare conditions, a faulty
1253 optimisation in the Cortex-A9 Store Buffer may lead to data
1254 corruption. This workaround sets a specific bit in the diagnostic
1255 register of the Cortex-A9 which disables the Store Buffer
1256 optimisation, preventing the defect from occurring. This has no
1257 visible impact on the overall performance or power consumption of the
1260 config ARM_ERRATA_751472
1261 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1262 depends on CPU_V7 && SMP
1264 This option enables the workaround for the 751472 Cortex-A9 (prior
1265 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1266 completion of a following broadcasted operation if the second
1267 operation is received by a CPU before the ICIALLUIS has completed,
1268 potentially leading to corrupted entries in the cache or TLB.
1270 config ARM_ERRATA_753970
1271 bool "ARM errata: cache sync operation may be faulty"
1272 depends on CACHE_PL310
1274 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1276 Under some condition the effect of cache sync operation on
1277 the store buffer still remains when the operation completes.
1278 This means that the store buffer is always asked to drain and
1279 this prevents it from merging any further writes. The workaround
1280 is to replace the normal offset of cache sync operation (0x730)
1281 by another offset targeting an unmapped PL310 register 0x740.
1282 This has the same effect as the cache sync operation: store buffer
1283 drain and waiting for all buffers empty.
1285 config ARM_ERRATA_754322
1286 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1289 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1290 r3p*) erratum. A speculative memory access may cause a page table walk
1291 which starts prior to an ASID switch but completes afterwards. This
1292 can populate the micro-TLB with a stale entry which may be hit with
1293 the new ASID. This workaround places two dsb instructions in the mm
1294 switching code so that no page table walks can cross the ASID switch.
1296 config ARM_ERRATA_754327
1297 bool "ARM errata: no automatic Store Buffer drain"
1298 depends on CPU_V7 && SMP
1300 This option enables the workaround for the 754327 Cortex-A9 (prior to
1301 r2p0) erratum. The Store Buffer does not have any automatic draining
1302 mechanism and therefore a livelock may occur if an external agent
1303 continuously polls a memory location waiting to observe an update.
1304 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1305 written polling loops from denying visibility of updates to memory.
1307 config ARM_ERRATA_764369
1308 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1309 depends on CPU_V7 && SMP
1311 This option enables the workaround for erratum 764369
1312 affecting Cortex-A9 MPCore with two or more processors (all
1313 current revisions). Under certain timing circumstances, a data
1314 cache line maintenance operation by MVA targeting an Inner
1315 Shareable memory region may fail to proceed up to either the
1316 Point of Coherency or to the Point of Unification of the
1317 system. This workaround adds a DSB instruction before the
1318 relevant cache maintenance functions and sets a specific bit
1319 in the diagnostic control register of the SCU.
1321 config PL310_ERRATA_769419
1322 bool "PL310 errata: no automatic Store Buffer drain"
1323 depends on CACHE_L2X0
1325 On revisions of the PL310 prior to r3p2, the Store Buffer does
1326 not automatically drain. This can cause normal, non-cacheable
1327 writes to be retained when the memory system is idle, leading
1328 to suboptimal I/O performance for drivers using coherent DMA.
1329 This option adds a write barrier to the cpu_idle loop so that,
1330 on systems with an outer cache, the store buffer is drained
1333 config ARM_ERRATA_775420
1334 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1337 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1338 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1339 operation aborts with MMU exception, it might cause the processor
1340 to deadlock. This workaround puts DSB before executing ISB if
1341 an abort may occur on cache maintenance.
1345 source "arch/arm/common/Kconfig"
1355 Find out whether you have ISA slots on your motherboard. ISA is the
1356 name of a bus system, i.e. the way the CPU talks to the other stuff
1357 inside your box. Other bus systems are PCI, EISA, MicroChannel
1358 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1359 newer boards don't support it. If you have ISA, say Y, otherwise N.
1361 # Select ISA DMA controller support
1366 # Select ISA DMA interface
1371 bool "PCI support" if MIGHT_HAVE_PCI
1373 Find out whether you have a PCI motherboard. PCI is the name of a
1374 bus system, i.e. the way the CPU talks to the other stuff inside
1375 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1376 VESA. If you have PCI, say Y, otherwise N.
1382 config PCI_NANOENGINE
1383 bool "BSE nanoEngine PCI support"
1384 depends on SA1100_NANOENGINE
1386 Enable PCI on the BSE nanoEngine board.
1391 # Select the host bridge type
1392 config PCI_HOST_VIA82C505
1394 depends on PCI && ARCH_SHARK
1397 config PCI_HOST_ITE8152
1399 depends on PCI && MACH_ARMCORE
1403 source "drivers/pci/Kconfig"
1405 source "drivers/pcmcia/Kconfig"
1409 menu "Kernel Features"
1411 source "kernel/time/Kconfig"
1416 This option should be selected by machines which have an SMP-
1419 The only effect of this option is to make the SMP-related
1420 options available to the user for configuration.
1423 bool "Symmetric Multi-Processing"
1424 depends on CPU_V6K || CPU_V7
1425 depends on GENERIC_CLOCKEVENTS
1428 select USE_GENERIC_SMP_HELPERS
1429 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1431 This enables support for systems with more than one CPU. If you have
1432 a system with only one CPU, like most personal computers, say N. If
1433 you have a system with more than one CPU, say Y.
1435 If you say N here, the kernel will run on single and multiprocessor
1436 machines, but will use only one CPU of a multiprocessor machine. If
1437 you say Y here, the kernel will run on many, but not all, single
1438 processor machines. On a single processor machine, the kernel will
1439 run faster if you say N here.
1441 See also <file:Documentation/i386/IO-APIC.txt>,
1442 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1443 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1445 If you don't know what to do here, say N.
1448 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1449 depends on EXPERIMENTAL
1450 depends on SMP && !XIP_KERNEL
1453 SMP kernels contain instructions which fail on non-SMP processors.
1454 Enabling this option allows the kernel to modify itself to make
1455 these instructions safe. Disabling it allows about 1K of space
1458 If you don't know what to do here, say Y.
1464 This option enables support for the ARM system coherency unit
1471 This options enables support for the ARM timer and watchdog unit
1474 prompt "Memory split"
1477 Select the desired split between kernel and user memory.
1479 If you are not absolutely sure what you are doing, leave this
1483 bool "3G/1G user/kernel split"
1485 bool "2G/2G user/kernel split"
1487 bool "1G/3G user/kernel split"
1492 default 0x40000000 if VMSPLIT_1G
1493 default 0x80000000 if VMSPLIT_2G
1497 int "Maximum number of CPUs (2-32)"
1503 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1504 depends on SMP && HOTPLUG && EXPERIMENTAL
1506 Say Y here to experiment with turning CPUs off and on. CPUs
1507 can be controlled through /sys/devices/system/cpu.
1510 bool "Use local timer interrupts"
1513 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT && !RK_TIMER)
1515 Enable support for local timers on SMP platforms, rather then the
1516 legacy IPI broadcast method. Local timers allows the system
1517 accounting to be spread across the timer interval, preventing a
1518 "thundering herd" at every timer tick.
1520 source kernel/Kconfig.preempt
1524 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1525 ARCH_S5PV210 || ARCH_EXYNOS4
1526 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1527 default AT91_TIMER_HZ if ARCH_AT91
1528 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1531 config THUMB2_KERNEL
1532 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1533 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1535 select ARM_ASM_UNIFIED
1537 By enabling this option, the kernel will be compiled in
1538 Thumb-2 mode. A compiler/assembler that understand the unified
1539 ARM-Thumb syntax is needed.
1543 config THUMB2_AVOID_R_ARM_THM_JUMP11
1544 bool "Work around buggy Thumb-2 short branch relocations in gas"
1545 depends on THUMB2_KERNEL && MODULES
1548 Various binutils versions can resolve Thumb-2 branches to
1549 locally-defined, preemptible global symbols as short-range "b.n"
1550 branch instructions.
1552 This is a problem, because there's no guarantee the final
1553 destination of the symbol, or any candidate locations for a
1554 trampoline, are within range of the branch. For this reason, the
1555 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1556 relocation in modules at all, and it makes little sense to add
1559 The symptom is that the kernel fails with an "unsupported
1560 relocation" error when loading some modules.
1562 Until fixed tools are available, passing
1563 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1564 code which hits this problem, at the cost of a bit of extra runtime
1565 stack usage in some cases.
1567 The problem is described in more detail at:
1568 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1570 Only Thumb-2 kernels are affected.
1572 Unless you are sure your tools don't have this problem, say Y.
1574 config ARM_ASM_UNIFIED
1578 bool "Use the ARM EABI to compile the kernel"
1580 This option allows for the kernel to be compiled using the latest
1581 ARM ABI (aka EABI). This is only useful if you are using a user
1582 space environment that is also compiled with EABI.
1584 Since there are major incompatibilities between the legacy ABI and
1585 EABI, especially with regard to structure member alignment, this
1586 option also changes the kernel syscall calling convention to
1587 disambiguate both ABIs and allow for backward compatibility support
1588 (selected with CONFIG_OABI_COMPAT).
1590 To use this you need GCC version 4.0.0 or later.
1593 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1594 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1597 This option preserves the old syscall interface along with the
1598 new (ARM EABI) one. It also provides a compatibility layer to
1599 intercept syscalls that have structure arguments which layout
1600 in memory differs between the legacy ABI and the new ARM EABI
1601 (only for non "thumb" binaries). This option adds a tiny
1602 overhead to all syscalls and produces a slightly larger kernel.
1603 If you know you'll be using only pure EABI user space then you
1604 can say N here. If this option is not selected and you attempt
1605 to execute a legacy ABI binary then the result will be
1606 UNPREDICTABLE (in fact it can be predicted that it won't work
1607 at all). If in doubt say Y.
1609 config ARCH_HAS_HOLES_MEMORYMODEL
1612 config ARCH_SPARSEMEM_ENABLE
1615 config ARCH_SPARSEMEM_DEFAULT
1616 def_bool ARCH_SPARSEMEM_ENABLE
1618 config ARCH_SELECT_MEMORY_MODEL
1619 def_bool ARCH_SPARSEMEM_ENABLE
1621 config HAVE_ARCH_PFN_VALID
1622 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1625 bool "High Memory Support"
1628 The address space of ARM processors is only 4 Gigabytes large
1629 and it has to accommodate user address space, kernel address
1630 space as well as some memory mapped IO. That means that, if you
1631 have a large amount of physical memory and/or IO, not all of the
1632 memory can be "permanently mapped" by the kernel. The physical
1633 memory that is not permanently mapped is called "high memory".
1635 Depending on the selected kernel/user memory split, minimum
1636 vmalloc space and actual amount of RAM, you may not need this
1637 option which should result in a slightly faster kernel.
1642 bool "Allocate 2nd-level pagetables from highmem"
1645 config HW_PERF_EVENTS
1646 bool "Enable hardware performance counter support for perf events"
1647 depends on PERF_EVENTS && CPU_HAS_PMU
1650 Enable hardware performance counter support for perf events. If
1651 disabled, perf events will use software events only.
1655 config FORCE_MAX_ZONEORDER
1656 int "Maximum zone order" if ARCH_SHMOBILE
1657 range 11 64 if ARCH_SHMOBILE
1658 default "9" if SA1111
1661 The kernel memory allocator divides physically contiguous memory
1662 blocks into "zones", where each zone is a power of two number of
1663 pages. This option selects the largest power of two that the kernel
1664 keeps in the memory allocator. If you need to allocate very large
1665 blocks of physically contiguous memory, then you may need to
1666 increase this value.
1668 This config option is actually maximum order plus one. For example,
1669 a value of 11 means that the largest free memory block is 2^10 pages.
1672 bool "Timer and CPU usage LEDs"
1673 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1674 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1675 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1676 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1677 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1678 ARCH_AT91 || ARCH_DAVINCI || \
1679 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1681 If you say Y here, the LEDs on your machine will be used
1682 to provide useful information about your current system status.
1684 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1685 be able to select which LEDs are active using the options below. If
1686 you are compiling a kernel for the EBSA-110 or the LART however, the
1687 red LED will simply flash regularly to indicate that the system is
1688 still functional. It is safe to say Y here if you have a CATS
1689 system, but the driver will do nothing.
1692 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1693 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1694 || MACH_OMAP_PERSEUS2
1696 depends on !GENERIC_CLOCKEVENTS
1697 default y if ARCH_EBSA110
1699 If you say Y here, one of the system LEDs (the green one on the
1700 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1701 will flash regularly to indicate that the system is still
1702 operational. This is mainly useful to kernel hackers who are
1703 debugging unstable kernels.
1705 The LART uses the same LED for both Timer LED and CPU usage LED
1706 functions. You may choose to use both, but the Timer LED function
1707 will overrule the CPU usage LED.
1710 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1712 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1713 || MACH_OMAP_PERSEUS2
1716 If you say Y here, the red LED will be used to give a good real
1717 time indication of CPU usage, by lighting whenever the idle task
1718 is not currently executing.
1720 The LART uses the same LED for both Timer LED and CPU usage LED
1721 functions. You may choose to use both, but the Timer LED function
1722 will overrule the CPU usage LED.
1724 config ALIGNMENT_TRAP
1726 depends on CPU_CP15_MMU
1727 default y if !ARCH_EBSA110
1728 select HAVE_PROC_CPU if PROC_FS
1730 ARM processors cannot fetch/store information which is not
1731 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1732 address divisible by 4. On 32-bit ARM processors, these non-aligned
1733 fetch/store instructions will be emulated in software if you say
1734 here, which has a severe performance impact. This is necessary for
1735 correct operation of some network protocols. With an IP-only
1736 configuration it is safe to say N, otherwise say Y.
1738 config UACCESS_WITH_MEMCPY
1739 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1740 depends on MMU && EXPERIMENTAL
1741 default y if CPU_FEROCEON
1743 Implement faster copy_to_user and clear_user methods for CPU
1744 cores where a 8-word STM instruction give significantly higher
1745 memory write throughput than a sequence of individual 32bit stores.
1747 A possible side effect is a slight increase in scheduling latency
1748 between threads sharing the same address space if they invoke
1749 such copy operations with large buffers.
1751 However, if the CPU data cache is using a write-allocate mode,
1752 this option is unlikely to provide any performance gain.
1756 prompt "Enable seccomp to safely compute untrusted bytecode"
1758 This kernel feature is useful for number crunching applications
1759 that may need to compute untrusted bytecode during their
1760 execution. By using pipes or other transports made available to
1761 the process as file descriptors supporting the read/write
1762 syscalls, it's possible to isolate those applications in
1763 their own address space using seccomp. Once seccomp is
1764 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1765 and the task is only allowed to execute a few safe syscalls
1766 defined by each seccomp mode.
1768 config CC_STACKPROTECTOR
1769 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1770 depends on EXPERIMENTAL
1772 This option turns on the -fstack-protector GCC feature. This
1773 feature puts, at the beginning of functions, a canary value on
1774 the stack just before the return address, and validates
1775 the value just before actually returning. Stack based buffer
1776 overflows (that need to overwrite this return address) now also
1777 overwrite the canary, which gets detected and the attack is then
1778 neutralized via a kernel panic.
1779 This feature requires gcc version 4.2 or above.
1781 config DEPRECATED_PARAM_STRUCT
1782 bool "Provide old way to pass kernel parameters"
1784 This was deprecated in 2001 and announced to live on for 5 years.
1785 Some old boot loaders still use this way.
1787 config ARM_FLUSH_CONSOLE_ON_RESTART
1788 bool "Force flush the console on restart"
1790 If the console is locked while the system is rebooted, the messages
1791 in the temporary logbuffer would not have propogated to all the
1792 console drivers. This option forces the console lock to be
1793 released if it failed to be acquired, which will cause all the
1794 pending messages to be flushed.
1801 bool "Flattened Device Tree support"
1803 select OF_EARLY_FLATTREE
1805 Include support for flattened device tree machine descriptions.
1807 # Compressed boot loader in ROM. Yes, we really want to ask about
1808 # TEXT and BSS so we preserve their values in the config files.
1809 config ZBOOT_ROM_TEXT
1810 hex "Compressed ROM boot loader base address"
1813 The physical address at which the ROM-able zImage is to be
1814 placed in the target. Platforms which normally make use of
1815 ROM-able zImage formats normally set this to a suitable
1816 value in their defconfig file.
1818 If ZBOOT_ROM is not enabled, this has no effect.
1820 config ZBOOT_ROM_BSS
1821 hex "Compressed ROM boot loader BSS address"
1824 The base address of an area of read/write memory in the target
1825 for the ROM-able zImage which must be available while the
1826 decompressor is running. It must be large enough to hold the
1827 entire decompressed kernel plus an additional 128 KiB.
1828 Platforms which normally make use of ROM-able zImage formats
1829 normally set this to a suitable value in their defconfig file.
1831 If ZBOOT_ROM is not enabled, this has no effect.
1834 bool "Compressed boot loader in ROM/flash"
1835 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1837 Say Y here if you intend to execute your compressed kernel image
1838 (zImage) directly from ROM or flash. If unsure, say N.
1840 config ZBOOT_ROM_MMCIF
1841 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1842 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1844 Say Y here to include experimental MMCIF loading code in the
1845 ROM-able zImage. With this enabled it is possible to write the
1846 the ROM-able zImage kernel image to an MMC card and boot the
1847 kernel straight from the reset vector. At reset the processor
1848 Mask ROM will load the first part of the the ROM-able zImage
1849 which in turn loads the rest the kernel image to RAM using the
1850 MMCIF hardware block.
1853 string "Default kernel command string"
1856 On some architectures (EBSA110 and CATS), there is currently no way
1857 for the boot loader to pass arguments to the kernel. For these
1858 architectures, you should supply some command-line options at build
1859 time by entering them here. As a minimum, you should specify the
1860 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1863 prompt "Kernel command line type" if CMDLINE != ""
1864 default CMDLINE_FROM_BOOTLOADER
1866 config CMDLINE_FROM_BOOTLOADER
1867 bool "Use bootloader kernel arguments if available"
1869 Uses the command-line options passed by the boot loader. If
1870 the boot loader doesn't provide any, the default kernel command
1871 string provided in CMDLINE will be used.
1873 config CMDLINE_EXTEND
1874 bool "Extend bootloader kernel arguments"
1876 The command-line arguments provided by the boot loader will be
1877 appended to the default kernel command string.
1879 config CMDLINE_FORCE
1880 bool "Always use the default kernel command string"
1882 Always use the default kernel command string, even if the boot
1883 loader passes other arguments to the kernel.
1884 This is useful if you cannot or don't want to change the
1885 command-line options your boot loader passes to the kernel.
1889 bool "Kernel Execute-In-Place from ROM"
1890 depends on !ZBOOT_ROM
1892 Execute-In-Place allows the kernel to run from non-volatile storage
1893 directly addressable by the CPU, such as NOR flash. This saves RAM
1894 space since the text section of the kernel is not loaded from flash
1895 to RAM. Read-write sections, such as the data section and stack,
1896 are still copied to RAM. The XIP kernel is not compressed since
1897 it has to run directly from flash, so it will take more space to
1898 store it. The flash address used to link the kernel object files,
1899 and for storing it, is configuration dependent. Therefore, if you
1900 say Y here, you must know the proper physical address where to
1901 store the kernel image depending on your own flash memory usage.
1903 Also note that the make target becomes "make xipImage" rather than
1904 "make zImage" or "make Image". The final kernel binary to put in
1905 ROM memory will be arch/arm/boot/xipImage.
1909 config XIP_PHYS_ADDR
1910 hex "XIP Kernel Physical Location"
1911 depends on XIP_KERNEL
1912 default "0x00080000"
1914 This is the physical address in your flash memory the kernel will
1915 be linked for and stored to. This address is dependent on your
1919 bool "Kexec system call (EXPERIMENTAL)"
1920 depends on EXPERIMENTAL
1922 kexec is a system call that implements the ability to shutdown your
1923 current kernel, and to start another kernel. It is like a reboot
1924 but it is independent of the system firmware. And like a reboot
1925 you can start any kernel with it, not just Linux.
1927 It is an ongoing process to be certain the hardware in a machine
1928 is properly shutdown, so do not be surprised if this code does not
1929 initially work for you. It may help to enable device hotplugging
1933 bool "Export atags in procfs"
1937 Should the atags used to boot the kernel be exported in an "atags"
1938 file in procfs. Useful with kexec.
1941 bool "Build kdump crash kernel (EXPERIMENTAL)"
1942 depends on EXPERIMENTAL
1944 Generate crash dump after being started by kexec. This should
1945 be normally only set in special crash dump kernels which are
1946 loaded in the main kernel with kexec-tools into a specially
1947 reserved region and then later executed after a crash by
1948 kdump/kexec. The crash dump kernel must be compiled to a
1949 memory address not used by the main kernel
1951 For more details see Documentation/kdump/kdump.txt
1953 config AUTO_ZRELADDR
1954 bool "Auto calculation of the decompressed kernel image address"
1955 depends on !ZBOOT_ROM && !ARCH_U300
1957 ZRELADDR is the physical address where the decompressed kernel
1958 image will be placed. If AUTO_ZRELADDR is selected, the address
1959 will be determined at run-time by masking the current IP with
1960 0xf8000000. This assumes the zImage being placed in the first 128MB
1961 from start of memory.
1965 menu "CPU Power Management"
1969 source "drivers/cpufreq/Kconfig"
1972 tristate "CPUfreq driver for i.MX CPUs"
1973 depends on ARCH_MXC && CPU_FREQ
1974 select CPU_FREQ_TABLE
1976 This enables the CPUfreq driver for i.MX CPUs.
1978 config CPU_FREQ_SA1100
1981 config CPU_FREQ_SA1110
1984 config CPU_FREQ_INTEGRATOR
1985 tristate "CPUfreq driver for ARM Integrator CPUs"
1986 depends on ARCH_INTEGRATOR && CPU_FREQ
1989 This enables the CPUfreq driver for ARM Integrator CPUs.
1991 For details, take a look at <file:Documentation/cpu-freq>.
1997 depends on CPU_FREQ && ARCH_PXA && PXA25x
1999 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2001 config CPU_FREQ_S3C64XX
2002 bool "CPUfreq support for Samsung S3C64XX CPUs"
2003 depends on CPU_FREQ && CPU_S3C6410
2008 Internal configuration node for common cpufreq on Samsung SoC
2010 config CPU_FREQ_S3C24XX
2011 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2012 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2015 This enables the CPUfreq driver for the Samsung S3C24XX family
2018 For details, take a look at <file:Documentation/cpu-freq>.
2022 config CPU_FREQ_S3C24XX_PLL
2023 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2024 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2026 Compile in support for changing the PLL frequency from the
2027 S3C24XX series CPUfreq driver. The PLL takes time to settle
2028 after a frequency change, so by default it is not enabled.
2030 This also means that the PLL tables for the selected CPU(s) will
2031 be built which may increase the size of the kernel image.
2033 config CPU_FREQ_S3C24XX_DEBUG
2034 bool "Debug CPUfreq Samsung driver core"
2035 depends on CPU_FREQ_S3C24XX
2037 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2039 config CPU_FREQ_S3C24XX_IODEBUG
2040 bool "Debug CPUfreq Samsung driver IO timing"
2041 depends on CPU_FREQ_S3C24XX
2043 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2045 config CPU_FREQ_S3C24XX_DEBUGFS
2046 bool "Export debugfs for CPUFreq"
2047 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2049 Export status information via debugfs.
2053 source "drivers/cpuidle/Kconfig"
2057 menu "Floating point emulation"
2059 comment "At least one emulation must be selected"
2062 bool "NWFPE math emulation"
2063 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2065 Say Y to include the NWFPE floating point emulator in the kernel.
2066 This is necessary to run most binaries. Linux does not currently
2067 support floating point hardware so you need to say Y here even if
2068 your machine has an FPA or floating point co-processor podule.
2070 You may say N here if you are going to load the Acorn FPEmulator
2071 early in the bootup.
2074 bool "Support extended precision"
2075 depends on FPE_NWFPE
2077 Say Y to include 80-bit support in the kernel floating-point
2078 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2079 Note that gcc does not generate 80-bit operations by default,
2080 so in most cases this option only enlarges the size of the
2081 floating point emulator without any good reason.
2083 You almost surely want to say N here.
2086 bool "FastFPE math emulation (EXPERIMENTAL)"
2087 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2089 Say Y here to include the FAST floating point emulator in the kernel.
2090 This is an experimental much faster emulator which now also has full
2091 precision for the mantissa. It does not support any exceptions.
2092 It is very simple, and approximately 3-6 times faster than NWFPE.
2094 It should be sufficient for most programs. It may be not suitable
2095 for scientific calculations, but you have to check this for yourself.
2096 If you do not feel you need a faster FP emulation you should better
2100 bool "VFP-format floating point maths"
2101 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2103 Say Y to include VFP support code in the kernel. This is needed
2104 if your hardware includes a VFP unit.
2106 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2107 release notes and additional status information.
2109 Say N if your target does not have VFP hardware.
2117 bool "Advanced SIMD (NEON) Extension support"
2118 depends on VFPv3 && CPU_V7
2120 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2125 menu "Userspace binary formats"
2127 source "fs/Kconfig.binfmt"
2130 tristate "RISC OS personality"
2133 Say Y here to include the kernel code necessary if you want to run
2134 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2135 experimental; if this sounds frightening, say N and sleep in peace.
2136 You can also say M here to compile this support as a module (which
2137 will be called arthur).
2141 menu "Power management options"
2143 source "kernel/power/Kconfig"
2145 config ARCH_SUSPEND_POSSIBLE
2146 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2147 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2148 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2153 source "net/Kconfig"
2155 source "drivers/Kconfig"
2159 source "arch/arm/Kconfig.debug"
2161 source "security/Kconfig"
2163 source "crypto/Kconfig"
2165 source "lib/Kconfig"