5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
47 config SYS_SUPPORTS_APM_EMULATION
50 config HAVE_SCHED_CLOCK
56 config ARCH_USES_GETTIMEOFFSET
60 config GENERIC_CLOCKEVENTS
63 config GENERIC_CLOCKEVENTS_BROADCAST
65 depends on GENERIC_CLOCKEVENTS
74 select GENERIC_ALLOCATOR
85 The Extended Industry Standard Architecture (EISA) bus was
86 developed as an open alternative to the IBM MicroChannel bus.
88 The EISA bus provided some of the features of the IBM MicroChannel
89 bus while maintaining backward compatibility with cards made for
90 the older ISA bus. The EISA bus saw limited use between 1988 and
91 1995 when it was made obsolete by the PCI bus.
93 Say Y here if you are building a kernel for an EISA-based machine.
103 MicroChannel Architecture is found in some IBM PS/2 machines and
104 laptops. It is a bus system similar to PCI or ISA. See
105 <file:Documentation/mca.txt> (and especially the web page given
106 there) before attempting to build an MCA bus kernel.
108 config STACKTRACE_SUPPORT
112 config HAVE_LATENCYTOP_SUPPORT
117 config LOCKDEP_SUPPORT
121 config TRACE_IRQFLAGS_SUPPORT
125 config HARDIRQS_SW_RESEND
129 config GENERIC_IRQ_PROBE
133 config GENERIC_LOCKBREAK
136 depends on SMP && PREEMPT
138 config RWSEM_GENERIC_SPINLOCK
142 config RWSEM_XCHGADD_ALGORITHM
145 config ARCH_HAS_ILOG2_U32
148 config ARCH_HAS_ILOG2_U64
151 config ARCH_HAS_CPUFREQ
154 Internal node to signify that the ARCH has CPUFREQ support
155 and that the relevant menu configurations are displayed for
158 config ARCH_HAS_CPU_IDLE_WAIT
161 config GENERIC_HWEIGHT
165 config GENERIC_CALIBRATE_DELAY
169 config ARCH_MAY_HAVE_PC_FDC
175 config NEED_DMA_MAP_STATE
178 config GENERIC_ISA_DMA
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
197 depends on EXPERIMENTAL
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary, or theoretically 64K
207 for the MSM machine class.
209 config ARM_PATCH_PHYS_VIRT_16BIT
211 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
213 This option extends the physical to virtual translation patching
214 to allow physical memory down to a theoretical minimum of 64K
217 source "init/Kconfig"
219 source "kernel/Kconfig.freezer"
224 bool "MMU-based Paged Memory Management Support"
227 Select if you want MMU-based virtualised addressing space
228 support by paged memory management. If unsure, say 'Y'.
231 # The "ARM system type" choice list is ordered alphabetically by option
232 # text. Please add new entries in the option alphabetic order.
235 prompt "ARM system type"
236 default ARCH_VERSATILE
238 config ARCH_INTEGRATOR
239 bool "ARM Ltd. Integrator family"
241 select ARCH_HAS_CPUFREQ
244 select GENERIC_CLOCKEVENTS
245 select PLAT_VERSATILE
246 select PLAT_VERSATILE_FPGA_IRQ
248 Support for ARM's Integrator platform.
251 bool "ARM Ltd. RealView family"
255 select GENERIC_CLOCKEVENTS
256 select ARCH_WANT_OPTIONAL_GPIOLIB
257 select PLAT_VERSATILE
258 select PLAT_VERSATILE_CLCD
259 select ARM_TIMER_SP804
260 select GPIO_PL061 if GPIOLIB
262 This enables support for ARM Ltd RealView boards.
264 config ARCH_VERSATILE
265 bool "ARM Ltd. Versatile family"
270 select GENERIC_CLOCKEVENTS
271 select ARCH_WANT_OPTIONAL_GPIOLIB
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_CLCD
274 select PLAT_VERSATILE_FPGA_IRQ
275 select ARM_TIMER_SP804
277 This enables support for ARM Ltd Versatile board.
280 bool "ARM Ltd. Versatile Express family"
281 select ARCH_WANT_OPTIONAL_GPIOLIB
283 select ARM_TIMER_SP804
285 select GENERIC_CLOCKEVENTS
287 select HAVE_PATA_PLATFORM
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
292 This enables support for the ARM Ltd Versatile Express boards.
296 select ARCH_REQUIRE_GPIOLIB
299 select ARM_PATCH_PHYS_VIRT if MMU
301 This enables support for systems based on the Atmel AT91RM9200,
302 AT91SAM9 and AT91CAP9 processors.
305 bool "Broadcom BCMRING"
309 select ARM_TIMER_SP804
311 select GENERIC_CLOCKEVENTS
312 select ARCH_WANT_OPTIONAL_GPIOLIB
314 Support for Broadcom's BCMRing platform.
317 bool "Cirrus Logic CLPS711x/EP721x-based"
319 select ARCH_USES_GETTIMEOFFSET
321 Support for Cirrus Logic 711x/721x based boards.
324 bool "Cavium Networks CNS3XXX family"
326 select GENERIC_CLOCKEVENTS
328 select MIGHT_HAVE_PCI
329 select PCI_DOMAINS if PCI
331 Support for Cavium Networks CNS3XXX platform.
334 bool "Cortina Systems Gemini"
336 select ARCH_REQUIRE_GPIOLIB
337 select ARCH_USES_GETTIMEOFFSET
339 Support for the Cortina Systems Gemini family SoCs
346 select ARCH_USES_GETTIMEOFFSET
348 This is an evaluation board for the StrongARM processor available
349 from Digital. It has limited hardware on-board, including an
350 Ethernet interface, two PCMCIA sockets, two serial ports and a
359 select ARCH_REQUIRE_GPIOLIB
360 select ARCH_HAS_HOLES_MEMORYMODEL
361 select ARCH_USES_GETTIMEOFFSET
363 This enables support for the Cirrus EP93xx series of CPUs.
365 config ARCH_FOOTBRIDGE
369 select GENERIC_CLOCKEVENTS
371 Support for systems based on the DC21285 companion chip
372 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
375 bool "Freescale MXC/iMX-based"
376 select GENERIC_CLOCKEVENTS
377 select ARCH_REQUIRE_GPIOLIB
380 select HAVE_SCHED_CLOCK
382 Support for Freescale MXC/iMX-based family of processors
385 bool "Freescale MXS-based"
386 select GENERIC_CLOCKEVENTS
387 select ARCH_REQUIRE_GPIOLIB
391 Support for Freescale MXS-based family of processors
394 bool "Hilscher NetX based"
398 select GENERIC_CLOCKEVENTS
400 This enables support for systems based on the Hilscher NetX Soc
403 bool "Hynix HMS720x-based"
406 select ARCH_USES_GETTIMEOFFSET
408 This enables support for systems based on the Hynix HMS720x
416 select ARCH_SUPPORTS_MSI
419 Support for Intel's IOP13XX (XScale) family of processors.
427 select ARCH_REQUIRE_GPIOLIB
429 Support for Intel's 80219 and IOP32X (XScale) family of
438 select ARCH_REQUIRE_GPIOLIB
440 Support for Intel's IOP33X (XScale) family of processors.
447 select ARCH_USES_GETTIMEOFFSET
449 Support for Intel's IXP23xx (XScale) family of processors.
452 bool "IXP2400/2800-based"
456 select ARCH_USES_GETTIMEOFFSET
458 Support for Intel's IXP2400/2800 (XScale) family of processors.
466 select GENERIC_CLOCKEVENTS
467 select HAVE_SCHED_CLOCK
468 select MIGHT_HAVE_PCI
469 select DMABOUNCE if PCI
471 Support for Intel's IXP4XX (XScale) family of processors.
477 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
481 Support for the Marvell Dove SoC 88AP510
484 bool "Marvell Kirkwood"
487 select ARCH_REQUIRE_GPIOLIB
488 select GENERIC_CLOCKEVENTS
491 Support for the following Marvell Kirkwood series SoCs:
492 88F6180, 88F6192 and 88F6281.
495 bool "Marvell Loki (88RC8480)"
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Loki (88RC8480) SoC.
506 select ARCH_REQUIRE_GPIOLIB
509 select USB_ARCH_HAS_OHCI
512 select GENERIC_CLOCKEVENTS
514 Support for the NXP LPC32XX family of processors
517 bool "Marvell MV78xx0"
520 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
524 Support for the following Marvell MV78xx0 series SoCs:
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
536 Support for the following Marvell Orion 5x series SoCs:
537 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
538 Orion-2 (5281), Orion-1-90 (6183).
541 bool "Marvell PXA168/910/MMP2"
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
546 select HAVE_SCHED_CLOCK
551 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
554 bool "Micrel/Kendin KS8695"
556 select ARCH_REQUIRE_GPIOLIB
557 select ARCH_USES_GETTIMEOFFSET
559 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
560 System-on-Chip devices.
563 bool "Nuvoton W90X900 CPU"
565 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
570 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
571 At present, the w90x900 has been renamed nuc900, regarding
572 the ARM series product line, you can login the following
573 link address to know more.
575 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
576 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
579 bool "Nuvoton NUC93X CPU"
583 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
584 low-power and high performance MPEG-4/JPEG multimedia controller chip.
591 select GENERIC_CLOCKEVENTS
594 select HAVE_SCHED_CLOCK
595 select ARCH_HAS_BARRIERS if CACHE_L2X0
596 select ARCH_HAS_CPUFREQ
598 This enables support for NVIDIA Tegra based systems (Tegra APX,
599 Tegra 6xx and Tegra 2 series).
602 bool "Philips Nexperia PNX4008 Mobile"
605 select ARCH_USES_GETTIMEOFFSET
607 This enables support for Philips PNX4008 mobile platform.
610 bool "PXA2xx/PXA3xx-based"
613 select ARCH_HAS_CPUFREQ
616 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
618 select HAVE_SCHED_CLOCK
623 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
628 select GENERIC_CLOCKEVENTS
629 select ARCH_REQUIRE_GPIOLIB
632 Support for Qualcomm MSM/QSD based systems. This runs on the
633 apps processor of the MSM/QSD and depends on a shared memory
634 interface to the modem processor which runs the baseband
635 stack and controls some vital subsystems
636 (clock and power control, etc).
639 bool "Renesas SH-Mobile / R-Mobile"
642 select GENERIC_CLOCKEVENTS
645 select MULTI_IRQ_HANDLER
647 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
654 select ARCH_MAY_HAVE_PC_FDC
655 select HAVE_PATA_PLATFORM
658 select ARCH_SPARSEMEM_ENABLE
659 select ARCH_USES_GETTIMEOFFSET
661 On the Acorn Risc-PC, Linux can support the internal IDE disk and
662 CD-ROM interface, serial and parallel port, and the floppy drive.
669 select ARCH_SPARSEMEM_ENABLE
671 select ARCH_HAS_CPUFREQ
673 select GENERIC_CLOCKEVENTS
675 select HAVE_SCHED_CLOCK
677 select ARCH_REQUIRE_GPIOLIB
679 Support for StrongARM 11x0 based boards.
682 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
684 select ARCH_HAS_CPUFREQ
686 select ARCH_USES_GETTIMEOFFSET
687 select HAVE_S3C2410_I2C if I2C
689 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
690 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
691 the Samsung SMDK2410 development board (and derivatives).
693 Note, the S3C2416 and the S3C2450 are so close that they even share
694 the same SoC ID code. This means that there is no separate machine
695 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
698 bool "Samsung S3C64XX"
704 select ARCH_USES_GETTIMEOFFSET
705 select ARCH_HAS_CPUFREQ
706 select ARCH_REQUIRE_GPIOLIB
707 select SAMSUNG_CLKSRC
708 select SAMSUNG_IRQ_VIC_TIMER
709 select SAMSUNG_IRQ_UART
710 select S3C_GPIO_TRACK
711 select S3C_GPIO_PULL_UPDOWN
712 select S3C_GPIO_CFG_S3C24XX
713 select S3C_GPIO_CFG_S3C64XX
715 select USB_ARCH_HAS_OHCI
716 select SAMSUNG_GPIOLIB_4BIT
717 select HAVE_S3C2410_I2C if I2C
718 select HAVE_S3C2410_WATCHDOG if WATCHDOG
720 Samsung S3C64XX series based systems
723 bool "Samsung S5P6440 S5P6450"
727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
728 select GENERIC_CLOCKEVENTS
729 select HAVE_SCHED_CLOCK
730 select HAVE_S3C2410_I2C if I2C
731 select HAVE_S3C_RTC if RTC_CLASS
733 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
737 bool "Samsung S5PC100"
741 select ARM_L1_CACHE_SHIFT_6
742 select ARCH_USES_GETTIMEOFFSET
743 select HAVE_S3C2410_I2C if I2C
744 select HAVE_S3C_RTC if RTC_CLASS
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 Samsung S5PC100 series based systems
750 bool "Samsung S5PV210/S5PC110"
752 select ARCH_SPARSEMEM_ENABLE
755 select ARM_L1_CACHE_SHIFT_6
756 select ARCH_HAS_CPUFREQ
757 select GENERIC_CLOCKEVENTS
758 select HAVE_SCHED_CLOCK
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C_RTC if RTC_CLASS
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 Samsung S5PV210/S5PC110 series based systems
766 bool "Samsung EXYNOS4"
768 select ARCH_SPARSEMEM_ENABLE
771 select ARCH_HAS_CPUFREQ
772 select GENERIC_CLOCKEVENTS
773 select HAVE_S3C_RTC if RTC_CLASS
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 Samsung EXYNOS4 series based systems
786 select ARCH_USES_GETTIMEOFFSET
788 Support for the StrongARM based Digital DNARD machine, also known
789 as "Shark" (<http://www.shark-linux.de/shark.html>).
792 bool "Telechips TCC ARM926-based systems"
797 select GENERIC_CLOCKEVENTS
799 Support for Telechips TCC ARM926-based systems.
802 bool "ST-Ericsson U300 Series"
806 select HAVE_SCHED_CLOCK
810 select GENERIC_CLOCKEVENTS
814 Support for ST-Ericsson U300 series mobile platforms.
817 bool "ST-Ericsson U8500 Series"
820 select GENERIC_CLOCKEVENTS
822 select ARCH_REQUIRE_GPIOLIB
823 select ARCH_HAS_CPUFREQ
825 Support for ST-Ericsson's Ux500 architecture
828 bool "STMicroelectronics Nomadik"
833 select GENERIC_CLOCKEVENTS
834 select ARCH_REQUIRE_GPIOLIB
836 Support for the Nomadik platform by ST-Ericsson
840 select GENERIC_CLOCKEVENTS
841 select ARCH_REQUIRE_GPIOLIB
845 select GENERIC_ALLOCATOR
846 select GENERIC_IRQ_CHIP
847 select ARCH_HAS_HOLES_MEMORYMODEL
849 Support for TI's DaVinci platform.
854 select ARCH_REQUIRE_GPIOLIB
855 select ARCH_HAS_CPUFREQ
856 select GENERIC_CLOCKEVENTS
857 select HAVE_SCHED_CLOCK
858 select ARCH_HAS_HOLES_MEMORYMODEL
860 Support for TI's OMAP platform (OMAP1/2/3/4).
863 bool "Rockchip RK29xx"
870 select ARM_L1_CACHE_SHIFT_6
872 Support for Rockchip's RK29xx SoCs.
875 bool "Rockchip RK30xx"
881 select MIGHT_HAVE_CACHE_L2X0
883 Support for Rockchip's RK30xx SoCs.
888 select ARCH_REQUIRE_GPIOLIB
891 select GENERIC_CLOCKEVENTS
894 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
897 bool "VIA/WonderMedia 85xx"
900 select ARCH_HAS_CPUFREQ
901 select GENERIC_CLOCKEVENTS
902 select ARCH_REQUIRE_GPIOLIB
905 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
909 # This is sorted alphabetically by mach-* pathname. However, plat-*
910 # Kconfigs may be included either alphabetically (according to the
911 # plat- suffix) or along side the corresponding mach-* source.
913 source "arch/arm/mach-at91/Kconfig"
915 source "arch/arm/mach-bcmring/Kconfig"
917 source "arch/arm/mach-clps711x/Kconfig"
919 source "arch/arm/mach-cns3xxx/Kconfig"
921 source "arch/arm/mach-davinci/Kconfig"
923 source "arch/arm/mach-dove/Kconfig"
925 source "arch/arm/mach-ep93xx/Kconfig"
927 source "arch/arm/mach-footbridge/Kconfig"
929 source "arch/arm/mach-gemini/Kconfig"
931 source "arch/arm/mach-h720x/Kconfig"
933 source "arch/arm/mach-integrator/Kconfig"
935 source "arch/arm/mach-iop32x/Kconfig"
937 source "arch/arm/mach-iop33x/Kconfig"
939 source "arch/arm/mach-iop13xx/Kconfig"
941 source "arch/arm/mach-ixp4xx/Kconfig"
943 source "arch/arm/mach-ixp2000/Kconfig"
945 source "arch/arm/mach-ixp23xx/Kconfig"
947 source "arch/arm/mach-kirkwood/Kconfig"
949 source "arch/arm/mach-ks8695/Kconfig"
951 source "arch/arm/mach-loki/Kconfig"
953 source "arch/arm/mach-lpc32xx/Kconfig"
955 source "arch/arm/mach-msm/Kconfig"
957 source "arch/arm/mach-mv78xx0/Kconfig"
959 source "arch/arm/plat-mxc/Kconfig"
961 source "arch/arm/mach-mxs/Kconfig"
963 source "arch/arm/mach-netx/Kconfig"
965 source "arch/arm/mach-nomadik/Kconfig"
966 source "arch/arm/plat-nomadik/Kconfig"
968 source "arch/arm/mach-nuc93x/Kconfig"
970 source "arch/arm/plat-omap/Kconfig"
972 source "arch/arm/mach-omap1/Kconfig"
974 source "arch/arm/mach-omap2/Kconfig"
976 source "arch/arm/mach-orion5x/Kconfig"
978 source "arch/arm/mach-pxa/Kconfig"
979 source "arch/arm/plat-pxa/Kconfig"
981 source "arch/arm/mach-mmp/Kconfig"
983 source "arch/arm/mach-realview/Kconfig"
985 source "arch/arm/plat-rk/Kconfig"
986 source "arch/arm/mach-rk29/Kconfig"
987 source "arch/arm/mach-rk30/Kconfig"
989 source "arch/arm/mach-sa1100/Kconfig"
991 source "arch/arm/plat-samsung/Kconfig"
992 source "arch/arm/plat-s3c24xx/Kconfig"
993 source "arch/arm/plat-s5p/Kconfig"
995 source "arch/arm/plat-spear/Kconfig"
997 source "arch/arm/plat-tcc/Kconfig"
1000 source "arch/arm/mach-s3c2400/Kconfig"
1001 source "arch/arm/mach-s3c2410/Kconfig"
1002 source "arch/arm/mach-s3c2412/Kconfig"
1003 source "arch/arm/mach-s3c2416/Kconfig"
1004 source "arch/arm/mach-s3c2440/Kconfig"
1005 source "arch/arm/mach-s3c2443/Kconfig"
1009 source "arch/arm/mach-s3c64xx/Kconfig"
1012 source "arch/arm/mach-s5p64x0/Kconfig"
1014 source "arch/arm/mach-s5pc100/Kconfig"
1016 source "arch/arm/mach-s5pv210/Kconfig"
1018 source "arch/arm/mach-exynos4/Kconfig"
1020 source "arch/arm/mach-shmobile/Kconfig"
1022 source "arch/arm/mach-tegra/Kconfig"
1024 source "arch/arm/mach-u300/Kconfig"
1026 source "arch/arm/mach-ux500/Kconfig"
1028 source "arch/arm/mach-versatile/Kconfig"
1030 source "arch/arm/mach-vexpress/Kconfig"
1031 source "arch/arm/plat-versatile/Kconfig"
1033 source "arch/arm/mach-vt8500/Kconfig"
1035 source "arch/arm/mach-w90x900/Kconfig"
1037 # Definitions to make life easier
1043 select GENERIC_CLOCKEVENTS
1044 select HAVE_SCHED_CLOCK
1049 select GENERIC_IRQ_CHIP
1050 select HAVE_SCHED_CLOCK
1057 select CLKDEV_LOOKUP
1058 select HAVE_SCHED_CLOCK
1059 select ARCH_HAS_CPUFREQ
1060 select GENERIC_CLOCKEVENTS
1061 select ARCH_REQUIRE_GPIOLIB
1063 config PLAT_VERSATILE
1066 config ARM_TIMER_SP804
1070 source arch/arm/mm/Kconfig
1073 bool "Enable iWMMXt support"
1074 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1075 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1077 Enable support for iWMMXt context switching at run time if
1078 running on a CPU that supports it.
1080 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1083 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1087 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1088 (!ARCH_OMAP3 || OMAP3_EMU)
1092 config MULTI_IRQ_HANDLER
1095 Allow each machine to specify it's own IRQ handler at run time.
1098 source "arch/arm/Kconfig-nommu"
1101 config ARM_ERRATA_411920
1102 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1103 depends on CPU_V6 || CPU_V6K
1105 Invalidation of the Instruction Cache operation can
1106 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1107 It does not affect the MPCore. This option enables the ARM Ltd.
1108 recommended workaround.
1110 config ARM_ERRATA_430973
1111 bool "ARM errata: Stale prediction on replaced interworking branch"
1114 This option enables the workaround for the 430973 Cortex-A8
1115 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1116 interworking branch is replaced with another code sequence at the
1117 same virtual address, whether due to self-modifying code or virtual
1118 to physical address re-mapping, Cortex-A8 does not recover from the
1119 stale interworking branch prediction. This results in Cortex-A8
1120 executing the new code sequence in the incorrect ARM or Thumb state.
1121 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1122 and also flushes the branch target cache at every context switch.
1123 Note that setting specific bits in the ACTLR register may not be
1124 available in non-secure mode.
1126 config ARM_ERRATA_458693
1127 bool "ARM errata: Processor deadlock when a false hazard is created"
1130 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1131 erratum. For very specific sequences of memory operations, it is
1132 possible for a hazard condition intended for a cache line to instead
1133 be incorrectly associated with a different cache line. This false
1134 hazard might then cause a processor deadlock. The workaround enables
1135 the L1 caching of the NEON accesses and disables the PLD instruction
1136 in the ACTLR register. Note that setting specific bits in the ACTLR
1137 register may not be available in non-secure mode.
1139 config ARM_ERRATA_460075
1140 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1143 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1144 erratum. Any asynchronous access to the L2 cache may encounter a
1145 situation in which recent store transactions to the L2 cache are lost
1146 and overwritten with stale memory contents from external memory. The
1147 workaround disables the write-allocate mode for the L2 cache via the
1148 ACTLR register. Note that setting specific bits in the ACTLR register
1149 may not be available in non-secure mode.
1151 config ARM_ERRATA_742230
1152 bool "ARM errata: DMB operation may be faulty"
1153 depends on CPU_V7 && SMP
1155 This option enables the workaround for the 742230 Cortex-A9
1156 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1157 between two write operations may not ensure the correct visibility
1158 ordering of the two writes. This workaround sets a specific bit in
1159 the diagnostic register of the Cortex-A9 which causes the DMB
1160 instruction to behave as a DSB, ensuring the correct behaviour of
1163 config ARM_ERRATA_742231
1164 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1165 depends on CPU_V7 && SMP
1167 This option enables the workaround for the 742231 Cortex-A9
1168 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1169 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1170 accessing some data located in the same cache line, may get corrupted
1171 data due to bad handling of the address hazard when the line gets
1172 replaced from one of the CPUs at the same time as another CPU is
1173 accessing it. This workaround sets specific bits in the diagnostic
1174 register of the Cortex-A9 which reduces the linefill issuing
1175 capabilities of the processor.
1177 config PL310_ERRATA_588369
1178 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1179 depends on CACHE_L2X0
1181 The PL310 L2 cache controller implements three types of Clean &
1182 Invalidate maintenance operations: by Physical Address
1183 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1184 They are architecturally defined to behave as the execution of a
1185 clean operation followed immediately by an invalidate operation,
1186 both performing to the same memory location. This functionality
1187 is not correctly implemented in PL310 as clean lines are not
1188 invalidated as a result of these operations.
1190 config ARM_ERRATA_720789
1191 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1192 depends on CPU_V7 && SMP
1194 This option enables the workaround for the 720789 Cortex-A9 (prior to
1195 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1196 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1197 As a consequence of this erratum, some TLB entries which should be
1198 invalidated are not, resulting in an incoherency in the system page
1199 tables. The workaround changes the TLB flushing routines to invalidate
1200 entries regardless of the ASID.
1202 config PL310_ERRATA_727915
1203 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1204 depends on CACHE_L2X0
1206 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1207 operation (offset 0x7FC). This operation runs in background so that
1208 PL310 can handle normal accesses while it is in progress. Under very
1209 rare circumstances, due to this erratum, write data can be lost when
1210 PL310 treats a cacheable write transaction during a Clean &
1211 Invalidate by Way operation.
1213 config ARM_ERRATA_743622
1214 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1217 This option enables the workaround for the 743622 Cortex-A9
1218 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1219 optimisation in the Cortex-A9 Store Buffer may lead to data
1220 corruption. This workaround sets a specific bit in the diagnostic
1221 register of the Cortex-A9 which disables the Store Buffer
1222 optimisation, preventing the defect from occurring. This has no
1223 visible impact on the overall performance or power consumption of the
1226 config ARM_ERRATA_751472
1227 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1228 depends on CPU_V7 && SMP
1230 This option enables the workaround for the 751472 Cortex-A9 (prior
1231 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1232 completion of a following broadcasted operation if the second
1233 operation is received by a CPU before the ICIALLUIS has completed,
1234 potentially leading to corrupted entries in the cache or TLB.
1236 config ARM_ERRATA_753970
1237 bool "ARM errata: cache sync operation may be faulty"
1238 depends on CACHE_PL310
1240 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1242 Under some condition the effect of cache sync operation on
1243 the store buffer still remains when the operation completes.
1244 This means that the store buffer is always asked to drain and
1245 this prevents it from merging any further writes. The workaround
1246 is to replace the normal offset of cache sync operation (0x730)
1247 by another offset targeting an unmapped PL310 register 0x740.
1248 This has the same effect as the cache sync operation: store buffer
1249 drain and waiting for all buffers empty.
1251 config ARM_ERRATA_754322
1252 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1255 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1256 r3p*) erratum. A speculative memory access may cause a page table walk
1257 which starts prior to an ASID switch but completes afterwards. This
1258 can populate the micro-TLB with a stale entry which may be hit with
1259 the new ASID. This workaround places two dsb instructions in the mm
1260 switching code so that no page table walks can cross the ASID switch.
1262 config ARM_ERRATA_754327
1263 bool "ARM errata: no automatic Store Buffer drain"
1264 depends on CPU_V7 && SMP
1266 This option enables the workaround for the 754327 Cortex-A9 (prior to
1267 r2p0) erratum. The Store Buffer does not have any automatic draining
1268 mechanism and therefore a livelock may occur if an external agent
1269 continuously polls a memory location waiting to observe an update.
1270 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1271 written polling loops from denying visibility of updates to memory.
1275 source "arch/arm/common/Kconfig"
1285 Find out whether you have ISA slots on your motherboard. ISA is the
1286 name of a bus system, i.e. the way the CPU talks to the other stuff
1287 inside your box. Other bus systems are PCI, EISA, MicroChannel
1288 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1289 newer boards don't support it. If you have ISA, say Y, otherwise N.
1291 # Select ISA DMA controller support
1296 # Select ISA DMA interface
1301 bool "PCI support" if MIGHT_HAVE_PCI
1303 Find out whether you have a PCI motherboard. PCI is the name of a
1304 bus system, i.e. the way the CPU talks to the other stuff inside
1305 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1306 VESA. If you have PCI, say Y, otherwise N.
1312 config PCI_NANOENGINE
1313 bool "BSE nanoEngine PCI support"
1314 depends on SA1100_NANOENGINE
1316 Enable PCI on the BSE nanoEngine board.
1321 # Select the host bridge type
1322 config PCI_HOST_VIA82C505
1324 depends on PCI && ARCH_SHARK
1327 config PCI_HOST_ITE8152
1329 depends on PCI && MACH_ARMCORE
1333 source "drivers/pci/Kconfig"
1335 source "drivers/pcmcia/Kconfig"
1337 config ARM_ERRATA_764369
1338 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1339 depends on CPU_V7 && SMP
1341 This option enables the workaround for erratum 764369
1342 affecting Cortex-A9 MPCore with two or more processors (all
1343 current revisions). Under certain timing circumstances, a data
1344 cache line maintenance operation by MVA targeting an Inner
1345 Shareable memory region may fail to proceed up to either the
1346 Point of Coherency or to the Point of Unification of the
1347 system. This workaround adds a DSB instruction before the
1348 relevant cache maintenance functions and sets a specific bit
1349 in the diagnostic control register of the SCU.
1353 menu "Kernel Features"
1355 source "kernel/time/Kconfig"
1360 This option should be selected by machines which have an SMP-
1363 The only effect of this option is to make the SMP-related
1364 options available to the user for configuration.
1367 bool "Symmetric Multi-Processing"
1368 depends on CPU_V6K || CPU_V7
1369 depends on GENERIC_CLOCKEVENTS
1372 select USE_GENERIC_SMP_HELPERS
1373 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1375 This enables support for systems with more than one CPU. If you have
1376 a system with only one CPU, like most personal computers, say N. If
1377 you have a system with more than one CPU, say Y.
1379 If you say N here, the kernel will run on single and multiprocessor
1380 machines, but will use only one CPU of a multiprocessor machine. If
1381 you say Y here, the kernel will run on many, but not all, single
1382 processor machines. On a single processor machine, the kernel will
1383 run faster if you say N here.
1385 See also <file:Documentation/i386/IO-APIC.txt>,
1386 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1387 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1389 If you don't know what to do here, say N.
1392 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1393 depends on EXPERIMENTAL
1394 depends on SMP && !XIP_KERNEL
1397 SMP kernels contain instructions which fail on non-SMP processors.
1398 Enabling this option allows the kernel to modify itself to make
1399 these instructions safe. Disabling it allows about 1K of space
1402 If you don't know what to do here, say Y.
1408 This option enables support for the ARM system coherency unit
1415 This options enables support for the ARM timer and watchdog unit
1418 prompt "Memory split"
1421 Select the desired split between kernel and user memory.
1423 If you are not absolutely sure what you are doing, leave this
1427 bool "3G/1G user/kernel split"
1429 bool "2G/2G user/kernel split"
1431 bool "1G/3G user/kernel split"
1436 default 0x40000000 if VMSPLIT_1G
1437 default 0x80000000 if VMSPLIT_2G
1441 int "Maximum number of CPUs (2-32)"
1447 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1448 depends on SMP && HOTPLUG && EXPERIMENTAL
1450 Say Y here to experiment with turning CPUs off and on. CPUs
1451 can be controlled through /sys/devices/system/cpu.
1454 bool "Use local timer interrupts"
1457 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1459 Enable support for local timers on SMP platforms, rather then the
1460 legacy IPI broadcast method. Local timers allows the system
1461 accounting to be spread across the timer interval, preventing a
1462 "thundering herd" at every timer tick.
1464 source kernel/Kconfig.preempt
1468 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1469 ARCH_S5PV210 || ARCH_EXYNOS4
1470 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1471 default AT91_TIMER_HZ if ARCH_AT91
1472 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1475 config THUMB2_KERNEL
1476 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1477 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1479 select ARM_ASM_UNIFIED
1481 By enabling this option, the kernel will be compiled in
1482 Thumb-2 mode. A compiler/assembler that understand the unified
1483 ARM-Thumb syntax is needed.
1487 config THUMB2_AVOID_R_ARM_THM_JUMP11
1488 bool "Work around buggy Thumb-2 short branch relocations in gas"
1489 depends on THUMB2_KERNEL && MODULES
1492 Various binutils versions can resolve Thumb-2 branches to
1493 locally-defined, preemptible global symbols as short-range "b.n"
1494 branch instructions.
1496 This is a problem, because there's no guarantee the final
1497 destination of the symbol, or any candidate locations for a
1498 trampoline, are within range of the branch. For this reason, the
1499 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1500 relocation in modules at all, and it makes little sense to add
1503 The symptom is that the kernel fails with an "unsupported
1504 relocation" error when loading some modules.
1506 Until fixed tools are available, passing
1507 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1508 code which hits this problem, at the cost of a bit of extra runtime
1509 stack usage in some cases.
1511 The problem is described in more detail at:
1512 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1514 Only Thumb-2 kernels are affected.
1516 Unless you are sure your tools don't have this problem, say Y.
1518 config ARM_ASM_UNIFIED
1522 bool "Use the ARM EABI to compile the kernel"
1524 This option allows for the kernel to be compiled using the latest
1525 ARM ABI (aka EABI). This is only useful if you are using a user
1526 space environment that is also compiled with EABI.
1528 Since there are major incompatibilities between the legacy ABI and
1529 EABI, especially with regard to structure member alignment, this
1530 option also changes the kernel syscall calling convention to
1531 disambiguate both ABIs and allow for backward compatibility support
1532 (selected with CONFIG_OABI_COMPAT).
1534 To use this you need GCC version 4.0.0 or later.
1537 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1538 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1541 This option preserves the old syscall interface along with the
1542 new (ARM EABI) one. It also provides a compatibility layer to
1543 intercept syscalls that have structure arguments which layout
1544 in memory differs between the legacy ABI and the new ARM EABI
1545 (only for non "thumb" binaries). This option adds a tiny
1546 overhead to all syscalls and produces a slightly larger kernel.
1547 If you know you'll be using only pure EABI user space then you
1548 can say N here. If this option is not selected and you attempt
1549 to execute a legacy ABI binary then the result will be
1550 UNPREDICTABLE (in fact it can be predicted that it won't work
1551 at all). If in doubt say Y.
1553 config ARCH_HAS_HOLES_MEMORYMODEL
1556 config ARCH_SPARSEMEM_ENABLE
1559 config ARCH_SPARSEMEM_DEFAULT
1560 def_bool ARCH_SPARSEMEM_ENABLE
1562 config ARCH_SELECT_MEMORY_MODEL
1563 def_bool ARCH_SPARSEMEM_ENABLE
1565 config HAVE_ARCH_PFN_VALID
1566 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1569 bool "High Memory Support"
1572 The address space of ARM processors is only 4 Gigabytes large
1573 and it has to accommodate user address space, kernel address
1574 space as well as some memory mapped IO. That means that, if you
1575 have a large amount of physical memory and/or IO, not all of the
1576 memory can be "permanently mapped" by the kernel. The physical
1577 memory that is not permanently mapped is called "high memory".
1579 Depending on the selected kernel/user memory split, minimum
1580 vmalloc space and actual amount of RAM, you may not need this
1581 option which should result in a slightly faster kernel.
1586 bool "Allocate 2nd-level pagetables from highmem"
1589 config HW_PERF_EVENTS
1590 bool "Enable hardware performance counter support for perf events"
1591 depends on PERF_EVENTS && CPU_HAS_PMU
1594 Enable hardware performance counter support for perf events. If
1595 disabled, perf events will use software events only.
1599 config FORCE_MAX_ZONEORDER
1600 int "Maximum zone order" if ARCH_SHMOBILE
1601 range 11 64 if ARCH_SHMOBILE
1602 default "9" if SA1111
1605 The kernel memory allocator divides physically contiguous memory
1606 blocks into "zones", where each zone is a power of two number of
1607 pages. This option selects the largest power of two that the kernel
1608 keeps in the memory allocator. If you need to allocate very large
1609 blocks of physically contiguous memory, then you may need to
1610 increase this value.
1612 This config option is actually maximum order plus one. For example,
1613 a value of 11 means that the largest free memory block is 2^10 pages.
1616 bool "Timer and CPU usage LEDs"
1617 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1618 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1619 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1620 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1621 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1622 ARCH_AT91 || ARCH_DAVINCI || \
1623 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1625 If you say Y here, the LEDs on your machine will be used
1626 to provide useful information about your current system status.
1628 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1629 be able to select which LEDs are active using the options below. If
1630 you are compiling a kernel for the EBSA-110 or the LART however, the
1631 red LED will simply flash regularly to indicate that the system is
1632 still functional. It is safe to say Y here if you have a CATS
1633 system, but the driver will do nothing.
1636 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1637 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1638 || MACH_OMAP_PERSEUS2
1640 depends on !GENERIC_CLOCKEVENTS
1641 default y if ARCH_EBSA110
1643 If you say Y here, one of the system LEDs (the green one on the
1644 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1645 will flash regularly to indicate that the system is still
1646 operational. This is mainly useful to kernel hackers who are
1647 debugging unstable kernels.
1649 The LART uses the same LED for both Timer LED and CPU usage LED
1650 functions. You may choose to use both, but the Timer LED function
1651 will overrule the CPU usage LED.
1654 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1656 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1657 || MACH_OMAP_PERSEUS2
1660 If you say Y here, the red LED will be used to give a good real
1661 time indication of CPU usage, by lighting whenever the idle task
1662 is not currently executing.
1664 The LART uses the same LED for both Timer LED and CPU usage LED
1665 functions. You may choose to use both, but the Timer LED function
1666 will overrule the CPU usage LED.
1668 config ALIGNMENT_TRAP
1670 depends on CPU_CP15_MMU
1671 default y if !ARCH_EBSA110
1672 select HAVE_PROC_CPU if PROC_FS
1674 ARM processors cannot fetch/store information which is not
1675 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1676 address divisible by 4. On 32-bit ARM processors, these non-aligned
1677 fetch/store instructions will be emulated in software if you say
1678 here, which has a severe performance impact. This is necessary for
1679 correct operation of some network protocols. With an IP-only
1680 configuration it is safe to say N, otherwise say Y.
1682 config UACCESS_WITH_MEMCPY
1683 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1684 depends on MMU && EXPERIMENTAL
1685 default y if CPU_FEROCEON
1687 Implement faster copy_to_user and clear_user methods for CPU
1688 cores where a 8-word STM instruction give significantly higher
1689 memory write throughput than a sequence of individual 32bit stores.
1691 A possible side effect is a slight increase in scheduling latency
1692 between threads sharing the same address space if they invoke
1693 such copy operations with large buffers.
1695 However, if the CPU data cache is using a write-allocate mode,
1696 this option is unlikely to provide any performance gain.
1700 prompt "Enable seccomp to safely compute untrusted bytecode"
1702 This kernel feature is useful for number crunching applications
1703 that may need to compute untrusted bytecode during their
1704 execution. By using pipes or other transports made available to
1705 the process as file descriptors supporting the read/write
1706 syscalls, it's possible to isolate those applications in
1707 their own address space using seccomp. Once seccomp is
1708 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1709 and the task is only allowed to execute a few safe syscalls
1710 defined by each seccomp mode.
1712 config CC_STACKPROTECTOR
1713 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1714 depends on EXPERIMENTAL
1716 This option turns on the -fstack-protector GCC feature. This
1717 feature puts, at the beginning of functions, a canary value on
1718 the stack just before the return address, and validates
1719 the value just before actually returning. Stack based buffer
1720 overflows (that need to overwrite this return address) now also
1721 overwrite the canary, which gets detected and the attack is then
1722 neutralized via a kernel panic.
1723 This feature requires gcc version 4.2 or above.
1725 config DEPRECATED_PARAM_STRUCT
1726 bool "Provide old way to pass kernel parameters"
1728 This was deprecated in 2001 and announced to live on for 5 years.
1729 Some old boot loaders still use this way.
1731 config ARM_FLUSH_CONSOLE_ON_RESTART
1732 bool "Force flush the console on restart"
1734 If the console is locked while the system is rebooted, the messages
1735 in the temporary logbuffer would not have propogated to all the
1736 console drivers. This option forces the console lock to be
1737 released if it failed to be acquired, which will cause all the
1738 pending messages to be flushed.
1745 bool "Flattened Device Tree support"
1747 select OF_EARLY_FLATTREE
1749 Include support for flattened device tree machine descriptions.
1751 # Compressed boot loader in ROM. Yes, we really want to ask about
1752 # TEXT and BSS so we preserve their values in the config files.
1753 config ZBOOT_ROM_TEXT
1754 hex "Compressed ROM boot loader base address"
1757 The physical address at which the ROM-able zImage is to be
1758 placed in the target. Platforms which normally make use of
1759 ROM-able zImage formats normally set this to a suitable
1760 value in their defconfig file.
1762 If ZBOOT_ROM is not enabled, this has no effect.
1764 config ZBOOT_ROM_BSS
1765 hex "Compressed ROM boot loader BSS address"
1768 The base address of an area of read/write memory in the target
1769 for the ROM-able zImage which must be available while the
1770 decompressor is running. It must be large enough to hold the
1771 entire decompressed kernel plus an additional 128 KiB.
1772 Platforms which normally make use of ROM-able zImage formats
1773 normally set this to a suitable value in their defconfig file.
1775 If ZBOOT_ROM is not enabled, this has no effect.
1778 bool "Compressed boot loader in ROM/flash"
1779 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1781 Say Y here if you intend to execute your compressed kernel image
1782 (zImage) directly from ROM or flash. If unsure, say N.
1784 config ZBOOT_ROM_MMCIF
1785 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1786 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1788 Say Y here to include experimental MMCIF loading code in the
1789 ROM-able zImage. With this enabled it is possible to write the
1790 the ROM-able zImage kernel image to an MMC card and boot the
1791 kernel straight from the reset vector. At reset the processor
1792 Mask ROM will load the first part of the the ROM-able zImage
1793 which in turn loads the rest the kernel image to RAM using the
1794 MMCIF hardware block.
1797 string "Default kernel command string"
1800 On some architectures (EBSA110 and CATS), there is currently no way
1801 for the boot loader to pass arguments to the kernel. For these
1802 architectures, you should supply some command-line options at build
1803 time by entering them here. As a minimum, you should specify the
1804 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1807 prompt "Kernel command line type" if CMDLINE != ""
1808 default CMDLINE_FROM_BOOTLOADER
1810 config CMDLINE_FROM_BOOTLOADER
1811 bool "Use bootloader kernel arguments if available"
1813 Uses the command-line options passed by the boot loader. If
1814 the boot loader doesn't provide any, the default kernel command
1815 string provided in CMDLINE will be used.
1817 config CMDLINE_EXTEND
1818 bool "Extend bootloader kernel arguments"
1820 The command-line arguments provided by the boot loader will be
1821 appended to the default kernel command string.
1823 config CMDLINE_FORCE
1824 bool "Always use the default kernel command string"
1826 Always use the default kernel command string, even if the boot
1827 loader passes other arguments to the kernel.
1828 This is useful if you cannot or don't want to change the
1829 command-line options your boot loader passes to the kernel.
1833 bool "Kernel Execute-In-Place from ROM"
1834 depends on !ZBOOT_ROM
1836 Execute-In-Place allows the kernel to run from non-volatile storage
1837 directly addressable by the CPU, such as NOR flash. This saves RAM
1838 space since the text section of the kernel is not loaded from flash
1839 to RAM. Read-write sections, such as the data section and stack,
1840 are still copied to RAM. The XIP kernel is not compressed since
1841 it has to run directly from flash, so it will take more space to
1842 store it. The flash address used to link the kernel object files,
1843 and for storing it, is configuration dependent. Therefore, if you
1844 say Y here, you must know the proper physical address where to
1845 store the kernel image depending on your own flash memory usage.
1847 Also note that the make target becomes "make xipImage" rather than
1848 "make zImage" or "make Image". The final kernel binary to put in
1849 ROM memory will be arch/arm/boot/xipImage.
1853 config XIP_PHYS_ADDR
1854 hex "XIP Kernel Physical Location"
1855 depends on XIP_KERNEL
1856 default "0x00080000"
1858 This is the physical address in your flash memory the kernel will
1859 be linked for and stored to. This address is dependent on your
1863 bool "Kexec system call (EXPERIMENTAL)"
1864 depends on EXPERIMENTAL
1866 kexec is a system call that implements the ability to shutdown your
1867 current kernel, and to start another kernel. It is like a reboot
1868 but it is independent of the system firmware. And like a reboot
1869 you can start any kernel with it, not just Linux.
1871 It is an ongoing process to be certain the hardware in a machine
1872 is properly shutdown, so do not be surprised if this code does not
1873 initially work for you. It may help to enable device hotplugging
1877 bool "Export atags in procfs"
1881 Should the atags used to boot the kernel be exported in an "atags"
1882 file in procfs. Useful with kexec.
1885 bool "Build kdump crash kernel (EXPERIMENTAL)"
1886 depends on EXPERIMENTAL
1888 Generate crash dump after being started by kexec. This should
1889 be normally only set in special crash dump kernels which are
1890 loaded in the main kernel with kexec-tools into a specially
1891 reserved region and then later executed after a crash by
1892 kdump/kexec. The crash dump kernel must be compiled to a
1893 memory address not used by the main kernel
1895 For more details see Documentation/kdump/kdump.txt
1897 config AUTO_ZRELADDR
1898 bool "Auto calculation of the decompressed kernel image address"
1899 depends on !ZBOOT_ROM && !ARCH_U300
1901 ZRELADDR is the physical address where the decompressed kernel
1902 image will be placed. If AUTO_ZRELADDR is selected, the address
1903 will be determined at run-time by masking the current IP with
1904 0xf8000000. This assumes the zImage being placed in the first 128MB
1905 from start of memory.
1909 menu "CPU Power Management"
1913 source "drivers/cpufreq/Kconfig"
1916 tristate "CPUfreq driver for i.MX CPUs"
1917 depends on ARCH_MXC && CPU_FREQ
1919 This enables the CPUfreq driver for i.MX CPUs.
1921 config CPU_FREQ_SA1100
1924 config CPU_FREQ_SA1110
1927 config CPU_FREQ_INTEGRATOR
1928 tristate "CPUfreq driver for ARM Integrator CPUs"
1929 depends on ARCH_INTEGRATOR && CPU_FREQ
1932 This enables the CPUfreq driver for ARM Integrator CPUs.
1934 For details, take a look at <file:Documentation/cpu-freq>.
1940 depends on CPU_FREQ && ARCH_PXA && PXA25x
1942 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1944 config CPU_FREQ_S3C64XX
1945 bool "CPUfreq support for Samsung S3C64XX CPUs"
1946 depends on CPU_FREQ && CPU_S3C6410
1951 Internal configuration node for common cpufreq on Samsung SoC
1953 config CPU_FREQ_S3C24XX
1954 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1955 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1958 This enables the CPUfreq driver for the Samsung S3C24XX family
1961 For details, take a look at <file:Documentation/cpu-freq>.
1965 config CPU_FREQ_S3C24XX_PLL
1966 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1967 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1969 Compile in support for changing the PLL frequency from the
1970 S3C24XX series CPUfreq driver. The PLL takes time to settle
1971 after a frequency change, so by default it is not enabled.
1973 This also means that the PLL tables for the selected CPU(s) will
1974 be built which may increase the size of the kernel image.
1976 config CPU_FREQ_S3C24XX_DEBUG
1977 bool "Debug CPUfreq Samsung driver core"
1978 depends on CPU_FREQ_S3C24XX
1980 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1982 config CPU_FREQ_S3C24XX_IODEBUG
1983 bool "Debug CPUfreq Samsung driver IO timing"
1984 depends on CPU_FREQ_S3C24XX
1986 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1988 config CPU_FREQ_S3C24XX_DEBUGFS
1989 bool "Export debugfs for CPUFreq"
1990 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1992 Export status information via debugfs.
1996 source "drivers/cpuidle/Kconfig"
2000 menu "Floating point emulation"
2002 comment "At least one emulation must be selected"
2005 bool "NWFPE math emulation"
2006 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2008 Say Y to include the NWFPE floating point emulator in the kernel.
2009 This is necessary to run most binaries. Linux does not currently
2010 support floating point hardware so you need to say Y here even if
2011 your machine has an FPA or floating point co-processor podule.
2013 You may say N here if you are going to load the Acorn FPEmulator
2014 early in the bootup.
2017 bool "Support extended precision"
2018 depends on FPE_NWFPE
2020 Say Y to include 80-bit support in the kernel floating-point
2021 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2022 Note that gcc does not generate 80-bit operations by default,
2023 so in most cases this option only enlarges the size of the
2024 floating point emulator without any good reason.
2026 You almost surely want to say N here.
2029 bool "FastFPE math emulation (EXPERIMENTAL)"
2030 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2032 Say Y here to include the FAST floating point emulator in the kernel.
2033 This is an experimental much faster emulator which now also has full
2034 precision for the mantissa. It does not support any exceptions.
2035 It is very simple, and approximately 3-6 times faster than NWFPE.
2037 It should be sufficient for most programs. It may be not suitable
2038 for scientific calculations, but you have to check this for yourself.
2039 If you do not feel you need a faster FP emulation you should better
2043 bool "VFP-format floating point maths"
2044 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2046 Say Y to include VFP support code in the kernel. This is needed
2047 if your hardware includes a VFP unit.
2049 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2050 release notes and additional status information.
2052 Say N if your target does not have VFP hardware.
2060 bool "Advanced SIMD (NEON) Extension support"
2061 depends on VFPv3 && CPU_V7
2063 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2068 menu "Userspace binary formats"
2070 source "fs/Kconfig.binfmt"
2073 tristate "RISC OS personality"
2076 Say Y here to include the kernel code necessary if you want to run
2077 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2078 experimental; if this sounds frightening, say N and sleep in peace.
2079 You can also say M here to compile this support as a module (which
2080 will be called arthur).
2084 menu "Power management options"
2086 source "kernel/power/Kconfig"
2088 config ARCH_SUSPEND_POSSIBLE
2089 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2090 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2091 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2096 source "net/Kconfig"
2098 source "drivers/Kconfig"
2102 source "arch/arm/Kconfig.debug"
2104 source "security/Kconfig"
2106 source "crypto/Kconfig"
2108 source "lib/Kconfig"