4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_CMPXCHG_LOCKREF
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CLONE_BACKWARDS
13 select CPU_PM if (SUSPEND || CPU_IDLE)
14 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
15 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
16 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
17 select GENERIC_IDLE_POLL_SETUP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_SCHED_CLOCK
22 select GENERIC_SMP_IDLE_THREAD
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select HARDIRQS_SW_RESEND
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
28 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_TRACEHOOK
31 select HAVE_CONTEXT_TRACKING
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_DMA_API_DEBUG
36 select HAVE_DMA_CONTIGUOUS if MMU
37 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
38 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
39 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
40 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
41 select HAVE_GENERIC_DMA_COHERENT
42 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
43 select HAVE_IDE if PCI || ISA || PCMCIA
44 select HAVE_IRQ_TIME_ACCOUNTING
45 select HAVE_KERNEL_GZIP
46 select HAVE_KERNEL_LZ4
47 select HAVE_KERNEL_LZMA
48 select HAVE_KERNEL_LZO
50 select HAVE_KPROBES if !XIP_KERNEL
51 select HAVE_KRETPROBES if (HAVE_KPROBES)
53 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
54 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
55 select HAVE_PERF_EVENTS
57 select HAVE_PERF_USER_STACK_DUMP
58 select HAVE_REGS_AND_STACK_ACCESS_API
59 select HAVE_SYSCALL_TRACEPOINTS
61 select HAVE_VIRT_CPU_ACCOUNTING_GEN
62 select IRQ_FORCED_THREADING
64 select MODULES_USE_ELF_REL
66 select OLD_SIGSUSPEND3
67 select PERF_USE_VMALLOC
69 select SYS_SUPPORTS_APM_EMULATION
70 # Above selects are sorted alphabetically; please add new ones
71 # according to that. Thanks.
73 The ARM series is a line of low-power-consumption RISC chip designs
74 licensed by ARM Ltd and targeted at embedded applications and
75 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
76 manufactured, but legacy ARM-based PC hardware remains popular in
77 Europe. There is an ARM Linux project with a web page at
78 <http://www.arm.linux.org.uk/>.
80 config ARM_HAS_SG_CHAIN
83 config NEED_SG_DMA_LENGTH
86 config ARM_DMA_USE_IOMMU
88 select ARM_HAS_SG_CHAIN
89 select NEED_SG_DMA_LENGTH
93 config ARM_DMA_IOMMU_ALIGNMENT
94 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
98 DMA mapping framework by default aligns all buffers to the smallest
99 PAGE_SIZE order which is greater than or equal to the requested buffer
100 size. This works well for buffers up to a few hundreds kilobytes, but
101 for larger buffers it just a waste of address space. Drivers which has
102 relatively small addressing window (like 64Mib) might run out of
103 virtual space with just a few allocations.
105 With this parameter you can specify the maximum PAGE_SIZE order for
106 DMA IOMMU buffers. Larger buffers will be aligned only to this
107 specified order. The order is expressed as a power of two multiplied
115 config MIGHT_HAVE_PCI
118 config SYS_SUPPORTS_APM_EMULATION
123 select GENERIC_ALLOCATOR
134 The Extended Industry Standard Architecture (EISA) bus was
135 developed as an open alternative to the IBM MicroChannel bus.
137 The EISA bus provided some of the features of the IBM MicroChannel
138 bus while maintaining backward compatibility with cards made for
139 the older ISA bus. The EISA bus saw limited use between 1988 and
140 1995 when it was made obsolete by the PCI bus.
142 Say Y here if you are building a kernel for an EISA-based machine.
149 config STACKTRACE_SUPPORT
153 config HAVE_LATENCYTOP_SUPPORT
158 config LOCKDEP_SUPPORT
162 config TRACE_IRQFLAGS_SUPPORT
166 config RWSEM_GENERIC_SPINLOCK
170 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_CPUFREQ
182 Internal node to signify that the ARCH has CPUFREQ support
183 and that the relevant menu configurations are displayed for
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_HAS_DMA_SET_COHERENT_MASK
209 config GENERIC_ISA_DMA
215 config NEED_RET_TO_USER
223 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
224 default DRAM_BASE if REMAP_VECTORS_TO_RAM
227 The base address of exception vectors. This must be two pages
230 config ARM_PATCH_PHYS_VIRT
231 bool "Patch physical to virtual translations at runtime" if EMBEDDED
233 depends on !XIP_KERNEL && MMU
234 depends on !ARCH_REALVIEW || !SPARSEMEM
236 Patch phys-to-virt and virt-to-phys translation functions at
237 boot and module load time according to the position of the
238 kernel in system memory.
240 This can only be used with non-XIP MMU kernels where the base
241 of physical memory is at a 16MB boundary.
243 Only disable this option if you know that you do not require
244 this feature (eg, building a kernel for a single machine) and
245 you need to shrink the kernel to the minimal size.
247 config NEED_MACH_GPIO_H
250 Select this when mach/gpio.h is required to provide special
251 definitions for this platform. The need for mach/gpio.h should
252 be avoided when possible.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
271 default DRAM_BASE if !MMU
273 Please provide the physical address corresponding to the
274 location of main memory in your system.
280 source "init/Kconfig"
282 source "kernel/Kconfig.freezer"
287 bool "MMU-based Paged Memory Management Support"
290 Select if you want MMU-based virtualised addressing space
291 support by paged memory management. If unsure, say 'Y'.
294 # The "ARM system type" choice list is ordered alphabetically by option
295 # text. Please add new entries in the option alphabetic order.
298 prompt "ARM system type"
299 default ARCH_VERSATILE if !MMU
300 default ARCH_MULTIPLATFORM if MMU
302 config ARCH_MULTIPLATFORM
303 bool "Allow multiple platforms to be selected"
305 select ARM_PATCH_PHYS_VIRT
308 select MULTI_IRQ_HANDLER
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
314 select ARCH_HAS_CPUFREQ
317 select COMMON_CLK_VERSATILE
318 select GENERIC_CLOCKEVENTS
321 select MULTI_IRQ_HANDLER
322 select NEED_MACH_MEMORY_H
323 select PLAT_VERSATILE
326 select VERSATILE_FPGA_IRQ
328 Support for ARM's Integrator platform.
331 bool "ARM Ltd. RealView family"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_TIMER_SP804
336 select COMMON_CLK_VERSATILE
337 select GENERIC_CLOCKEVENTS
338 select GPIO_PL061 if GPIOLIB
340 select NEED_MACH_MEMORY_H
341 select PLAT_VERSATILE
342 select PLAT_VERSATILE_CLCD
344 This enables support for ARM Ltd RealView boards.
346 config ARCH_VERSATILE
347 bool "ARM Ltd. Versatile family"
348 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
354 select HAVE_MACH_CLKDEV
356 select PLAT_VERSATILE
357 select PLAT_VERSATILE_CLCD
358 select PLAT_VERSATILE_CLOCK
359 select VERSATILE_FPGA_IRQ
361 This enables support for ARM Ltd Versatile board.
365 select ARCH_REQUIRE_GPIOLIB
368 select NEED_MACH_GPIO_H
369 select NEED_MACH_IO_H if PCCARD
371 select PINCTRL_AT91 if USE_OF
373 This enables support for systems based on Atmel
374 AT91RM9200 and AT91SAM9* processors.
377 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
378 select ARCH_REQUIRE_GPIOLIB
383 select GENERIC_CLOCKEVENTS
385 select MULTI_IRQ_HANDLER
388 Support for Cirrus Logic 711x/721x/731x based boards.
391 bool "Cortina Systems Gemini"
392 select ARCH_REQUIRE_GPIOLIB
395 select GENERIC_CLOCKEVENTS
397 Support for the Cortina Systems Gemini family SoCs
401 select ARCH_USES_GETTIMEOFFSET
404 select NEED_MACH_IO_H
405 select NEED_MACH_MEMORY_H
408 This is an evaluation board for the StrongARM processor available
409 from Digital. It has limited hardware on-board, including an
410 Ethernet interface, two PCMCIA sockets, two serial ports and a
414 bool "Energy Micro efm32"
416 select ARCH_REQUIRE_GPIOLIB
418 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
419 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
424 select GENERIC_CLOCKEVENTS
430 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
435 select ARCH_HAS_HOLES_MEMORYMODEL
436 select ARCH_REQUIRE_GPIOLIB
437 select ARCH_USES_GETTIMEOFFSET
442 select NEED_MACH_MEMORY_H
444 This enables support for the Cirrus EP93xx series of CPUs.
446 config ARCH_FOOTBRIDGE
450 select GENERIC_CLOCKEVENTS
452 select NEED_MACH_IO_H if !MMU
453 select NEED_MACH_MEMORY_H
455 Support for systems based on the DC21285 companion chip
456 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
459 bool "Hilscher NetX based"
463 select GENERIC_CLOCKEVENTS
465 This enables support for systems based on the Hilscher NetX Soc
471 select NEED_MACH_MEMORY_H
472 select NEED_RET_TO_USER
477 Support for Intel's IOP13XX (XScale) family of processors.
482 select ARCH_REQUIRE_GPIOLIB
485 select NEED_RET_TO_USER
489 Support for Intel's 80219 and IOP32X (XScale) family of
495 select ARCH_REQUIRE_GPIOLIB
498 select NEED_RET_TO_USER
502 Support for Intel's IOP33X (XScale) family of processors.
507 select ARCH_HAS_DMA_SET_COHERENT_MASK
508 select ARCH_SUPPORTS_BIG_ENDIAN
509 select ARCH_REQUIRE_GPIOLIB
512 select DMABOUNCE if PCI
513 select GENERIC_CLOCKEVENTS
514 select MIGHT_HAVE_PCI
515 select NEED_MACH_IO_H
516 select USB_EHCI_BIG_ENDIAN_DESC
517 select USB_EHCI_BIG_ENDIAN_MMIO
519 Support for Intel's IXP4XX (XScale) family of processors.
523 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
526 select MIGHT_HAVE_PCI
530 select PLAT_ORION_LEGACY
531 select USB_ARCH_HAS_EHCI
533 Support for the Marvell Dove SoC 88AP510
536 bool "Marvell Kirkwood"
537 select ARCH_HAS_CPUFREQ
538 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
545 select PINCTRL_KIRKWOOD
546 select PLAT_ORION_LEGACY
548 Support for the following Marvell Kirkwood series SoCs:
549 88F6180, 88F6192 and 88F6281.
552 bool "Marvell MV78xx0"
553 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_CLOCKEVENTS
558 select PLAT_ORION_LEGACY
560 Support for the following Marvell MV78xx0 series SoCs:
566 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
571 select PLAT_ORION_LEGACY
573 Support for the following Marvell Orion 5x series SoCs:
574 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
575 Orion-2 (5281), Orion-1-90 (6183).
578 bool "Marvell PXA168/910/MMP2"
580 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_ALLOCATOR
583 select GENERIC_CLOCKEVENTS
586 select MULTI_IRQ_HANDLER
591 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
594 bool "Micrel/Kendin KS8695"
595 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
599 select NEED_MACH_MEMORY_H
601 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
602 System-on-Chip devices.
605 bool "Nuvoton W90X900 CPU"
606 select ARCH_REQUIRE_GPIOLIB
610 select GENERIC_CLOCKEVENTS
612 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
613 At present, the w90x900 has been renamed nuc900, regarding
614 the ARM series product line, you can login the following
615 link address to know more.
617 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
618 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
622 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
630 select USB_ARCH_HAS_OHCI
633 Support for the NXP LPC32XX family of processors
636 bool "PXA2xx/PXA3xx-based"
638 select ARCH_HAS_CPUFREQ
640 select ARCH_REQUIRE_GPIOLIB
641 select ARM_CPU_SUSPEND if PM
645 select GENERIC_CLOCKEVENTS
648 select MULTI_IRQ_HANDLER
652 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
656 select ARCH_REQUIRE_GPIOLIB
657 select CLKSRC_OF if OF
659 select GENERIC_CLOCKEVENTS
661 Support for Qualcomm MSM/QSD based systems. This runs on the
662 apps processor of the MSM/QSD and depends on a shared memory
663 interface to the modem processor which runs the baseband
664 stack and controls some vital subsystems
665 (clock and power control, etc).
668 bool "Renesas SH-Mobile / R-Mobile"
669 select ARM_PATCH_PHYS_VIRT
671 select GENERIC_CLOCKEVENTS
672 select HAVE_ARM_SCU if SMP
673 select HAVE_ARM_TWD if SMP
674 select HAVE_MACH_CLKDEV
676 select MIGHT_HAVE_CACHE_L2X0
677 select MULTI_IRQ_HANDLER
680 select PM_GENERIC_DOMAINS if PM
683 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
688 select ARCH_MAY_HAVE_PC_FDC
689 select ARCH_SPARSEMEM_ENABLE
690 select ARCH_USES_GETTIMEOFFSET
693 select HAVE_PATA_PLATFORM
695 select NEED_MACH_IO_H
696 select NEED_MACH_MEMORY_H
700 On the Acorn Risc-PC, Linux can support the internal IDE disk and
701 CD-ROM interface, serial and parallel port, and the floppy drive.
705 select ARCH_HAS_CPUFREQ
707 select ARCH_REQUIRE_GPIOLIB
708 select ARCH_SPARSEMEM_ENABLE
713 select GENERIC_CLOCKEVENTS
716 select NEED_MACH_MEMORY_H
719 Support for StrongARM 11x0 based boards.
722 bool "Samsung S3C24XX SoCs"
723 select ARCH_HAS_CPUFREQ
724 select ARCH_REQUIRE_GPIOLIB
726 select CLKSRC_SAMSUNG_PWM
727 select GENERIC_CLOCKEVENTS
729 select HAVE_S3C2410_I2C if I2C
730 select HAVE_S3C2410_WATCHDOG if WATCHDOG
731 select HAVE_S3C_RTC if RTC_CLASS
732 select MULTI_IRQ_HANDLER
733 select NEED_MACH_GPIO_H
734 select NEED_MACH_IO_H
737 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
738 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
739 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
740 Samsung SMDK2410 development board (and derivatives).
743 bool "Samsung S3C64XX"
744 select ARCH_HAS_CPUFREQ
745 select ARCH_REQUIRE_GPIOLIB
748 select CLKSRC_SAMSUNG_PWM
751 select GENERIC_CLOCKEVENTS
753 select HAVE_S3C2410_I2C if I2C
754 select HAVE_S3C2410_WATCHDOG if WATCHDOG
756 select NEED_MACH_GPIO_H
759 select PM_GENERIC_DOMAINS
761 select S3C_GPIO_TRACK
763 select SAMSUNG_GPIOLIB_4BIT
764 select SAMSUNG_WAKEMASK
765 select SAMSUNG_WDT_RESET
766 select USB_ARCH_HAS_OHCI
768 Samsung S3C64XX series based systems
771 bool "Samsung S5P6440 S5P6450"
773 select CLKSRC_SAMSUNG_PWM
775 select GENERIC_CLOCKEVENTS
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select HAVE_S3C_RTC if RTC_CLASS
780 select NEED_MACH_GPIO_H
782 select SAMSUNG_WDT_RESET
784 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
788 bool "Samsung S5PC100"
789 select ARCH_REQUIRE_GPIOLIB
791 select CLKSRC_SAMSUNG_PWM
793 select GENERIC_CLOCKEVENTS
795 select HAVE_S3C2410_I2C if I2C
796 select HAVE_S3C2410_WATCHDOG if WATCHDOG
797 select HAVE_S3C_RTC if RTC_CLASS
798 select NEED_MACH_GPIO_H
800 select SAMSUNG_WDT_RESET
802 Samsung S5PC100 series based systems
805 bool "Samsung S5PV210/S5PC110"
806 select ARCH_HAS_CPUFREQ
807 select ARCH_HAS_HOLES_MEMORYMODEL
808 select ARCH_SPARSEMEM_ENABLE
810 select CLKSRC_SAMSUNG_PWM
812 select GENERIC_CLOCKEVENTS
814 select HAVE_S3C2410_I2C if I2C
815 select HAVE_S3C2410_WATCHDOG if WATCHDOG
816 select HAVE_S3C_RTC if RTC_CLASS
817 select NEED_MACH_GPIO_H
818 select NEED_MACH_MEMORY_H
821 Samsung S5PV210/S5PC110 series based systems
824 bool "Samsung EXYNOS"
825 select ARCH_HAS_CPUFREQ
826 select ARCH_HAS_HOLES_MEMORYMODEL
827 select ARCH_REQUIRE_GPIOLIB
828 select ARCH_SPARSEMEM_ENABLE
832 select GENERIC_CLOCKEVENTS
833 select HAVE_S3C2410_I2C if I2C
834 select HAVE_S3C2410_WATCHDOG if WATCHDOG
835 select HAVE_S3C_RTC if RTC_CLASS
836 select NEED_MACH_MEMORY_H
840 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
844 select ARCH_HAS_HOLES_MEMORYMODEL
845 select ARCH_REQUIRE_GPIOLIB
847 select GENERIC_ALLOCATOR
848 select GENERIC_CLOCKEVENTS
849 select GENERIC_IRQ_CHIP
855 Support for TI's DaVinci platform.
860 select ARCH_HAS_CPUFREQ
861 select ARCH_HAS_HOLES_MEMORYMODEL
863 select ARCH_REQUIRE_GPIOLIB
866 select GENERIC_CLOCKEVENTS
867 select GENERIC_IRQ_CHIP
870 select NEED_MACH_IO_H if PCCARD
871 select NEED_MACH_MEMORY_H
873 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
877 menu "Multiple platform selection"
878 depends on ARCH_MULTIPLATFORM
880 comment "CPU Core family selection"
882 config ARCH_MULTI_V4T
883 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
884 depends on !ARCH_MULTI_V6_V7
885 select ARCH_MULTI_V4_V5
886 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
887 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
888 CPU_ARM925T || CPU_ARM940T)
891 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
892 depends on !ARCH_MULTI_V6_V7
893 select ARCH_MULTI_V4_V5
894 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
895 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
896 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
898 config ARCH_MULTI_V4_V5
902 bool "ARMv6 based platforms (ARM11)"
903 select ARCH_MULTI_V6_V7
907 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
909 select ARCH_MULTI_V6_V7
912 config ARCH_MULTI_V6_V7
915 config ARCH_MULTI_CPU_AUTO
916 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
922 # This is sorted alphabetically by mach-* pathname. However, plat-*
923 # Kconfigs may be included either alphabetically (according to the
924 # plat- suffix) or along side the corresponding mach-* source.
926 source "arch/arm/mach-mvebu/Kconfig"
928 source "arch/arm/mach-at91/Kconfig"
930 source "arch/arm/mach-bcm/Kconfig"
932 source "arch/arm/mach-bcm2835/Kconfig"
934 source "arch/arm/mach-clps711x/Kconfig"
936 source "arch/arm/mach-cns3xxx/Kconfig"
938 source "arch/arm/mach-davinci/Kconfig"
940 source "arch/arm/mach-dove/Kconfig"
942 source "arch/arm/mach-ep93xx/Kconfig"
944 source "arch/arm/mach-footbridge/Kconfig"
946 source "arch/arm/mach-gemini/Kconfig"
948 source "arch/arm/mach-highbank/Kconfig"
950 source "arch/arm/mach-integrator/Kconfig"
952 source "arch/arm/mach-iop32x/Kconfig"
954 source "arch/arm/mach-iop33x/Kconfig"
956 source "arch/arm/mach-iop13xx/Kconfig"
958 source "arch/arm/mach-ixp4xx/Kconfig"
960 source "arch/arm/mach-keystone/Kconfig"
962 source "arch/arm/mach-kirkwood/Kconfig"
964 source "arch/arm/mach-ks8695/Kconfig"
966 source "arch/arm/mach-msm/Kconfig"
968 source "arch/arm/mach-mv78xx0/Kconfig"
970 source "arch/arm/mach-imx/Kconfig"
972 source "arch/arm/mach-mxs/Kconfig"
974 source "arch/arm/mach-netx/Kconfig"
976 source "arch/arm/mach-nomadik/Kconfig"
978 source "arch/arm/mach-nspire/Kconfig"
980 source "arch/arm/plat-omap/Kconfig"
982 source "arch/arm/mach-omap1/Kconfig"
984 source "arch/arm/mach-omap2/Kconfig"
986 source "arch/arm/mach-orion5x/Kconfig"
988 source "arch/arm/mach-picoxcell/Kconfig"
990 source "arch/arm/mach-pxa/Kconfig"
991 source "arch/arm/plat-pxa/Kconfig"
993 source "arch/arm/mach-mmp/Kconfig"
995 source "arch/arm/mach-realview/Kconfig"
997 source "arch/arm/mach-rockchip/Kconfig"
999 source "arch/arm/mach-sa1100/Kconfig"
1001 source "arch/arm/plat-samsung/Kconfig"
1003 source "arch/arm/mach-socfpga/Kconfig"
1005 source "arch/arm/mach-spear/Kconfig"
1007 source "arch/arm/mach-sti/Kconfig"
1009 source "arch/arm/mach-s3c24xx/Kconfig"
1011 source "arch/arm/mach-s3c64xx/Kconfig"
1013 source "arch/arm/mach-s5p64x0/Kconfig"
1015 source "arch/arm/mach-s5pc100/Kconfig"
1017 source "arch/arm/mach-s5pv210/Kconfig"
1019 source "arch/arm/mach-exynos/Kconfig"
1021 source "arch/arm/mach-shmobile/Kconfig"
1023 source "arch/arm/mach-sunxi/Kconfig"
1025 source "arch/arm/mach-prima2/Kconfig"
1027 source "arch/arm/mach-tegra/Kconfig"
1029 source "arch/arm/mach-u300/Kconfig"
1031 source "arch/arm/mach-ux500/Kconfig"
1033 source "arch/arm/mach-versatile/Kconfig"
1035 source "arch/arm/mach-vexpress/Kconfig"
1036 source "arch/arm/plat-versatile/Kconfig"
1038 source "arch/arm/mach-virt/Kconfig"
1040 source "arch/arm/mach-vt8500/Kconfig"
1042 source "arch/arm/mach-w90x900/Kconfig"
1044 source "arch/arm/mach-zynq/Kconfig"
1046 # Definitions to make life easier
1052 select GENERIC_CLOCKEVENTS
1058 select GENERIC_IRQ_CHIP
1061 config PLAT_ORION_LEGACY
1068 config PLAT_VERSATILE
1071 config ARM_TIMER_SP804
1074 select CLKSRC_OF if OF
1076 source arch/arm/mm/Kconfig
1080 default 16 if ARCH_EP93XX
1084 bool "Enable iWMMXt support" if !CPU_PJ4
1085 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1086 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1088 Enable support for iWMMXt context switching at run time if
1089 running on a CPU that supports it.
1091 config MULTI_IRQ_HANDLER
1094 Allow each machine to specify it's own IRQ handler at run time.
1097 source "arch/arm/Kconfig-nommu"
1100 config PJ4B_ERRATA_4742
1101 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1102 depends on CPU_PJ4B && MACH_ARMADA_370
1105 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1106 Event (WFE) IDLE states, a specific timing sensitivity exists between
1107 the retiring WFI/WFE instructions and the newly issued subsequent
1108 instructions. This sensitivity can result in a CPU hang scenario.
1110 The software must insert either a Data Synchronization Barrier (DSB)
1111 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1114 config ARM_ERRATA_326103
1115 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1118 Executing a SWP instruction to read-only memory does not set bit 11
1119 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1120 treat the access as a read, preventing a COW from occurring and
1121 causing the faulting task to livelock.
1123 config ARM_ERRATA_411920
1124 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1125 depends on CPU_V6 || CPU_V6K
1127 Invalidation of the Instruction Cache operation can
1128 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1129 It does not affect the MPCore. This option enables the ARM Ltd.
1130 recommended workaround.
1132 config ARM_ERRATA_430973
1133 bool "ARM errata: Stale prediction on replaced interworking branch"
1136 This option enables the workaround for the 430973 Cortex-A8
1137 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1138 interworking branch is replaced with another code sequence at the
1139 same virtual address, whether due to self-modifying code or virtual
1140 to physical address re-mapping, Cortex-A8 does not recover from the
1141 stale interworking branch prediction. This results in Cortex-A8
1142 executing the new code sequence in the incorrect ARM or Thumb state.
1143 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1144 and also flushes the branch target cache at every context switch.
1145 Note that setting specific bits in the ACTLR register may not be
1146 available in non-secure mode.
1148 config ARM_ERRATA_458693
1149 bool "ARM errata: Processor deadlock when a false hazard is created"
1151 depends on !ARCH_MULTIPLATFORM
1153 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1154 erratum. For very specific sequences of memory operations, it is
1155 possible for a hazard condition intended for a cache line to instead
1156 be incorrectly associated with a different cache line. This false
1157 hazard might then cause a processor deadlock. The workaround enables
1158 the L1 caching of the NEON accesses and disables the PLD instruction
1159 in the ACTLR register. Note that setting specific bits in the ACTLR
1160 register may not be available in non-secure mode.
1162 config ARM_ERRATA_460075
1163 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1165 depends on !ARCH_MULTIPLATFORM
1167 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1168 erratum. Any asynchronous access to the L2 cache may encounter a
1169 situation in which recent store transactions to the L2 cache are lost
1170 and overwritten with stale memory contents from external memory. The
1171 workaround disables the write-allocate mode for the L2 cache via the
1172 ACTLR register. Note that setting specific bits in the ACTLR register
1173 may not be available in non-secure mode.
1175 config ARM_ERRATA_742230
1176 bool "ARM errata: DMB operation may be faulty"
1177 depends on CPU_V7 && SMP
1178 depends on !ARCH_MULTIPLATFORM
1180 This option enables the workaround for the 742230 Cortex-A9
1181 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1182 between two write operations may not ensure the correct visibility
1183 ordering of the two writes. This workaround sets a specific bit in
1184 the diagnostic register of the Cortex-A9 which causes the DMB
1185 instruction to behave as a DSB, ensuring the correct behaviour of
1188 config ARM_ERRATA_742231
1189 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1190 depends on CPU_V7 && SMP
1191 depends on !ARCH_MULTIPLATFORM
1193 This option enables the workaround for the 742231 Cortex-A9
1194 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1195 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1196 accessing some data located in the same cache line, may get corrupted
1197 data due to bad handling of the address hazard when the line gets
1198 replaced from one of the CPUs at the same time as another CPU is
1199 accessing it. This workaround sets specific bits in the diagnostic
1200 register of the Cortex-A9 which reduces the linefill issuing
1201 capabilities of the processor.
1203 config PL310_ERRATA_588369
1204 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1205 depends on CACHE_L2X0
1207 The PL310 L2 cache controller implements three types of Clean &
1208 Invalidate maintenance operations: by Physical Address
1209 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1210 They are architecturally defined to behave as the execution of a
1211 clean operation followed immediately by an invalidate operation,
1212 both performing to the same memory location. This functionality
1213 is not correctly implemented in PL310 as clean lines are not
1214 invalidated as a result of these operations.
1216 config ARM_ERRATA_643719
1217 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1218 depends on CPU_V7 && SMP
1220 This option enables the workaround for the 643719 Cortex-A9 (prior to
1221 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1222 register returns zero when it should return one. The workaround
1223 corrects this value, ensuring cache maintenance operations which use
1224 it behave as intended and avoiding data corruption.
1226 config ARM_ERRATA_720789
1227 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1230 This option enables the workaround for the 720789 Cortex-A9 (prior to
1231 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1232 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1233 As a consequence of this erratum, some TLB entries which should be
1234 invalidated are not, resulting in an incoherency in the system page
1235 tables. The workaround changes the TLB flushing routines to invalidate
1236 entries regardless of the ASID.
1238 config PL310_ERRATA_727915
1239 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1240 depends on CACHE_L2X0
1242 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1243 operation (offset 0x7FC). This operation runs in background so that
1244 PL310 can handle normal accesses while it is in progress. Under very
1245 rare circumstances, due to this erratum, write data can be lost when
1246 PL310 treats a cacheable write transaction during a Clean &
1247 Invalidate by Way operation.
1249 config ARM_ERRATA_743622
1250 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1252 depends on !ARCH_MULTIPLATFORM
1254 This option enables the workaround for the 743622 Cortex-A9
1255 (r2p*) erratum. Under very rare conditions, a faulty
1256 optimisation in the Cortex-A9 Store Buffer may lead to data
1257 corruption. This workaround sets a specific bit in the diagnostic
1258 register of the Cortex-A9 which disables the Store Buffer
1259 optimisation, preventing the defect from occurring. This has no
1260 visible impact on the overall performance or power consumption of the
1263 config ARM_ERRATA_751472
1264 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1266 depends on !ARCH_MULTIPLATFORM
1268 This option enables the workaround for the 751472 Cortex-A9 (prior
1269 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1270 completion of a following broadcasted operation if the second
1271 operation is received by a CPU before the ICIALLUIS has completed,
1272 potentially leading to corrupted entries in the cache or TLB.
1274 config PL310_ERRATA_753970
1275 bool "PL310 errata: cache sync operation may be faulty"
1276 depends on CACHE_PL310
1278 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1280 Under some condition the effect of cache sync operation on
1281 the store buffer still remains when the operation completes.
1282 This means that the store buffer is always asked to drain and
1283 this prevents it from merging any further writes. The workaround
1284 is to replace the normal offset of cache sync operation (0x730)
1285 by another offset targeting an unmapped PL310 register 0x740.
1286 This has the same effect as the cache sync operation: store buffer
1287 drain and waiting for all buffers empty.
1289 config ARM_ERRATA_754322
1290 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1293 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1294 r3p*) erratum. A speculative memory access may cause a page table walk
1295 which starts prior to an ASID switch but completes afterwards. This
1296 can populate the micro-TLB with a stale entry which may be hit with
1297 the new ASID. This workaround places two dsb instructions in the mm
1298 switching code so that no page table walks can cross the ASID switch.
1300 config ARM_ERRATA_754327
1301 bool "ARM errata: no automatic Store Buffer drain"
1302 depends on CPU_V7 && SMP
1304 This option enables the workaround for the 754327 Cortex-A9 (prior to
1305 r2p0) erratum. The Store Buffer does not have any automatic draining
1306 mechanism and therefore a livelock may occur if an external agent
1307 continuously polls a memory location waiting to observe an update.
1308 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1309 written polling loops from denying visibility of updates to memory.
1311 config ARM_ERRATA_364296
1312 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1315 This options enables the workaround for the 364296 ARM1136
1316 r0p2 erratum (possible cache data corruption with
1317 hit-under-miss enabled). It sets the undocumented bit 31 in
1318 the auxiliary control register and the FI bit in the control
1319 register, thus disabling hit-under-miss without putting the
1320 processor into full low interrupt latency mode. ARM11MPCore
1323 config ARM_ERRATA_764369
1324 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1325 depends on CPU_V7 && SMP
1327 This option enables the workaround for erratum 764369
1328 affecting Cortex-A9 MPCore with two or more processors (all
1329 current revisions). Under certain timing circumstances, a data
1330 cache line maintenance operation by MVA targeting an Inner
1331 Shareable memory region may fail to proceed up to either the
1332 Point of Coherency or to the Point of Unification of the
1333 system. This workaround adds a DSB instruction before the
1334 relevant cache maintenance functions and sets a specific bit
1335 in the diagnostic control register of the SCU.
1337 config PL310_ERRATA_769419
1338 bool "PL310 errata: no automatic Store Buffer drain"
1339 depends on CACHE_L2X0
1341 On revisions of the PL310 prior to r3p2, the Store Buffer does
1342 not automatically drain. This can cause normal, non-cacheable
1343 writes to be retained when the memory system is idle, leading
1344 to suboptimal I/O performance for drivers using coherent DMA.
1345 This option adds a write barrier to the cpu_idle loop so that,
1346 on systems with an outer cache, the store buffer is drained
1349 config ARM_ERRATA_775420
1350 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1353 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1354 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1355 operation aborts with MMU exception, it might cause the processor
1356 to deadlock. This workaround puts DSB before executing ISB if
1357 an abort may occur on cache maintenance.
1359 config ARM_ERRATA_798181
1360 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1361 depends on CPU_V7 && SMP
1363 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1364 adequately shooting down all use of the old entries. This
1365 option enables the Linux kernel workaround for this erratum
1366 which sends an IPI to the CPUs that are running the same ASID
1367 as the one being invalidated.
1369 config ARM_ERRATA_773022
1370 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1373 This option enables the workaround for the 773022 Cortex-A15
1374 (up to r0p4) erratum. In certain rare sequences of code, the
1375 loop buffer may deliver incorrect instructions. This
1376 workaround disables the loop buffer to avoid the erratum.
1380 source "arch/arm/common/Kconfig"
1390 Find out whether you have ISA slots on your motherboard. ISA is the
1391 name of a bus system, i.e. the way the CPU talks to the other stuff
1392 inside your box. Other bus systems are PCI, EISA, MicroChannel
1393 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1394 newer boards don't support it. If you have ISA, say Y, otherwise N.
1396 # Select ISA DMA controller support
1401 # Select ISA DMA interface
1406 bool "PCI support" if MIGHT_HAVE_PCI
1408 Find out whether you have a PCI motherboard. PCI is the name of a
1409 bus system, i.e. the way the CPU talks to the other stuff inside
1410 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1411 VESA. If you have PCI, say Y, otherwise N.
1417 config PCI_NANOENGINE
1418 bool "BSE nanoEngine PCI support"
1419 depends on SA1100_NANOENGINE
1421 Enable PCI on the BSE nanoEngine board.
1426 config PCI_HOST_ITE8152
1428 depends on PCI && MACH_ARMCORE
1432 source "drivers/pci/Kconfig"
1433 source "drivers/pci/pcie/Kconfig"
1435 source "drivers/pcmcia/Kconfig"
1439 menu "Kernel Features"
1444 This option should be selected by machines which have an SMP-
1447 The only effect of this option is to make the SMP-related
1448 options available to the user for configuration.
1451 bool "Symmetric Multi-Processing"
1452 depends on CPU_V6K || CPU_V7
1453 depends on GENERIC_CLOCKEVENTS
1455 depends on MMU || ARM_MPU
1457 This enables support for systems with more than one CPU. If you have
1458 a system with only one CPU, like most personal computers, say N. If
1459 you have a system with more than one CPU, say Y.
1461 If you say N here, the kernel will run on single and multiprocessor
1462 machines, but will use only one CPU of a multiprocessor machine. If
1463 you say Y here, the kernel will run on many, but not all, single
1464 processor machines. On a single processor machine, the kernel will
1465 run faster if you say N here.
1467 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1468 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1469 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1471 If you don't know what to do here, say N.
1474 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1475 depends on SMP && !XIP_KERNEL && MMU
1478 SMP kernels contain instructions which fail on non-SMP processors.
1479 Enabling this option allows the kernel to modify itself to make
1480 these instructions safe. Disabling it allows about 1K of space
1483 If you don't know what to do here, say Y.
1485 config ARM_CPU_TOPOLOGY
1486 bool "Support cpu topology definition"
1487 depends on SMP && CPU_V7
1490 Support ARM cpu topology definition. The MPIDR register defines
1491 affinity between processors which is then used to describe the cpu
1492 topology of an ARM System.
1495 bool "Multi-core scheduler support"
1496 depends on ARM_CPU_TOPOLOGY
1498 Multi-core scheduler support improves the CPU scheduler's decision
1499 making when dealing with multi-core CPU chips at a cost of slightly
1500 increased overhead in some places. If unsure say N here.
1503 bool "SMT scheduler support"
1504 depends on ARM_CPU_TOPOLOGY
1506 Improves the CPU scheduler's decision making when dealing with
1507 MultiThreading at a cost of slightly increased overhead in some
1508 places. If unsure say N here.
1513 This option enables support for the ARM system coherency unit
1515 config HAVE_ARM_ARCH_TIMER
1516 bool "Architected timer support"
1518 select ARM_ARCH_TIMER
1519 select GENERIC_CLOCKEVENTS
1521 This option enables support for the ARM architected timer
1526 select CLKSRC_OF if OF
1528 This options enables support for the ARM timer and watchdog unit
1531 bool "Multi-Cluster Power Management"
1532 depends on CPU_V7 && SMP
1534 This option provides the common power management infrastructure
1535 for (multi-)cluster based systems, such as big.LITTLE based
1539 bool "big.LITTLE support (Experimental)"
1540 depends on CPU_V7 && SMP
1543 This option enables support selections for the big.LITTLE
1544 system architecture.
1547 bool "big.LITTLE switcher support"
1548 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1550 select ARM_CPU_SUSPEND
1552 The big.LITTLE "switcher" provides the core functionality to
1553 transparently handle transition between a cluster of A15's
1554 and a cluster of A7's in a big.LITTLE system.
1556 config BL_SWITCHER_DUMMY_IF
1557 tristate "Simple big.LITTLE switcher user interface"
1558 depends on BL_SWITCHER && DEBUG_KERNEL
1560 This is a simple and dummy char dev interface to control
1561 the big.LITTLE switcher core code. It is meant for
1562 debugging purposes only.
1565 prompt "Memory split"
1568 Select the desired split between kernel and user memory.
1570 If you are not absolutely sure what you are doing, leave this
1574 bool "3G/1G user/kernel split"
1576 bool "2G/2G user/kernel split"
1578 bool "1G/3G user/kernel split"
1583 default 0x40000000 if VMSPLIT_1G
1584 default 0x80000000 if VMSPLIT_2G
1588 int "Maximum number of CPUs (2-32)"
1594 bool "Support for hot-pluggable CPUs"
1597 Say Y here to experiment with turning CPUs off and on. CPUs
1598 can be controlled through /sys/devices/system/cpu.
1601 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1604 Say Y here if you want Linux to communicate with system firmware
1605 implementing the PSCI specification for CPU-centric power
1606 management operations described in ARM document number ARM DEN
1607 0022A ("Power State Coordination Interface System Software on
1610 # The GPIO number here must be sorted by descending number. In case of
1611 # a multiplatform kernel, we just want the highest value required by the
1612 # selected platforms.
1615 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1616 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1617 default 392 if ARCH_U8500
1618 default 352 if ARCH_VT8500
1619 default 288 if ARCH_SUNXI
1620 default 264 if MACH_H4700
1623 Maximum number of GPIOs in the system.
1625 If unsure, leave the default value.
1627 source kernel/Kconfig.preempt
1631 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1632 ARCH_S5PV210 || ARCH_EXYNOS4
1633 default AT91_TIMER_HZ if ARCH_AT91
1634 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1638 depends on HZ_FIXED = 0
1639 prompt "Timer frequency"
1663 default HZ_FIXED if HZ_FIXED != 0
1664 default 100 if HZ_100
1665 default 200 if HZ_200
1666 default 250 if HZ_250
1667 default 300 if HZ_300
1668 default 500 if HZ_500
1672 def_bool HIGH_RES_TIMERS
1675 def_bool HIGH_RES_TIMERS
1677 config THUMB2_KERNEL
1678 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1679 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1680 default y if CPU_THUMBONLY
1682 select ARM_ASM_UNIFIED
1685 By enabling this option, the kernel will be compiled in
1686 Thumb-2 mode. A compiler/assembler that understand the unified
1687 ARM-Thumb syntax is needed.
1691 config THUMB2_AVOID_R_ARM_THM_JUMP11
1692 bool "Work around buggy Thumb-2 short branch relocations in gas"
1693 depends on THUMB2_KERNEL && MODULES
1696 Various binutils versions can resolve Thumb-2 branches to
1697 locally-defined, preemptible global symbols as short-range "b.n"
1698 branch instructions.
1700 This is a problem, because there's no guarantee the final
1701 destination of the symbol, or any candidate locations for a
1702 trampoline, are within range of the branch. For this reason, the
1703 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1704 relocation in modules at all, and it makes little sense to add
1707 The symptom is that the kernel fails with an "unsupported
1708 relocation" error when loading some modules.
1710 Until fixed tools are available, passing
1711 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1712 code which hits this problem, at the cost of a bit of extra runtime
1713 stack usage in some cases.
1715 The problem is described in more detail at:
1716 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1718 Only Thumb-2 kernels are affected.
1720 Unless you are sure your tools don't have this problem, say Y.
1722 config ARM_ASM_UNIFIED
1726 bool "Use the ARM EABI to compile the kernel"
1728 This option allows for the kernel to be compiled using the latest
1729 ARM ABI (aka EABI). This is only useful if you are using a user
1730 space environment that is also compiled with EABI.
1732 Since there are major incompatibilities between the legacy ABI and
1733 EABI, especially with regard to structure member alignment, this
1734 option also changes the kernel syscall calling convention to
1735 disambiguate both ABIs and allow for backward compatibility support
1736 (selected with CONFIG_OABI_COMPAT).
1738 To use this you need GCC version 4.0.0 or later.
1741 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1742 depends on AEABI && !THUMB2_KERNEL
1744 This option preserves the old syscall interface along with the
1745 new (ARM EABI) one. It also provides a compatibility layer to
1746 intercept syscalls that have structure arguments which layout
1747 in memory differs between the legacy ABI and the new ARM EABI
1748 (only for non "thumb" binaries). This option adds a tiny
1749 overhead to all syscalls and produces a slightly larger kernel.
1751 The seccomp filter system will not be available when this is
1752 selected, since there is no way yet to sensibly distinguish
1753 between calling conventions during filtering.
1755 If you know you'll be using only pure EABI user space then you
1756 can say N here. If this option is not selected and you attempt
1757 to execute a legacy ABI binary then the result will be
1758 UNPREDICTABLE (in fact it can be predicted that it won't work
1759 at all). If in doubt say N.
1761 config ARCH_HAS_HOLES_MEMORYMODEL
1764 config ARCH_SPARSEMEM_ENABLE
1767 config ARCH_SPARSEMEM_DEFAULT
1768 def_bool ARCH_SPARSEMEM_ENABLE
1770 config ARCH_SELECT_MEMORY_MODEL
1771 def_bool ARCH_SPARSEMEM_ENABLE
1773 config HAVE_ARCH_PFN_VALID
1774 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1777 bool "High Memory Support"
1780 The address space of ARM processors is only 4 Gigabytes large
1781 and it has to accommodate user address space, kernel address
1782 space as well as some memory mapped IO. That means that, if you
1783 have a large amount of physical memory and/or IO, not all of the
1784 memory can be "permanently mapped" by the kernel. The physical
1785 memory that is not permanently mapped is called "high memory".
1787 Depending on the selected kernel/user memory split, minimum
1788 vmalloc space and actual amount of RAM, you may not need this
1789 option which should result in a slightly faster kernel.
1794 bool "Allocate 2nd-level pagetables from highmem"
1797 config HW_PERF_EVENTS
1798 bool "Enable hardware performance counter support for perf events"
1799 depends on PERF_EVENTS
1802 Enable hardware performance counter support for perf events. If
1803 disabled, perf events will use software events only.
1805 config SYS_SUPPORTS_HUGETLBFS
1809 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1813 config ARCH_WANT_GENERAL_HUGETLB
1818 config FORCE_MAX_ZONEORDER
1819 int "Maximum zone order" if ARCH_SHMOBILE
1820 range 11 64 if ARCH_SHMOBILE
1821 default "12" if SOC_AM33XX
1822 default "9" if SA1111 || ARCH_EFM32
1825 The kernel memory allocator divides physically contiguous memory
1826 blocks into "zones", where each zone is a power of two number of
1827 pages. This option selects the largest power of two that the kernel
1828 keeps in the memory allocator. If you need to allocate very large
1829 blocks of physically contiguous memory, then you may need to
1830 increase this value.
1832 This config option is actually maximum order plus one. For example,
1833 a value of 11 means that the largest free memory block is 2^10 pages.
1835 config ALIGNMENT_TRAP
1837 depends on CPU_CP15_MMU
1838 default y if !ARCH_EBSA110
1839 select HAVE_PROC_CPU if PROC_FS
1841 ARM processors cannot fetch/store information which is not
1842 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1843 address divisible by 4. On 32-bit ARM processors, these non-aligned
1844 fetch/store instructions will be emulated in software if you say
1845 here, which has a severe performance impact. This is necessary for
1846 correct operation of some network protocols. With an IP-only
1847 configuration it is safe to say N, otherwise say Y.
1849 config UACCESS_WITH_MEMCPY
1850 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1852 default y if CPU_FEROCEON
1854 Implement faster copy_to_user and clear_user methods for CPU
1855 cores where a 8-word STM instruction give significantly higher
1856 memory write throughput than a sequence of individual 32bit stores.
1858 A possible side effect is a slight increase in scheduling latency
1859 between threads sharing the same address space if they invoke
1860 such copy operations with large buffers.
1862 However, if the CPU data cache is using a write-allocate mode,
1863 this option is unlikely to provide any performance gain.
1867 prompt "Enable seccomp to safely compute untrusted bytecode"
1869 This kernel feature is useful for number crunching applications
1870 that may need to compute untrusted bytecode during their
1871 execution. By using pipes or other transports made available to
1872 the process as file descriptors supporting the read/write
1873 syscalls, it's possible to isolate those applications in
1874 their own address space using seccomp. Once seccomp is
1875 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1876 and the task is only allowed to execute a few safe syscalls
1877 defined by each seccomp mode.
1879 config CC_STACKPROTECTOR
1880 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1882 This option turns on the -fstack-protector GCC feature. This
1883 feature puts, at the beginning of functions, a canary value on
1884 the stack just before the return address, and validates
1885 the value just before actually returning. Stack based buffer
1886 overflows (that need to overwrite this return address) now also
1887 overwrite the canary, which gets detected and the attack is then
1888 neutralized via a kernel panic.
1889 This feature requires gcc version 4.2 or above.
1902 bool "Xen guest support on ARM (EXPERIMENTAL)"
1903 depends on ARM && AEABI && OF
1904 depends on CPU_V7 && !CPU_V6
1905 depends on !GENERIC_ATOMIC64
1909 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1916 bool "Flattened Device Tree support"
1919 select OF_EARLY_FLATTREE
1921 Include support for flattened device tree machine descriptions.
1924 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1927 This is the traditional way of passing data to the kernel at boot
1928 time. If you are solely relying on the flattened device tree (or
1929 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1930 to remove ATAGS support from your kernel binary. If unsure,
1933 config DEPRECATED_PARAM_STRUCT
1934 bool "Provide old way to pass kernel parameters"
1937 This was deprecated in 2001 and announced to live on for 5 years.
1938 Some old boot loaders still use this way.
1940 # Compressed boot loader in ROM. Yes, we really want to ask about
1941 # TEXT and BSS so we preserve their values in the config files.
1942 config ZBOOT_ROM_TEXT
1943 hex "Compressed ROM boot loader base address"
1946 The physical address at which the ROM-able zImage is to be
1947 placed in the target. Platforms which normally make use of
1948 ROM-able zImage formats normally set this to a suitable
1949 value in their defconfig file.
1951 If ZBOOT_ROM is not enabled, this has no effect.
1953 config ZBOOT_ROM_BSS
1954 hex "Compressed ROM boot loader BSS address"
1957 The base address of an area of read/write memory in the target
1958 for the ROM-able zImage which must be available while the
1959 decompressor is running. It must be large enough to hold the
1960 entire decompressed kernel plus an additional 128 KiB.
1961 Platforms which normally make use of ROM-able zImage formats
1962 normally set this to a suitable value in their defconfig file.
1964 If ZBOOT_ROM is not enabled, this has no effect.
1967 bool "Compressed boot loader in ROM/flash"
1968 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1970 Say Y here if you intend to execute your compressed kernel image
1971 (zImage) directly from ROM or flash. If unsure, say N.
1974 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1975 depends on ZBOOT_ROM && ARCH_SH7372
1976 default ZBOOT_ROM_NONE
1978 Include experimental SD/MMC loading code in the ROM-able zImage.
1979 With this enabled it is possible to write the ROM-able zImage
1980 kernel image to an MMC or SD card and boot the kernel straight
1981 from the reset vector. At reset the processor Mask ROM will load
1982 the first part of the ROM-able zImage which in turn loads the
1983 rest the kernel image to RAM.
1985 config ZBOOT_ROM_NONE
1986 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1988 Do not load image from SD or MMC
1990 config ZBOOT_ROM_MMCIF
1991 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1993 Load image from MMCIF hardware block.
1995 config ZBOOT_ROM_SH_MOBILE_SDHI
1996 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1998 Load image from SDHI hardware block
2002 config ARM_APPENDED_DTB
2003 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2004 depends on OF && !ZBOOT_ROM
2006 With this option, the boot code will look for a device tree binary
2007 (DTB) appended to zImage
2008 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2010 This is meant as a backward compatibility convenience for those
2011 systems with a bootloader that can't be upgraded to accommodate
2012 the documented boot protocol using a device tree.
2014 Beware that there is very little in terms of protection against
2015 this option being confused by leftover garbage in memory that might
2016 look like a DTB header after a reboot if no actual DTB is appended
2017 to zImage. Do not leave this option active in a production kernel
2018 if you don't intend to always append a DTB. Proper passing of the
2019 location into r2 of a bootloader provided DTB is always preferable
2022 config ARM_ATAG_DTB_COMPAT
2023 bool "Supplement the appended DTB with traditional ATAG information"
2024 depends on ARM_APPENDED_DTB
2026 Some old bootloaders can't be updated to a DTB capable one, yet
2027 they provide ATAGs with memory configuration, the ramdisk address,
2028 the kernel cmdline string, etc. Such information is dynamically
2029 provided by the bootloader and can't always be stored in a static
2030 DTB. To allow a device tree enabled kernel to be used with such
2031 bootloaders, this option allows zImage to extract the information
2032 from the ATAG list and store it at run time into the appended DTB.
2035 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2036 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2038 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2039 bool "Use bootloader kernel arguments if available"
2041 Uses the command-line options passed by the boot loader instead of
2042 the device tree bootargs property. If the boot loader doesn't provide
2043 any, the device tree bootargs property will be used.
2045 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2046 bool "Extend with bootloader kernel arguments"
2048 The command-line arguments provided by the boot loader will be
2049 appended to the the device tree bootargs property.
2054 string "Default kernel command string"
2057 On some architectures (EBSA110 and CATS), there is currently no way
2058 for the boot loader to pass arguments to the kernel. For these
2059 architectures, you should supply some command-line options at build
2060 time by entering them here. As a minimum, you should specify the
2061 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2064 prompt "Kernel command line type" if CMDLINE != ""
2065 default CMDLINE_FROM_BOOTLOADER
2068 config CMDLINE_FROM_BOOTLOADER
2069 bool "Use bootloader kernel arguments if available"
2071 Uses the command-line options passed by the boot loader. If
2072 the boot loader doesn't provide any, the default kernel command
2073 string provided in CMDLINE will be used.
2075 config CMDLINE_EXTEND
2076 bool "Extend bootloader kernel arguments"
2078 The command-line arguments provided by the boot loader will be
2079 appended to the default kernel command string.
2081 config CMDLINE_FORCE
2082 bool "Always use the default kernel command string"
2084 Always use the default kernel command string, even if the boot
2085 loader passes other arguments to the kernel.
2086 This is useful if you cannot or don't want to change the
2087 command-line options your boot loader passes to the kernel.
2091 bool "Kernel Execute-In-Place from ROM"
2092 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2094 Execute-In-Place allows the kernel to run from non-volatile storage
2095 directly addressable by the CPU, such as NOR flash. This saves RAM
2096 space since the text section of the kernel is not loaded from flash
2097 to RAM. Read-write sections, such as the data section and stack,
2098 are still copied to RAM. The XIP kernel is not compressed since
2099 it has to run directly from flash, so it will take more space to
2100 store it. The flash address used to link the kernel object files,
2101 and for storing it, is configuration dependent. Therefore, if you
2102 say Y here, you must know the proper physical address where to
2103 store the kernel image depending on your own flash memory usage.
2105 Also note that the make target becomes "make xipImage" rather than
2106 "make zImage" or "make Image". The final kernel binary to put in
2107 ROM memory will be arch/arm/boot/xipImage.
2111 config XIP_PHYS_ADDR
2112 hex "XIP Kernel Physical Location"
2113 depends on XIP_KERNEL
2114 default "0x00080000"
2116 This is the physical address in your flash memory the kernel will
2117 be linked for and stored to. This address is dependent on your
2121 bool "Kexec system call (EXPERIMENTAL)"
2122 depends on (!SMP || PM_SLEEP_SMP)
2124 kexec is a system call that implements the ability to shutdown your
2125 current kernel, and to start another kernel. It is like a reboot
2126 but it is independent of the system firmware. And like a reboot
2127 you can start any kernel with it, not just Linux.
2129 It is an ongoing process to be certain the hardware in a machine
2130 is properly shutdown, so do not be surprised if this code does not
2131 initially work for you.
2134 bool "Export atags in procfs"
2135 depends on ATAGS && KEXEC
2138 Should the atags used to boot the kernel be exported in an "atags"
2139 file in procfs. Useful with kexec.
2142 bool "Build kdump crash kernel (EXPERIMENTAL)"
2144 Generate crash dump after being started by kexec. This should
2145 be normally only set in special crash dump kernels which are
2146 loaded in the main kernel with kexec-tools into a specially
2147 reserved region and then later executed after a crash by
2148 kdump/kexec. The crash dump kernel must be compiled to a
2149 memory address not used by the main kernel
2151 For more details see Documentation/kdump/kdump.txt
2153 config AUTO_ZRELADDR
2154 bool "Auto calculation of the decompressed kernel image address"
2155 depends on !ZBOOT_ROM
2157 ZRELADDR is the physical address where the decompressed kernel
2158 image will be placed. If AUTO_ZRELADDR is selected, the address
2159 will be determined at run-time by masking the current IP with
2160 0xf8000000. This assumes the zImage being placed in the first 128MB
2161 from start of memory.
2165 menu "CPU Power Management"
2168 source "drivers/cpufreq/Kconfig"
2171 source "drivers/cpuidle/Kconfig"
2175 menu "Floating point emulation"
2177 comment "At least one emulation must be selected"
2180 bool "NWFPE math emulation"
2181 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2183 Say Y to include the NWFPE floating point emulator in the kernel.
2184 This is necessary to run most binaries. Linux does not currently
2185 support floating point hardware so you need to say Y here even if
2186 your machine has an FPA or floating point co-processor podule.
2188 You may say N here if you are going to load the Acorn FPEmulator
2189 early in the bootup.
2192 bool "Support extended precision"
2193 depends on FPE_NWFPE
2195 Say Y to include 80-bit support in the kernel floating-point
2196 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2197 Note that gcc does not generate 80-bit operations by default,
2198 so in most cases this option only enlarges the size of the
2199 floating point emulator without any good reason.
2201 You almost surely want to say N here.
2204 bool "FastFPE math emulation (EXPERIMENTAL)"
2205 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2207 Say Y here to include the FAST floating point emulator in the kernel.
2208 This is an experimental much faster emulator which now also has full
2209 precision for the mantissa. It does not support any exceptions.
2210 It is very simple, and approximately 3-6 times faster than NWFPE.
2212 It should be sufficient for most programs. It may be not suitable
2213 for scientific calculations, but you have to check this for yourself.
2214 If you do not feel you need a faster FP emulation you should better
2218 bool "VFP-format floating point maths"
2219 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2221 Say Y to include VFP support code in the kernel. This is needed
2222 if your hardware includes a VFP unit.
2224 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2225 release notes and additional status information.
2227 Say N if your target does not have VFP hardware.
2235 bool "Advanced SIMD (NEON) Extension support"
2236 depends on VFPv3 && CPU_V7
2238 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2241 config KERNEL_MODE_NEON
2242 bool "Support for NEON in kernel mode"
2243 depends on NEON && AEABI
2245 Say Y to include support for NEON in kernel mode.
2249 menu "Userspace binary formats"
2251 source "fs/Kconfig.binfmt"
2254 tristate "RISC OS personality"
2257 Say Y here to include the kernel code necessary if you want to run
2258 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2259 experimental; if this sounds frightening, say N and sleep in peace.
2260 You can also say M here to compile this support as a module (which
2261 will be called arthur).
2265 menu "Power management options"
2267 source "kernel/power/Kconfig"
2269 config ARCH_SUSPEND_POSSIBLE
2270 depends on !ARCH_S5PC100
2271 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2272 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2275 config ARM_CPU_SUSPEND
2280 source "net/Kconfig"
2282 source "drivers/Kconfig"
2286 source "arch/arm/Kconfig.debug"
2288 source "security/Kconfig"
2290 source "crypto/Kconfig"
2292 source "lib/Kconfig"
2294 source "arch/arm/kvm/Kconfig"