5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
47 config SYS_SUPPORTS_APM_EMULATION
50 config HAVE_SCHED_CLOCK
56 config ARCH_USES_GETTIMEOFFSET
60 config GENERIC_CLOCKEVENTS
63 config GENERIC_CLOCKEVENTS_BROADCAST
65 depends on GENERIC_CLOCKEVENTS
74 select GENERIC_ALLOCATOR
85 The Extended Industry Standard Architecture (EISA) bus was
86 developed as an open alternative to the IBM MicroChannel bus.
88 The EISA bus provided some of the features of the IBM MicroChannel
89 bus while maintaining backward compatibility with cards made for
90 the older ISA bus. The EISA bus saw limited use between 1988 and
91 1995 when it was made obsolete by the PCI bus.
93 Say Y here if you are building a kernel for an EISA-based machine.
103 MicroChannel Architecture is found in some IBM PS/2 machines and
104 laptops. It is a bus system similar to PCI or ISA. See
105 <file:Documentation/mca.txt> (and especially the web page given
106 there) before attempting to build an MCA bus kernel.
108 config STACKTRACE_SUPPORT
112 config HAVE_LATENCYTOP_SUPPORT
117 config LOCKDEP_SUPPORT
121 config TRACE_IRQFLAGS_SUPPORT
125 config HARDIRQS_SW_RESEND
129 config GENERIC_IRQ_PROBE
133 config GENERIC_LOCKBREAK
136 depends on SMP && PREEMPT
138 config RWSEM_GENERIC_SPINLOCK
142 config RWSEM_XCHGADD_ALGORITHM
145 config ARCH_HAS_ILOG2_U32
148 config ARCH_HAS_ILOG2_U64
151 config ARCH_HAS_CPUFREQ
154 Internal node to signify that the ARCH has CPUFREQ support
155 and that the relevant menu configurations are displayed for
158 config ARCH_HAS_CPU_IDLE_WAIT
161 config GENERIC_HWEIGHT
165 config GENERIC_CALIBRATE_DELAY
169 config ARCH_MAY_HAVE_PC_FDC
175 config NEED_DMA_MAP_STATE
178 config GENERIC_ISA_DMA
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
197 depends on EXPERIMENTAL
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary, or theoretically 64K
207 for the MSM machine class.
209 config ARM_PATCH_PHYS_VIRT_16BIT
211 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
213 This option extends the physical to virtual translation patching
214 to allow physical memory down to a theoretical minimum of 64K
217 source "init/Kconfig"
219 source "kernel/Kconfig.freezer"
224 bool "MMU-based Paged Memory Management Support"
227 Select if you want MMU-based virtualised addressing space
228 support by paged memory management. If unsure, say 'Y'.
231 # The "ARM system type" choice list is ordered alphabetically by option
232 # text. Please add new entries in the option alphabetic order.
235 prompt "ARM system type"
236 default ARCH_VERSATILE
238 config ARCH_INTEGRATOR
239 bool "ARM Ltd. Integrator family"
241 select ARCH_HAS_CPUFREQ
244 select GENERIC_CLOCKEVENTS
245 select PLAT_VERSATILE
246 select PLAT_VERSATILE_FPGA_IRQ
248 Support for ARM's Integrator platform.
251 bool "ARM Ltd. RealView family"
255 select GENERIC_CLOCKEVENTS
256 select ARCH_WANT_OPTIONAL_GPIOLIB
257 select PLAT_VERSATILE
258 select PLAT_VERSATILE_CLCD
259 select ARM_TIMER_SP804
260 select GPIO_PL061 if GPIOLIB
262 This enables support for ARM Ltd RealView boards.
264 config ARCH_VERSATILE
265 bool "ARM Ltd. Versatile family"
270 select GENERIC_CLOCKEVENTS
271 select ARCH_WANT_OPTIONAL_GPIOLIB
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_CLCD
274 select PLAT_VERSATILE_FPGA_IRQ
275 select ARM_TIMER_SP804
277 This enables support for ARM Ltd Versatile board.
280 bool "ARM Ltd. Versatile Express family"
281 select ARCH_WANT_OPTIONAL_GPIOLIB
283 select ARM_TIMER_SP804
285 select GENERIC_CLOCKEVENTS
287 select HAVE_PATA_PLATFORM
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
292 This enables support for the ARM Ltd Versatile Express boards.
296 select ARCH_REQUIRE_GPIOLIB
299 select ARM_PATCH_PHYS_VIRT if MMU
301 This enables support for systems based on the Atmel AT91RM9200,
302 AT91SAM9 and AT91CAP9 processors.
305 bool "Broadcom BCMRING"
309 select ARM_TIMER_SP804
311 select GENERIC_CLOCKEVENTS
312 select ARCH_WANT_OPTIONAL_GPIOLIB
314 Support for Broadcom's BCMRing platform.
317 bool "Cirrus Logic CLPS711x/EP721x-based"
319 select ARCH_USES_GETTIMEOFFSET
321 Support for Cirrus Logic 711x/721x based boards.
324 bool "Cavium Networks CNS3XXX family"
326 select GENERIC_CLOCKEVENTS
328 select MIGHT_HAVE_PCI
329 select PCI_DOMAINS if PCI
331 Support for Cavium Networks CNS3XXX platform.
334 bool "Cortina Systems Gemini"
336 select ARCH_REQUIRE_GPIOLIB
337 select ARCH_USES_GETTIMEOFFSET
339 Support for the Cortina Systems Gemini family SoCs
346 select ARCH_USES_GETTIMEOFFSET
348 This is an evaluation board for the StrongARM processor available
349 from Digital. It has limited hardware on-board, including an
350 Ethernet interface, two PCMCIA sockets, two serial ports and a
359 select ARCH_REQUIRE_GPIOLIB
360 select ARCH_HAS_HOLES_MEMORYMODEL
361 select ARCH_USES_GETTIMEOFFSET
363 This enables support for the Cirrus EP93xx series of CPUs.
365 config ARCH_FOOTBRIDGE
369 select GENERIC_CLOCKEVENTS
371 Support for systems based on the DC21285 companion chip
372 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
375 bool "Freescale MXC/iMX-based"
376 select GENERIC_CLOCKEVENTS
377 select ARCH_REQUIRE_GPIOLIB
380 select HAVE_SCHED_CLOCK
382 Support for Freescale MXC/iMX-based family of processors
385 bool "Freescale MXS-based"
386 select GENERIC_CLOCKEVENTS
387 select ARCH_REQUIRE_GPIOLIB
391 Support for Freescale MXS-based family of processors
394 bool "Hilscher NetX based"
398 select GENERIC_CLOCKEVENTS
400 This enables support for systems based on the Hilscher NetX Soc
403 bool "Hynix HMS720x-based"
406 select ARCH_USES_GETTIMEOFFSET
408 This enables support for systems based on the Hynix HMS720x
416 select ARCH_SUPPORTS_MSI
419 Support for Intel's IOP13XX (XScale) family of processors.
427 select ARCH_REQUIRE_GPIOLIB
429 Support for Intel's 80219 and IOP32X (XScale) family of
438 select ARCH_REQUIRE_GPIOLIB
440 Support for Intel's IOP33X (XScale) family of processors.
447 select ARCH_USES_GETTIMEOFFSET
449 Support for Intel's IXP23xx (XScale) family of processors.
452 bool "IXP2400/2800-based"
456 select ARCH_USES_GETTIMEOFFSET
458 Support for Intel's IXP2400/2800 (XScale) family of processors.
466 select GENERIC_CLOCKEVENTS
467 select HAVE_SCHED_CLOCK
468 select MIGHT_HAVE_PCI
469 select DMABOUNCE if PCI
471 Support for Intel's IXP4XX (XScale) family of processors.
477 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
481 Support for the Marvell Dove SoC 88AP510
484 bool "Marvell Kirkwood"
487 select ARCH_REQUIRE_GPIOLIB
488 select GENERIC_CLOCKEVENTS
491 Support for the following Marvell Kirkwood series SoCs:
492 88F6180, 88F6192 and 88F6281.
495 bool "Marvell Loki (88RC8480)"
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Loki (88RC8480) SoC.
506 select ARCH_REQUIRE_GPIOLIB
509 select USB_ARCH_HAS_OHCI
512 select GENERIC_CLOCKEVENTS
514 Support for the NXP LPC32XX family of processors
517 bool "Marvell MV78xx0"
520 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
524 Support for the following Marvell MV78xx0 series SoCs:
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
536 Support for the following Marvell Orion 5x series SoCs:
537 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
538 Orion-2 (5281), Orion-1-90 (6183).
541 bool "Marvell PXA168/910/MMP2"
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
546 select HAVE_SCHED_CLOCK
551 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
554 bool "Micrel/Kendin KS8695"
556 select ARCH_REQUIRE_GPIOLIB
557 select ARCH_USES_GETTIMEOFFSET
559 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
560 System-on-Chip devices.
563 bool "Nuvoton W90X900 CPU"
565 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
570 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
571 At present, the w90x900 has been renamed nuc900, regarding
572 the ARM series product line, you can login the following
573 link address to know more.
575 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
576 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
579 bool "Nuvoton NUC93X CPU"
583 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
584 low-power and high performance MPEG-4/JPEG multimedia controller chip.
591 select GENERIC_CLOCKEVENTS
594 select HAVE_SCHED_CLOCK
595 select ARCH_HAS_BARRIERS if CACHE_L2X0
596 select ARCH_HAS_CPUFREQ
598 This enables support for NVIDIA Tegra based systems (Tegra APX,
599 Tegra 6xx and Tegra 2 series).
602 bool "Philips Nexperia PNX4008 Mobile"
605 select ARCH_USES_GETTIMEOFFSET
607 This enables support for Philips PNX4008 mobile platform.
610 bool "PXA2xx/PXA3xx-based"
613 select ARCH_HAS_CPUFREQ
616 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
618 select HAVE_SCHED_CLOCK
623 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
628 select GENERIC_CLOCKEVENTS
629 select ARCH_REQUIRE_GPIOLIB
632 Support for Qualcomm MSM/QSD based systems. This runs on the
633 apps processor of the MSM/QSD and depends on a shared memory
634 interface to the modem processor which runs the baseband
635 stack and controls some vital subsystems
636 (clock and power control, etc).
639 bool "Renesas SH-Mobile / R-Mobile"
642 select GENERIC_CLOCKEVENTS
645 select MULTI_IRQ_HANDLER
647 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
654 select ARCH_MAY_HAVE_PC_FDC
655 select HAVE_PATA_PLATFORM
658 select ARCH_SPARSEMEM_ENABLE
659 select ARCH_USES_GETTIMEOFFSET
661 On the Acorn Risc-PC, Linux can support the internal IDE disk and
662 CD-ROM interface, serial and parallel port, and the floppy drive.
669 select ARCH_SPARSEMEM_ENABLE
671 select ARCH_HAS_CPUFREQ
673 select GENERIC_CLOCKEVENTS
675 select HAVE_SCHED_CLOCK
677 select ARCH_REQUIRE_GPIOLIB
679 Support for StrongARM 11x0 based boards.
682 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
684 select ARCH_HAS_CPUFREQ
686 select ARCH_USES_GETTIMEOFFSET
687 select HAVE_S3C2410_I2C if I2C
689 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
690 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
691 the Samsung SMDK2410 development board (and derivatives).
693 Note, the S3C2416 and the S3C2450 are so close that they even share
694 the same SoC ID code. This means that there is no separate machine
695 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
698 bool "Samsung S3C64XX"
704 select ARCH_USES_GETTIMEOFFSET
705 select ARCH_HAS_CPUFREQ
706 select ARCH_REQUIRE_GPIOLIB
707 select SAMSUNG_CLKSRC
708 select SAMSUNG_IRQ_VIC_TIMER
709 select SAMSUNG_IRQ_UART
710 select S3C_GPIO_TRACK
711 select S3C_GPIO_PULL_UPDOWN
712 select S3C_GPIO_CFG_S3C24XX
713 select S3C_GPIO_CFG_S3C64XX
715 select USB_ARCH_HAS_OHCI
716 select SAMSUNG_GPIOLIB_4BIT
717 select HAVE_S3C2410_I2C if I2C
718 select HAVE_S3C2410_WATCHDOG if WATCHDOG
720 Samsung S3C64XX series based systems
723 bool "Samsung S5P6440 S5P6450"
727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
728 select GENERIC_CLOCKEVENTS
729 select HAVE_SCHED_CLOCK
730 select HAVE_S3C2410_I2C if I2C
731 select HAVE_S3C_RTC if RTC_CLASS
733 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
737 bool "Samsung S5PC100"
741 select ARM_L1_CACHE_SHIFT_6
742 select ARCH_USES_GETTIMEOFFSET
743 select HAVE_S3C2410_I2C if I2C
744 select HAVE_S3C_RTC if RTC_CLASS
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 Samsung S5PC100 series based systems
750 bool "Samsung S5PV210/S5PC110"
752 select ARCH_SPARSEMEM_ENABLE
755 select ARM_L1_CACHE_SHIFT_6
756 select ARCH_HAS_CPUFREQ
757 select GENERIC_CLOCKEVENTS
758 select HAVE_SCHED_CLOCK
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C_RTC if RTC_CLASS
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 Samsung S5PV210/S5PC110 series based systems
766 bool "Samsung EXYNOS4"
768 select ARCH_SPARSEMEM_ENABLE
771 select ARCH_HAS_CPUFREQ
772 select GENERIC_CLOCKEVENTS
773 select HAVE_S3C_RTC if RTC_CLASS
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 Samsung EXYNOS4 series based systems
786 select ARCH_USES_GETTIMEOFFSET
788 Support for the StrongARM based Digital DNARD machine, also known
789 as "Shark" (<http://www.shark-linux.de/shark.html>).
792 bool "Telechips TCC ARM926-based systems"
797 select GENERIC_CLOCKEVENTS
799 Support for Telechips TCC ARM926-based systems.
802 bool "ST-Ericsson U300 Series"
806 select HAVE_SCHED_CLOCK
810 select GENERIC_CLOCKEVENTS
814 Support for ST-Ericsson U300 series mobile platforms.
817 bool "ST-Ericsson U8500 Series"
820 select GENERIC_CLOCKEVENTS
822 select ARCH_REQUIRE_GPIOLIB
823 select ARCH_HAS_CPUFREQ
825 Support for ST-Ericsson's Ux500 architecture
828 bool "STMicroelectronics Nomadik"
833 select GENERIC_CLOCKEVENTS
834 select ARCH_REQUIRE_GPIOLIB
836 Support for the Nomadik platform by ST-Ericsson
840 select GENERIC_CLOCKEVENTS
841 select ARCH_REQUIRE_GPIOLIB
845 select GENERIC_ALLOCATOR
846 select GENERIC_IRQ_CHIP
847 select ARCH_HAS_HOLES_MEMORYMODEL
849 Support for TI's DaVinci platform.
854 select ARCH_REQUIRE_GPIOLIB
855 select ARCH_HAS_CPUFREQ
856 select GENERIC_CLOCKEVENTS
857 select HAVE_SCHED_CLOCK
858 select ARCH_HAS_HOLES_MEMORYMODEL
860 Support for TI's OMAP platform (OMAP1/2/3/4).
863 bool "Rockchip RK29xx"
870 select ARM_L1_CACHE_SHIFT_6
872 Support for Rockchip's RK29xx SoCs.
875 bool "Rockchip RK2928"
880 select MIGHT_HAVE_CACHE_L2X0
881 select ARM_ERRATA_754322
883 Support for Rockchip's RK2928 SoCs.
886 bool "Rockchip RK30xx"
892 select MIGHT_HAVE_CACHE_L2X0
893 select ARM_ERRATA_764369
894 select ARM_ERRATA_754322
896 Support for Rockchip's RK30xx SoCs.
901 select ARCH_REQUIRE_GPIOLIB
904 select GENERIC_CLOCKEVENTS
907 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
910 bool "VIA/WonderMedia 85xx"
913 select ARCH_HAS_CPUFREQ
914 select GENERIC_CLOCKEVENTS
915 select ARCH_REQUIRE_GPIOLIB
918 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
922 # This is sorted alphabetically by mach-* pathname. However, plat-*
923 # Kconfigs may be included either alphabetically (according to the
924 # plat- suffix) or along side the corresponding mach-* source.
926 source "arch/arm/mach-at91/Kconfig"
928 source "arch/arm/mach-bcmring/Kconfig"
930 source "arch/arm/mach-clps711x/Kconfig"
932 source "arch/arm/mach-cns3xxx/Kconfig"
934 source "arch/arm/mach-davinci/Kconfig"
936 source "arch/arm/mach-dove/Kconfig"
938 source "arch/arm/mach-ep93xx/Kconfig"
940 source "arch/arm/mach-footbridge/Kconfig"
942 source "arch/arm/mach-gemini/Kconfig"
944 source "arch/arm/mach-h720x/Kconfig"
946 source "arch/arm/mach-integrator/Kconfig"
948 source "arch/arm/mach-iop32x/Kconfig"
950 source "arch/arm/mach-iop33x/Kconfig"
952 source "arch/arm/mach-iop13xx/Kconfig"
954 source "arch/arm/mach-ixp4xx/Kconfig"
956 source "arch/arm/mach-ixp2000/Kconfig"
958 source "arch/arm/mach-ixp23xx/Kconfig"
960 source "arch/arm/mach-kirkwood/Kconfig"
962 source "arch/arm/mach-ks8695/Kconfig"
964 source "arch/arm/mach-loki/Kconfig"
966 source "arch/arm/mach-lpc32xx/Kconfig"
968 source "arch/arm/mach-msm/Kconfig"
970 source "arch/arm/mach-mv78xx0/Kconfig"
972 source "arch/arm/plat-mxc/Kconfig"
974 source "arch/arm/mach-mxs/Kconfig"
976 source "arch/arm/mach-netx/Kconfig"
978 source "arch/arm/mach-nomadik/Kconfig"
979 source "arch/arm/plat-nomadik/Kconfig"
981 source "arch/arm/mach-nuc93x/Kconfig"
983 source "arch/arm/plat-omap/Kconfig"
985 source "arch/arm/mach-omap1/Kconfig"
987 source "arch/arm/mach-omap2/Kconfig"
989 source "arch/arm/mach-orion5x/Kconfig"
991 source "arch/arm/mach-pxa/Kconfig"
992 source "arch/arm/plat-pxa/Kconfig"
994 source "arch/arm/mach-mmp/Kconfig"
996 source "arch/arm/mach-realview/Kconfig"
998 source "arch/arm/plat-rk/Kconfig"
999 source "arch/arm/mach-rk29/Kconfig"
1000 source "arch/arm/mach-rk2928/Kconfig"
1001 source "arch/arm/mach-rk30/Kconfig"
1003 source "arch/arm/mach-sa1100/Kconfig"
1005 source "arch/arm/plat-samsung/Kconfig"
1006 source "arch/arm/plat-s3c24xx/Kconfig"
1007 source "arch/arm/plat-s5p/Kconfig"
1009 source "arch/arm/plat-spear/Kconfig"
1011 source "arch/arm/plat-tcc/Kconfig"
1014 source "arch/arm/mach-s3c2400/Kconfig"
1015 source "arch/arm/mach-s3c2410/Kconfig"
1016 source "arch/arm/mach-s3c2412/Kconfig"
1017 source "arch/arm/mach-s3c2416/Kconfig"
1018 source "arch/arm/mach-s3c2440/Kconfig"
1019 source "arch/arm/mach-s3c2443/Kconfig"
1023 source "arch/arm/mach-s3c64xx/Kconfig"
1026 source "arch/arm/mach-s5p64x0/Kconfig"
1028 source "arch/arm/mach-s5pc100/Kconfig"
1030 source "arch/arm/mach-s5pv210/Kconfig"
1032 source "arch/arm/mach-exynos4/Kconfig"
1034 source "arch/arm/mach-shmobile/Kconfig"
1036 source "arch/arm/mach-tegra/Kconfig"
1038 source "arch/arm/mach-u300/Kconfig"
1040 source "arch/arm/mach-ux500/Kconfig"
1042 source "arch/arm/mach-versatile/Kconfig"
1044 source "arch/arm/mach-vexpress/Kconfig"
1045 source "arch/arm/plat-versatile/Kconfig"
1047 source "arch/arm/mach-vt8500/Kconfig"
1049 source "arch/arm/mach-w90x900/Kconfig"
1051 # Definitions to make life easier
1057 select GENERIC_CLOCKEVENTS
1058 select HAVE_SCHED_CLOCK
1063 select GENERIC_IRQ_CHIP
1064 select HAVE_SCHED_CLOCK
1071 select CLKDEV_LOOKUP
1072 select HAVE_SCHED_CLOCK
1073 select ARCH_HAS_CPUFREQ
1074 select GENERIC_CLOCKEVENTS
1075 select ARCH_REQUIRE_GPIOLIB
1077 config PLAT_VERSATILE
1080 config ARM_TIMER_SP804
1084 source arch/arm/mm/Kconfig
1087 bool "Enable iWMMXt support"
1088 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1089 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1091 Enable support for iWMMXt context switching at run time if
1092 running on a CPU that supports it.
1094 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1097 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1101 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1102 (!ARCH_OMAP3 || OMAP3_EMU)
1106 config MULTI_IRQ_HANDLER
1109 Allow each machine to specify it's own IRQ handler at run time.
1112 source "arch/arm/Kconfig-nommu"
1115 config ARM_ERRATA_411920
1116 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1117 depends on CPU_V6 || CPU_V6K
1119 Invalidation of the Instruction Cache operation can
1120 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1121 It does not affect the MPCore. This option enables the ARM Ltd.
1122 recommended workaround.
1124 config ARM_ERRATA_430973
1125 bool "ARM errata: Stale prediction on replaced interworking branch"
1128 This option enables the workaround for the 430973 Cortex-A8
1129 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1130 interworking branch is replaced with another code sequence at the
1131 same virtual address, whether due to self-modifying code or virtual
1132 to physical address re-mapping, Cortex-A8 does not recover from the
1133 stale interworking branch prediction. This results in Cortex-A8
1134 executing the new code sequence in the incorrect ARM or Thumb state.
1135 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1136 and also flushes the branch target cache at every context switch.
1137 Note that setting specific bits in the ACTLR register may not be
1138 available in non-secure mode.
1140 config ARM_ERRATA_458693
1141 bool "ARM errata: Processor deadlock when a false hazard is created"
1144 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1145 erratum. For very specific sequences of memory operations, it is
1146 possible for a hazard condition intended for a cache line to instead
1147 be incorrectly associated with a different cache line. This false
1148 hazard might then cause a processor deadlock. The workaround enables
1149 the L1 caching of the NEON accesses and disables the PLD instruction
1150 in the ACTLR register. Note that setting specific bits in the ACTLR
1151 register may not be available in non-secure mode.
1153 config ARM_ERRATA_460075
1154 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1157 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1158 erratum. Any asynchronous access to the L2 cache may encounter a
1159 situation in which recent store transactions to the L2 cache are lost
1160 and overwritten with stale memory contents from external memory. The
1161 workaround disables the write-allocate mode for the L2 cache via the
1162 ACTLR register. Note that setting specific bits in the ACTLR register
1163 may not be available in non-secure mode.
1165 config ARM_ERRATA_742230
1166 bool "ARM errata: DMB operation may be faulty"
1167 depends on CPU_V7 && SMP
1169 This option enables the workaround for the 742230 Cortex-A9
1170 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1171 between two write operations may not ensure the correct visibility
1172 ordering of the two writes. This workaround sets a specific bit in
1173 the diagnostic register of the Cortex-A9 which causes the DMB
1174 instruction to behave as a DSB, ensuring the correct behaviour of
1177 config ARM_ERRATA_742231
1178 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1179 depends on CPU_V7 && SMP
1181 This option enables the workaround for the 742231 Cortex-A9
1182 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1183 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1184 accessing some data located in the same cache line, may get corrupted
1185 data due to bad handling of the address hazard when the line gets
1186 replaced from one of the CPUs at the same time as another CPU is
1187 accessing it. This workaround sets specific bits in the diagnostic
1188 register of the Cortex-A9 which reduces the linefill issuing
1189 capabilities of the processor.
1191 config PL310_ERRATA_588369
1192 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1193 depends on CACHE_L2X0
1195 The PL310 L2 cache controller implements three types of Clean &
1196 Invalidate maintenance operations: by Physical Address
1197 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1198 They are architecturally defined to behave as the execution of a
1199 clean operation followed immediately by an invalidate operation,
1200 both performing to the same memory location. This functionality
1201 is not correctly implemented in PL310 as clean lines are not
1202 invalidated as a result of these operations.
1204 config ARM_ERRATA_720789
1205 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1206 depends on CPU_V7 && SMP
1208 This option enables the workaround for the 720789 Cortex-A9 (prior to
1209 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1210 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1211 As a consequence of this erratum, some TLB entries which should be
1212 invalidated are not, resulting in an incoherency in the system page
1213 tables. The workaround changes the TLB flushing routines to invalidate
1214 entries regardless of the ASID.
1216 config PL310_ERRATA_727915
1217 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1218 depends on CACHE_L2X0
1220 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1221 operation (offset 0x7FC). This operation runs in background so that
1222 PL310 can handle normal accesses while it is in progress. Under very
1223 rare circumstances, due to this erratum, write data can be lost when
1224 PL310 treats a cacheable write transaction during a Clean &
1225 Invalidate by Way operation.
1227 config ARM_ERRATA_743622
1228 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1231 This option enables the workaround for the 743622 Cortex-A9
1232 (r2p*) erratum. Under very rare conditions, a faulty
1233 optimisation in the Cortex-A9 Store Buffer may lead to data
1234 corruption. This workaround sets a specific bit in the diagnostic
1235 register of the Cortex-A9 which disables the Store Buffer
1236 optimisation, preventing the defect from occurring. This has no
1237 visible impact on the overall performance or power consumption of the
1240 config ARM_ERRATA_751472
1241 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1242 depends on CPU_V7 && SMP
1244 This option enables the workaround for the 751472 Cortex-A9 (prior
1245 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1246 completion of a following broadcasted operation if the second
1247 operation is received by a CPU before the ICIALLUIS has completed,
1248 potentially leading to corrupted entries in the cache or TLB.
1250 config ARM_ERRATA_753970
1251 bool "ARM errata: cache sync operation may be faulty"
1252 depends on CACHE_PL310
1254 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1256 Under some condition the effect of cache sync operation on
1257 the store buffer still remains when the operation completes.
1258 This means that the store buffer is always asked to drain and
1259 this prevents it from merging any further writes. The workaround
1260 is to replace the normal offset of cache sync operation (0x730)
1261 by another offset targeting an unmapped PL310 register 0x740.
1262 This has the same effect as the cache sync operation: store buffer
1263 drain and waiting for all buffers empty.
1265 config ARM_ERRATA_754322
1266 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1269 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1270 r3p*) erratum. A speculative memory access may cause a page table walk
1271 which starts prior to an ASID switch but completes afterwards. This
1272 can populate the micro-TLB with a stale entry which may be hit with
1273 the new ASID. This workaround places two dsb instructions in the mm
1274 switching code so that no page table walks can cross the ASID switch.
1276 config ARM_ERRATA_754327
1277 bool "ARM errata: no automatic Store Buffer drain"
1278 depends on CPU_V7 && SMP
1280 This option enables the workaround for the 754327 Cortex-A9 (prior to
1281 r2p0) erratum. The Store Buffer does not have any automatic draining
1282 mechanism and therefore a livelock may occur if an external agent
1283 continuously polls a memory location waiting to observe an update.
1284 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1285 written polling loops from denying visibility of updates to memory.
1287 config ARM_ERRATA_764369
1288 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1289 depends on CPU_V7 && SMP
1291 This option enables the workaround for erratum 764369
1292 affecting Cortex-A9 MPCore with two or more processors (all
1293 current revisions). Under certain timing circumstances, a data
1294 cache line maintenance operation by MVA targeting an Inner
1295 Shareable memory region may fail to proceed up to either the
1296 Point of Coherency or to the Point of Unification of the
1297 system. This workaround adds a DSB instruction before the
1298 relevant cache maintenance functions and sets a specific bit
1299 in the diagnostic control register of the SCU.
1301 config PL310_ERRATA_769419
1302 bool "PL310 errata: no automatic Store Buffer drain"
1303 depends on CACHE_L2X0
1305 On revisions of the PL310 prior to r3p2, the Store Buffer does
1306 not automatically drain. This can cause normal, non-cacheable
1307 writes to be retained when the memory system is idle, leading
1308 to suboptimal I/O performance for drivers using coherent DMA.
1309 This option adds a write barrier to the cpu_idle loop so that,
1310 on systems with an outer cache, the store buffer is drained
1315 source "arch/arm/common/Kconfig"
1325 Find out whether you have ISA slots on your motherboard. ISA is the
1326 name of a bus system, i.e. the way the CPU talks to the other stuff
1327 inside your box. Other bus systems are PCI, EISA, MicroChannel
1328 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1329 newer boards don't support it. If you have ISA, say Y, otherwise N.
1331 # Select ISA DMA controller support
1336 # Select ISA DMA interface
1341 bool "PCI support" if MIGHT_HAVE_PCI
1343 Find out whether you have a PCI motherboard. PCI is the name of a
1344 bus system, i.e. the way the CPU talks to the other stuff inside
1345 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1346 VESA. If you have PCI, say Y, otherwise N.
1352 config PCI_NANOENGINE
1353 bool "BSE nanoEngine PCI support"
1354 depends on SA1100_NANOENGINE
1356 Enable PCI on the BSE nanoEngine board.
1361 # Select the host bridge type
1362 config PCI_HOST_VIA82C505
1364 depends on PCI && ARCH_SHARK
1367 config PCI_HOST_ITE8152
1369 depends on PCI && MACH_ARMCORE
1373 source "drivers/pci/Kconfig"
1375 source "drivers/pcmcia/Kconfig"
1379 menu "Kernel Features"
1381 source "kernel/time/Kconfig"
1386 This option should be selected by machines which have an SMP-
1389 The only effect of this option is to make the SMP-related
1390 options available to the user for configuration.
1393 bool "Symmetric Multi-Processing"
1394 depends on CPU_V6K || CPU_V7
1395 depends on GENERIC_CLOCKEVENTS
1398 select USE_GENERIC_SMP_HELPERS
1399 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1401 This enables support for systems with more than one CPU. If you have
1402 a system with only one CPU, like most personal computers, say N. If
1403 you have a system with more than one CPU, say Y.
1405 If you say N here, the kernel will run on single and multiprocessor
1406 machines, but will use only one CPU of a multiprocessor machine. If
1407 you say Y here, the kernel will run on many, but not all, single
1408 processor machines. On a single processor machine, the kernel will
1409 run faster if you say N here.
1411 See also <file:Documentation/i386/IO-APIC.txt>,
1412 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1413 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1415 If you don't know what to do here, say N.
1418 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1419 depends on EXPERIMENTAL
1420 depends on SMP && !XIP_KERNEL
1423 SMP kernels contain instructions which fail on non-SMP processors.
1424 Enabling this option allows the kernel to modify itself to make
1425 these instructions safe. Disabling it allows about 1K of space
1428 If you don't know what to do here, say Y.
1434 This option enables support for the ARM system coherency unit
1441 This options enables support for the ARM timer and watchdog unit
1444 prompt "Memory split"
1447 Select the desired split between kernel and user memory.
1449 If you are not absolutely sure what you are doing, leave this
1453 bool "3G/1G user/kernel split"
1455 bool "2G/2G user/kernel split"
1457 bool "1G/3G user/kernel split"
1462 default 0x40000000 if VMSPLIT_1G
1463 default 0x80000000 if VMSPLIT_2G
1467 int "Maximum number of CPUs (2-32)"
1473 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1474 depends on SMP && HOTPLUG && EXPERIMENTAL
1476 Say Y here to experiment with turning CPUs off and on. CPUs
1477 can be controlled through /sys/devices/system/cpu.
1480 bool "Use local timer interrupts"
1483 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1485 Enable support for local timers on SMP platforms, rather then the
1486 legacy IPI broadcast method. Local timers allows the system
1487 accounting to be spread across the timer interval, preventing a
1488 "thundering herd" at every timer tick.
1490 source kernel/Kconfig.preempt
1494 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1495 ARCH_S5PV210 || ARCH_EXYNOS4
1496 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1497 default AT91_TIMER_HZ if ARCH_AT91
1498 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1501 config THUMB2_KERNEL
1502 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1503 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1505 select ARM_ASM_UNIFIED
1507 By enabling this option, the kernel will be compiled in
1508 Thumb-2 mode. A compiler/assembler that understand the unified
1509 ARM-Thumb syntax is needed.
1513 config THUMB2_AVOID_R_ARM_THM_JUMP11
1514 bool "Work around buggy Thumb-2 short branch relocations in gas"
1515 depends on THUMB2_KERNEL && MODULES
1518 Various binutils versions can resolve Thumb-2 branches to
1519 locally-defined, preemptible global symbols as short-range "b.n"
1520 branch instructions.
1522 This is a problem, because there's no guarantee the final
1523 destination of the symbol, or any candidate locations for a
1524 trampoline, are within range of the branch. For this reason, the
1525 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1526 relocation in modules at all, and it makes little sense to add
1529 The symptom is that the kernel fails with an "unsupported
1530 relocation" error when loading some modules.
1532 Until fixed tools are available, passing
1533 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1534 code which hits this problem, at the cost of a bit of extra runtime
1535 stack usage in some cases.
1537 The problem is described in more detail at:
1538 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1540 Only Thumb-2 kernels are affected.
1542 Unless you are sure your tools don't have this problem, say Y.
1544 config ARM_ASM_UNIFIED
1548 bool "Use the ARM EABI to compile the kernel"
1550 This option allows for the kernel to be compiled using the latest
1551 ARM ABI (aka EABI). This is only useful if you are using a user
1552 space environment that is also compiled with EABI.
1554 Since there are major incompatibilities between the legacy ABI and
1555 EABI, especially with regard to structure member alignment, this
1556 option also changes the kernel syscall calling convention to
1557 disambiguate both ABIs and allow for backward compatibility support
1558 (selected with CONFIG_OABI_COMPAT).
1560 To use this you need GCC version 4.0.0 or later.
1563 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1564 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1567 This option preserves the old syscall interface along with the
1568 new (ARM EABI) one. It also provides a compatibility layer to
1569 intercept syscalls that have structure arguments which layout
1570 in memory differs between the legacy ABI and the new ARM EABI
1571 (only for non "thumb" binaries). This option adds a tiny
1572 overhead to all syscalls and produces a slightly larger kernel.
1573 If you know you'll be using only pure EABI user space then you
1574 can say N here. If this option is not selected and you attempt
1575 to execute a legacy ABI binary then the result will be
1576 UNPREDICTABLE (in fact it can be predicted that it won't work
1577 at all). If in doubt say Y.
1579 config ARCH_HAS_HOLES_MEMORYMODEL
1582 config ARCH_SPARSEMEM_ENABLE
1585 config ARCH_SPARSEMEM_DEFAULT
1586 def_bool ARCH_SPARSEMEM_ENABLE
1588 config ARCH_SELECT_MEMORY_MODEL
1589 def_bool ARCH_SPARSEMEM_ENABLE
1591 config HAVE_ARCH_PFN_VALID
1592 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1595 bool "High Memory Support"
1598 The address space of ARM processors is only 4 Gigabytes large
1599 and it has to accommodate user address space, kernel address
1600 space as well as some memory mapped IO. That means that, if you
1601 have a large amount of physical memory and/or IO, not all of the
1602 memory can be "permanently mapped" by the kernel. The physical
1603 memory that is not permanently mapped is called "high memory".
1605 Depending on the selected kernel/user memory split, minimum
1606 vmalloc space and actual amount of RAM, you may not need this
1607 option which should result in a slightly faster kernel.
1612 bool "Allocate 2nd-level pagetables from highmem"
1615 config HW_PERF_EVENTS
1616 bool "Enable hardware performance counter support for perf events"
1617 depends on PERF_EVENTS && CPU_HAS_PMU
1620 Enable hardware performance counter support for perf events. If
1621 disabled, perf events will use software events only.
1625 config FORCE_MAX_ZONEORDER
1626 int "Maximum zone order" if ARCH_SHMOBILE
1627 range 11 64 if ARCH_SHMOBILE
1628 default "9" if SA1111
1631 The kernel memory allocator divides physically contiguous memory
1632 blocks into "zones", where each zone is a power of two number of
1633 pages. This option selects the largest power of two that the kernel
1634 keeps in the memory allocator. If you need to allocate very large
1635 blocks of physically contiguous memory, then you may need to
1636 increase this value.
1638 This config option is actually maximum order plus one. For example,
1639 a value of 11 means that the largest free memory block is 2^10 pages.
1642 bool "Timer and CPU usage LEDs"
1643 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1644 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1645 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1646 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1647 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1648 ARCH_AT91 || ARCH_DAVINCI || \
1649 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1651 If you say Y here, the LEDs on your machine will be used
1652 to provide useful information about your current system status.
1654 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1655 be able to select which LEDs are active using the options below. If
1656 you are compiling a kernel for the EBSA-110 or the LART however, the
1657 red LED will simply flash regularly to indicate that the system is
1658 still functional. It is safe to say Y here if you have a CATS
1659 system, but the driver will do nothing.
1662 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1663 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1664 || MACH_OMAP_PERSEUS2
1666 depends on !GENERIC_CLOCKEVENTS
1667 default y if ARCH_EBSA110
1669 If you say Y here, one of the system LEDs (the green one on the
1670 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1671 will flash regularly to indicate that the system is still
1672 operational. This is mainly useful to kernel hackers who are
1673 debugging unstable kernels.
1675 The LART uses the same LED for both Timer LED and CPU usage LED
1676 functions. You may choose to use both, but the Timer LED function
1677 will overrule the CPU usage LED.
1680 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1682 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1683 || MACH_OMAP_PERSEUS2
1686 If you say Y here, the red LED will be used to give a good real
1687 time indication of CPU usage, by lighting whenever the idle task
1688 is not currently executing.
1690 The LART uses the same LED for both Timer LED and CPU usage LED
1691 functions. You may choose to use both, but the Timer LED function
1692 will overrule the CPU usage LED.
1694 config ALIGNMENT_TRAP
1696 depends on CPU_CP15_MMU
1697 default y if !ARCH_EBSA110
1698 select HAVE_PROC_CPU if PROC_FS
1700 ARM processors cannot fetch/store information which is not
1701 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1702 address divisible by 4. On 32-bit ARM processors, these non-aligned
1703 fetch/store instructions will be emulated in software if you say
1704 here, which has a severe performance impact. This is necessary for
1705 correct operation of some network protocols. With an IP-only
1706 configuration it is safe to say N, otherwise say Y.
1708 config UACCESS_WITH_MEMCPY
1709 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1710 depends on MMU && EXPERIMENTAL
1711 default y if CPU_FEROCEON
1713 Implement faster copy_to_user and clear_user methods for CPU
1714 cores where a 8-word STM instruction give significantly higher
1715 memory write throughput than a sequence of individual 32bit stores.
1717 A possible side effect is a slight increase in scheduling latency
1718 between threads sharing the same address space if they invoke
1719 such copy operations with large buffers.
1721 However, if the CPU data cache is using a write-allocate mode,
1722 this option is unlikely to provide any performance gain.
1726 prompt "Enable seccomp to safely compute untrusted bytecode"
1728 This kernel feature is useful for number crunching applications
1729 that may need to compute untrusted bytecode during their
1730 execution. By using pipes or other transports made available to
1731 the process as file descriptors supporting the read/write
1732 syscalls, it's possible to isolate those applications in
1733 their own address space using seccomp. Once seccomp is
1734 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1735 and the task is only allowed to execute a few safe syscalls
1736 defined by each seccomp mode.
1738 config CC_STACKPROTECTOR
1739 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1740 depends on EXPERIMENTAL
1742 This option turns on the -fstack-protector GCC feature. This
1743 feature puts, at the beginning of functions, a canary value on
1744 the stack just before the return address, and validates
1745 the value just before actually returning. Stack based buffer
1746 overflows (that need to overwrite this return address) now also
1747 overwrite the canary, which gets detected and the attack is then
1748 neutralized via a kernel panic.
1749 This feature requires gcc version 4.2 or above.
1751 config DEPRECATED_PARAM_STRUCT
1752 bool "Provide old way to pass kernel parameters"
1754 This was deprecated in 2001 and announced to live on for 5 years.
1755 Some old boot loaders still use this way.
1757 config ARM_FLUSH_CONSOLE_ON_RESTART
1758 bool "Force flush the console on restart"
1760 If the console is locked while the system is rebooted, the messages
1761 in the temporary logbuffer would not have propogated to all the
1762 console drivers. This option forces the console lock to be
1763 released if it failed to be acquired, which will cause all the
1764 pending messages to be flushed.
1771 bool "Flattened Device Tree support"
1773 select OF_EARLY_FLATTREE
1775 Include support for flattened device tree machine descriptions.
1777 # Compressed boot loader in ROM. Yes, we really want to ask about
1778 # TEXT and BSS so we preserve their values in the config files.
1779 config ZBOOT_ROM_TEXT
1780 hex "Compressed ROM boot loader base address"
1783 The physical address at which the ROM-able zImage is to be
1784 placed in the target. Platforms which normally make use of
1785 ROM-able zImage formats normally set this to a suitable
1786 value in their defconfig file.
1788 If ZBOOT_ROM is not enabled, this has no effect.
1790 config ZBOOT_ROM_BSS
1791 hex "Compressed ROM boot loader BSS address"
1794 The base address of an area of read/write memory in the target
1795 for the ROM-able zImage which must be available while the
1796 decompressor is running. It must be large enough to hold the
1797 entire decompressed kernel plus an additional 128 KiB.
1798 Platforms which normally make use of ROM-able zImage formats
1799 normally set this to a suitable value in their defconfig file.
1801 If ZBOOT_ROM is not enabled, this has no effect.
1804 bool "Compressed boot loader in ROM/flash"
1805 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1807 Say Y here if you intend to execute your compressed kernel image
1808 (zImage) directly from ROM or flash. If unsure, say N.
1810 config ZBOOT_ROM_MMCIF
1811 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1812 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1814 Say Y here to include experimental MMCIF loading code in the
1815 ROM-able zImage. With this enabled it is possible to write the
1816 the ROM-able zImage kernel image to an MMC card and boot the
1817 kernel straight from the reset vector. At reset the processor
1818 Mask ROM will load the first part of the the ROM-able zImage
1819 which in turn loads the rest the kernel image to RAM using the
1820 MMCIF hardware block.
1823 string "Default kernel command string"
1826 On some architectures (EBSA110 and CATS), there is currently no way
1827 for the boot loader to pass arguments to the kernel. For these
1828 architectures, you should supply some command-line options at build
1829 time by entering them here. As a minimum, you should specify the
1830 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1833 prompt "Kernel command line type" if CMDLINE != ""
1834 default CMDLINE_FROM_BOOTLOADER
1836 config CMDLINE_FROM_BOOTLOADER
1837 bool "Use bootloader kernel arguments if available"
1839 Uses the command-line options passed by the boot loader. If
1840 the boot loader doesn't provide any, the default kernel command
1841 string provided in CMDLINE will be used.
1843 config CMDLINE_EXTEND
1844 bool "Extend bootloader kernel arguments"
1846 The command-line arguments provided by the boot loader will be
1847 appended to the default kernel command string.
1849 config CMDLINE_FORCE
1850 bool "Always use the default kernel command string"
1852 Always use the default kernel command string, even if the boot
1853 loader passes other arguments to the kernel.
1854 This is useful if you cannot or don't want to change the
1855 command-line options your boot loader passes to the kernel.
1859 bool "Kernel Execute-In-Place from ROM"
1860 depends on !ZBOOT_ROM
1862 Execute-In-Place allows the kernel to run from non-volatile storage
1863 directly addressable by the CPU, such as NOR flash. This saves RAM
1864 space since the text section of the kernel is not loaded from flash
1865 to RAM. Read-write sections, such as the data section and stack,
1866 are still copied to RAM. The XIP kernel is not compressed since
1867 it has to run directly from flash, so it will take more space to
1868 store it. The flash address used to link the kernel object files,
1869 and for storing it, is configuration dependent. Therefore, if you
1870 say Y here, you must know the proper physical address where to
1871 store the kernel image depending on your own flash memory usage.
1873 Also note that the make target becomes "make xipImage" rather than
1874 "make zImage" or "make Image". The final kernel binary to put in
1875 ROM memory will be arch/arm/boot/xipImage.
1879 config XIP_PHYS_ADDR
1880 hex "XIP Kernel Physical Location"
1881 depends on XIP_KERNEL
1882 default "0x00080000"
1884 This is the physical address in your flash memory the kernel will
1885 be linked for and stored to. This address is dependent on your
1889 bool "Kexec system call (EXPERIMENTAL)"
1890 depends on EXPERIMENTAL
1892 kexec is a system call that implements the ability to shutdown your
1893 current kernel, and to start another kernel. It is like a reboot
1894 but it is independent of the system firmware. And like a reboot
1895 you can start any kernel with it, not just Linux.
1897 It is an ongoing process to be certain the hardware in a machine
1898 is properly shutdown, so do not be surprised if this code does not
1899 initially work for you. It may help to enable device hotplugging
1903 bool "Export atags in procfs"
1907 Should the atags used to boot the kernel be exported in an "atags"
1908 file in procfs. Useful with kexec.
1911 bool "Build kdump crash kernel (EXPERIMENTAL)"
1912 depends on EXPERIMENTAL
1914 Generate crash dump after being started by kexec. This should
1915 be normally only set in special crash dump kernels which are
1916 loaded in the main kernel with kexec-tools into a specially
1917 reserved region and then later executed after a crash by
1918 kdump/kexec. The crash dump kernel must be compiled to a
1919 memory address not used by the main kernel
1921 For more details see Documentation/kdump/kdump.txt
1923 config AUTO_ZRELADDR
1924 bool "Auto calculation of the decompressed kernel image address"
1925 depends on !ZBOOT_ROM && !ARCH_U300
1927 ZRELADDR is the physical address where the decompressed kernel
1928 image will be placed. If AUTO_ZRELADDR is selected, the address
1929 will be determined at run-time by masking the current IP with
1930 0xf8000000. This assumes the zImage being placed in the first 128MB
1931 from start of memory.
1935 menu "CPU Power Management"
1939 source "drivers/cpufreq/Kconfig"
1942 tristate "CPUfreq driver for i.MX CPUs"
1943 depends on ARCH_MXC && CPU_FREQ
1944 select CPU_FREQ_TABLE
1946 This enables the CPUfreq driver for i.MX CPUs.
1948 config CPU_FREQ_SA1100
1951 config CPU_FREQ_SA1110
1954 config CPU_FREQ_INTEGRATOR
1955 tristate "CPUfreq driver for ARM Integrator CPUs"
1956 depends on ARCH_INTEGRATOR && CPU_FREQ
1959 This enables the CPUfreq driver for ARM Integrator CPUs.
1961 For details, take a look at <file:Documentation/cpu-freq>.
1967 depends on CPU_FREQ && ARCH_PXA && PXA25x
1969 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1971 config CPU_FREQ_S3C64XX
1972 bool "CPUfreq support for Samsung S3C64XX CPUs"
1973 depends on CPU_FREQ && CPU_S3C6410
1978 Internal configuration node for common cpufreq on Samsung SoC
1980 config CPU_FREQ_S3C24XX
1981 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1982 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1985 This enables the CPUfreq driver for the Samsung S3C24XX family
1988 For details, take a look at <file:Documentation/cpu-freq>.
1992 config CPU_FREQ_S3C24XX_PLL
1993 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1994 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1996 Compile in support for changing the PLL frequency from the
1997 S3C24XX series CPUfreq driver. The PLL takes time to settle
1998 after a frequency change, so by default it is not enabled.
2000 This also means that the PLL tables for the selected CPU(s) will
2001 be built which may increase the size of the kernel image.
2003 config CPU_FREQ_S3C24XX_DEBUG
2004 bool "Debug CPUfreq Samsung driver core"
2005 depends on CPU_FREQ_S3C24XX
2007 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2009 config CPU_FREQ_S3C24XX_IODEBUG
2010 bool "Debug CPUfreq Samsung driver IO timing"
2011 depends on CPU_FREQ_S3C24XX
2013 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2015 config CPU_FREQ_S3C24XX_DEBUGFS
2016 bool "Export debugfs for CPUFreq"
2017 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2019 Export status information via debugfs.
2023 source "drivers/cpuidle/Kconfig"
2027 menu "Floating point emulation"
2029 comment "At least one emulation must be selected"
2032 bool "NWFPE math emulation"
2033 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2035 Say Y to include the NWFPE floating point emulator in the kernel.
2036 This is necessary to run most binaries. Linux does not currently
2037 support floating point hardware so you need to say Y here even if
2038 your machine has an FPA or floating point co-processor podule.
2040 You may say N here if you are going to load the Acorn FPEmulator
2041 early in the bootup.
2044 bool "Support extended precision"
2045 depends on FPE_NWFPE
2047 Say Y to include 80-bit support in the kernel floating-point
2048 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2049 Note that gcc does not generate 80-bit operations by default,
2050 so in most cases this option only enlarges the size of the
2051 floating point emulator without any good reason.
2053 You almost surely want to say N here.
2056 bool "FastFPE math emulation (EXPERIMENTAL)"
2057 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2059 Say Y here to include the FAST floating point emulator in the kernel.
2060 This is an experimental much faster emulator which now also has full
2061 precision for the mantissa. It does not support any exceptions.
2062 It is very simple, and approximately 3-6 times faster than NWFPE.
2064 It should be sufficient for most programs. It may be not suitable
2065 for scientific calculations, but you have to check this for yourself.
2066 If you do not feel you need a faster FP emulation you should better
2070 bool "VFP-format floating point maths"
2071 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2073 Say Y to include VFP support code in the kernel. This is needed
2074 if your hardware includes a VFP unit.
2076 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2077 release notes and additional status information.
2079 Say N if your target does not have VFP hardware.
2087 bool "Advanced SIMD (NEON) Extension support"
2088 depends on VFPv3 && CPU_V7
2090 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2095 menu "Userspace binary formats"
2097 source "fs/Kconfig.binfmt"
2100 tristate "RISC OS personality"
2103 Say Y here to include the kernel code necessary if you want to run
2104 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2105 experimental; if this sounds frightening, say N and sleep in peace.
2106 You can also say M here to compile this support as a module (which
2107 will be called arthur).
2111 menu "Power management options"
2113 source "kernel/power/Kconfig"
2115 config ARCH_SUSPEND_POSSIBLE
2116 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2117 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2118 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2123 source "net/Kconfig"
2125 source "drivers/Kconfig"
2129 source "arch/arm/Kconfig.debug"
2131 source "security/Kconfig"
2133 source "crypto/Kconfig"
2135 source "lib/Kconfig"