5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
46 config SYS_SUPPORTS_APM_EMULATION
49 config HAVE_SCHED_CLOCK
55 config ARCH_USES_GETTIMEOFFSET
59 config GENERIC_CLOCKEVENTS
62 config GENERIC_CLOCKEVENTS_BROADCAST
64 depends on GENERIC_CLOCKEVENTS
73 select GENERIC_ALLOCATOR
84 The Extended Industry Standard Architecture (EISA) bus was
85 developed as an open alternative to the IBM MicroChannel bus.
87 The EISA bus provided some of the features of the IBM MicroChannel
88 bus while maintaining backward compatibility with cards made for
89 the older ISA bus. The EISA bus saw limited use between 1988 and
90 1995 when it was made obsolete by the PCI bus.
92 Say Y here if you are building a kernel for an EISA-based machine.
102 MicroChannel Architecture is found in some IBM PS/2 machines and
103 laptops. It is a bus system similar to PCI or ISA. See
104 <file:Documentation/mca.txt> (and especially the web page given
105 there) before attempting to build an MCA bus kernel.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config HARDIRQS_SW_RESEND
128 config GENERIC_IRQ_PROBE
132 config GENERIC_LOCKBREAK
135 depends on SMP && PREEMPT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config ARCH_HAS_CPU_IDLE_WAIT
160 config GENERIC_HWEIGHT
164 config GENERIC_CALIBRATE_DELAY
168 config ARCH_MAY_HAVE_PC_FDC
174 config NEED_DMA_MAP_STATE
177 config GENERIC_ISA_DMA
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
196 depends on EXPERIMENTAL
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary, or theoretically 64K
206 for the MSM machine class.
208 config ARM_PATCH_PHYS_VIRT_16BIT
210 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
212 This option extends the physical to virtual translation patching
213 to allow physical memory down to a theoretical minimum of 64K
216 source "init/Kconfig"
218 source "kernel/Kconfig.freezer"
223 bool "MMU-based Paged Memory Management Support"
226 Select if you want MMU-based virtualised addressing space
227 support by paged memory management. If unsure, say 'Y'.
230 # The "ARM system type" choice list is ordered alphabetically by option
231 # text. Please add new entries in the option alphabetic order.
234 prompt "ARM system type"
235 default ARCH_VERSATILE
237 config ARCH_INTEGRATOR
238 bool "ARM Ltd. Integrator family"
240 select ARCH_HAS_CPUFREQ
243 select GENERIC_CLOCKEVENTS
244 select PLAT_VERSATILE
245 select PLAT_VERSATILE_FPGA_IRQ
247 Support for ARM's Integrator platform.
250 bool "ARM Ltd. RealView family"
254 select GENERIC_CLOCKEVENTS
255 select ARCH_WANT_OPTIONAL_GPIOLIB
256 select PLAT_VERSATILE
257 select PLAT_VERSATILE_CLCD
258 select ARM_TIMER_SP804
259 select GPIO_PL061 if GPIOLIB
261 This enables support for ARM Ltd RealView boards.
263 config ARCH_VERSATILE
264 bool "ARM Ltd. Versatile family"
269 select GENERIC_CLOCKEVENTS
270 select ARCH_WANT_OPTIONAL_GPIOLIB
271 select PLAT_VERSATILE
272 select PLAT_VERSATILE_CLCD
273 select PLAT_VERSATILE_FPGA_IRQ
274 select ARM_TIMER_SP804
276 This enables support for ARM Ltd Versatile board.
279 bool "ARM Ltd. Versatile Express family"
280 select ARCH_WANT_OPTIONAL_GPIOLIB
282 select ARM_TIMER_SP804
284 select GENERIC_CLOCKEVENTS
286 select HAVE_PATA_PLATFORM
288 select PLAT_VERSATILE
289 select PLAT_VERSATILE_CLCD
291 This enables support for the ARM Ltd Versatile Express boards.
295 select ARCH_REQUIRE_GPIOLIB
298 select ARM_PATCH_PHYS_VIRT if MMU
300 This enables support for systems based on the Atmel AT91RM9200,
301 AT91SAM9 and AT91CAP9 processors.
304 bool "Broadcom BCMRING"
308 select ARM_TIMER_SP804
310 select GENERIC_CLOCKEVENTS
311 select ARCH_WANT_OPTIONAL_GPIOLIB
313 Support for Broadcom's BCMRing platform.
316 bool "Cirrus Logic CLPS711x/EP721x-based"
318 select ARCH_USES_GETTIMEOFFSET
320 Support for Cirrus Logic 711x/721x based boards.
323 bool "Cavium Networks CNS3XXX family"
325 select GENERIC_CLOCKEVENTS
327 select MIGHT_HAVE_PCI
328 select PCI_DOMAINS if PCI
330 Support for Cavium Networks CNS3XXX platform.
333 bool "Cortina Systems Gemini"
335 select ARCH_REQUIRE_GPIOLIB
336 select ARCH_USES_GETTIMEOFFSET
338 Support for the Cortina Systems Gemini family SoCs
345 select ARCH_USES_GETTIMEOFFSET
347 This is an evaluation board for the StrongARM processor available
348 from Digital. It has limited hardware on-board, including an
349 Ethernet interface, two PCMCIA sockets, two serial ports and a
358 select ARCH_REQUIRE_GPIOLIB
359 select ARCH_HAS_HOLES_MEMORYMODEL
360 select ARCH_USES_GETTIMEOFFSET
362 This enables support for the Cirrus EP93xx series of CPUs.
364 config ARCH_FOOTBRIDGE
368 select GENERIC_CLOCKEVENTS
370 Support for systems based on the DC21285 companion chip
371 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
374 bool "Freescale MXC/iMX-based"
375 select GENERIC_CLOCKEVENTS
376 select ARCH_REQUIRE_GPIOLIB
379 select HAVE_SCHED_CLOCK
381 Support for Freescale MXC/iMX-based family of processors
384 bool "Freescale MXS-based"
385 select GENERIC_CLOCKEVENTS
386 select ARCH_REQUIRE_GPIOLIB
390 Support for Freescale MXS-based family of processors
393 bool "Hilscher NetX based"
397 select GENERIC_CLOCKEVENTS
399 This enables support for systems based on the Hilscher NetX Soc
402 bool "Hynix HMS720x-based"
405 select ARCH_USES_GETTIMEOFFSET
407 This enables support for systems based on the Hynix HMS720x
415 select ARCH_SUPPORTS_MSI
418 Support for Intel's IOP13XX (XScale) family of processors.
426 select ARCH_REQUIRE_GPIOLIB
428 Support for Intel's 80219 and IOP32X (XScale) family of
437 select ARCH_REQUIRE_GPIOLIB
439 Support for Intel's IOP33X (XScale) family of processors.
446 select ARCH_USES_GETTIMEOFFSET
448 Support for Intel's IXP23xx (XScale) family of processors.
451 bool "IXP2400/2800-based"
455 select ARCH_USES_GETTIMEOFFSET
457 Support for Intel's IXP2400/2800 (XScale) family of processors.
465 select GENERIC_CLOCKEVENTS
466 select HAVE_SCHED_CLOCK
467 select MIGHT_HAVE_PCI
468 select DMABOUNCE if PCI
470 Support for Intel's IXP4XX (XScale) family of processors.
476 select ARCH_REQUIRE_GPIOLIB
477 select GENERIC_CLOCKEVENTS
480 Support for the Marvell Dove SoC 88AP510
483 bool "Marvell Kirkwood"
486 select ARCH_REQUIRE_GPIOLIB
487 select GENERIC_CLOCKEVENTS
490 Support for the following Marvell Kirkwood series SoCs:
491 88F6180, 88F6192 and 88F6281.
494 bool "Marvell Loki (88RC8480)"
496 select GENERIC_CLOCKEVENTS
499 Support for the Marvell Loki (88RC8480) SoC.
505 select ARCH_REQUIRE_GPIOLIB
508 select USB_ARCH_HAS_OHCI
511 select GENERIC_CLOCKEVENTS
513 Support for the NXP LPC32XX family of processors
516 bool "Marvell MV78xx0"
519 select ARCH_REQUIRE_GPIOLIB
520 select GENERIC_CLOCKEVENTS
523 Support for the following Marvell MV78xx0 series SoCs:
531 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
535 Support for the following Marvell Orion 5x series SoCs:
536 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
537 Orion-2 (5281), Orion-1-90 (6183).
540 bool "Marvell PXA168/910/MMP2"
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
545 select HAVE_SCHED_CLOCK
550 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
553 bool "Micrel/Kendin KS8695"
555 select ARCH_REQUIRE_GPIOLIB
556 select ARCH_USES_GETTIMEOFFSET
558 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
559 System-on-Chip devices.
562 bool "Nuvoton W90X900 CPU"
564 select ARCH_REQUIRE_GPIOLIB
567 select GENERIC_CLOCKEVENTS
569 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
570 At present, the w90x900 has been renamed nuc900, regarding
571 the ARM series product line, you can login the following
572 link address to know more.
574 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
575 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
578 bool "Nuvoton NUC93X CPU"
582 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
583 low-power and high performance MPEG-4/JPEG multimedia controller chip.
590 select GENERIC_CLOCKEVENTS
593 select HAVE_SCHED_CLOCK
594 select ARCH_HAS_BARRIERS if CACHE_L2X0
595 select ARCH_HAS_CPUFREQ
597 This enables support for NVIDIA Tegra based systems (Tegra APX,
598 Tegra 6xx and Tegra 2 series).
601 bool "Philips Nexperia PNX4008 Mobile"
604 select ARCH_USES_GETTIMEOFFSET
606 This enables support for Philips PNX4008 mobile platform.
609 bool "PXA2xx/PXA3xx-based"
612 select ARCH_HAS_CPUFREQ
615 select ARCH_REQUIRE_GPIOLIB
616 select GENERIC_CLOCKEVENTS
617 select HAVE_SCHED_CLOCK
622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
627 select GENERIC_CLOCKEVENTS
628 select ARCH_REQUIRE_GPIOLIB
631 Support for Qualcomm MSM/QSD based systems. This runs on the
632 apps processor of the MSM/QSD and depends on a shared memory
633 interface to the modem processor which runs the baseband
634 stack and controls some vital subsystems
635 (clock and power control, etc).
638 bool "Renesas SH-Mobile / R-Mobile"
641 select GENERIC_CLOCKEVENTS
644 select MULTI_IRQ_HANDLER
646 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
653 select ARCH_MAY_HAVE_PC_FDC
654 select HAVE_PATA_PLATFORM
657 select ARCH_SPARSEMEM_ENABLE
658 select ARCH_USES_GETTIMEOFFSET
660 On the Acorn Risc-PC, Linux can support the internal IDE disk and
661 CD-ROM interface, serial and parallel port, and the floppy drive.
668 select ARCH_SPARSEMEM_ENABLE
670 select ARCH_HAS_CPUFREQ
672 select GENERIC_CLOCKEVENTS
674 select HAVE_SCHED_CLOCK
676 select ARCH_REQUIRE_GPIOLIB
678 Support for StrongARM 11x0 based boards.
681 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
683 select ARCH_HAS_CPUFREQ
685 select ARCH_USES_GETTIMEOFFSET
686 select HAVE_S3C2410_I2C if I2C
688 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
689 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
690 the Samsung SMDK2410 development board (and derivatives).
692 Note, the S3C2416 and the S3C2450 are so close that they even share
693 the same SoC ID code. This means that there is no separate machine
694 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
697 bool "Samsung S3C64XX"
703 select ARCH_USES_GETTIMEOFFSET
704 select ARCH_HAS_CPUFREQ
705 select ARCH_REQUIRE_GPIOLIB
706 select SAMSUNG_CLKSRC
707 select SAMSUNG_IRQ_VIC_TIMER
708 select SAMSUNG_IRQ_UART
709 select S3C_GPIO_TRACK
710 select S3C_GPIO_PULL_UPDOWN
711 select S3C_GPIO_CFG_S3C24XX
712 select S3C_GPIO_CFG_S3C64XX
714 select USB_ARCH_HAS_OHCI
715 select SAMSUNG_GPIOLIB_4BIT
716 select HAVE_S3C2410_I2C if I2C
717 select HAVE_S3C2410_WATCHDOG if WATCHDOG
719 Samsung S3C64XX series based systems
722 bool "Samsung S5P6440 S5P6450"
726 select HAVE_S3C2410_WATCHDOG if WATCHDOG
727 select GENERIC_CLOCKEVENTS
728 select HAVE_SCHED_CLOCK
729 select HAVE_S3C2410_I2C if I2C
730 select HAVE_S3C_RTC if RTC_CLASS
732 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
736 bool "Samsung S5PC100"
740 select ARM_L1_CACHE_SHIFT_6
741 select ARCH_USES_GETTIMEOFFSET
742 select HAVE_S3C2410_I2C if I2C
743 select HAVE_S3C_RTC if RTC_CLASS
744 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 Samsung S5PC100 series based systems
749 bool "Samsung S5PV210/S5PC110"
751 select ARCH_SPARSEMEM_ENABLE
754 select ARM_L1_CACHE_SHIFT_6
755 select ARCH_HAS_CPUFREQ
756 select GENERIC_CLOCKEVENTS
757 select HAVE_SCHED_CLOCK
758 select HAVE_S3C2410_I2C if I2C
759 select HAVE_S3C_RTC if RTC_CLASS
760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
762 Samsung S5PV210/S5PC110 series based systems
765 bool "Samsung EXYNOS4"
767 select ARCH_SPARSEMEM_ENABLE
770 select ARCH_HAS_CPUFREQ
771 select GENERIC_CLOCKEVENTS
772 select HAVE_S3C_RTC if RTC_CLASS
773 select HAVE_S3C2410_I2C if I2C
774 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 Samsung EXYNOS4 series based systems
785 select ARCH_USES_GETTIMEOFFSET
787 Support for the StrongARM based Digital DNARD machine, also known
788 as "Shark" (<http://www.shark-linux.de/shark.html>).
791 bool "Telechips TCC ARM926-based systems"
796 select GENERIC_CLOCKEVENTS
798 Support for Telechips TCC ARM926-based systems.
801 bool "ST-Ericsson U300 Series"
805 select HAVE_SCHED_CLOCK
809 select GENERIC_CLOCKEVENTS
813 Support for ST-Ericsson U300 series mobile platforms.
816 bool "ST-Ericsson U8500 Series"
819 select GENERIC_CLOCKEVENTS
821 select ARCH_REQUIRE_GPIOLIB
822 select ARCH_HAS_CPUFREQ
824 Support for ST-Ericsson's Ux500 architecture
827 bool "STMicroelectronics Nomadik"
832 select GENERIC_CLOCKEVENTS
833 select ARCH_REQUIRE_GPIOLIB
835 Support for the Nomadik platform by ST-Ericsson
839 select GENERIC_CLOCKEVENTS
840 select ARCH_REQUIRE_GPIOLIB
844 select GENERIC_ALLOCATOR
845 select GENERIC_IRQ_CHIP
846 select ARCH_HAS_HOLES_MEMORYMODEL
848 Support for TI's DaVinci platform.
853 select ARCH_REQUIRE_GPIOLIB
854 select ARCH_HAS_CPUFREQ
855 select GENERIC_CLOCKEVENTS
856 select HAVE_SCHED_CLOCK
857 select ARCH_HAS_HOLES_MEMORYMODEL
859 Support for TI's OMAP platform (OMAP1/2/3/4).
862 bool "Rockchip Soc Rk29"
867 select HAVE_SCHED_CLOCK
868 select ARCH_HAS_CPUFREQ
870 select GENERIC_CLOCKEVENTS
871 select ARCH_REQUIRE_GPIOLIB
876 select ARM_L1_CACHE_SHIFT_6
878 Support for Rockchip RK29 soc.
883 select ARCH_REQUIRE_GPIOLIB
886 select GENERIC_CLOCKEVENTS
889 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
892 bool "VIA/WonderMedia 85xx"
895 select ARCH_HAS_CPUFREQ
896 select GENERIC_CLOCKEVENTS
897 select ARCH_REQUIRE_GPIOLIB
900 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
904 # This is sorted alphabetically by mach-* pathname. However, plat-*
905 # Kconfigs may be included either alphabetically (according to the
906 # plat- suffix) or along side the corresponding mach-* source.
908 source "arch/arm/mach-at91/Kconfig"
910 source "arch/arm/mach-bcmring/Kconfig"
912 source "arch/arm/mach-clps711x/Kconfig"
914 source "arch/arm/mach-cns3xxx/Kconfig"
916 source "arch/arm/mach-davinci/Kconfig"
918 source "arch/arm/mach-dove/Kconfig"
920 source "arch/arm/mach-ep93xx/Kconfig"
922 source "arch/arm/mach-footbridge/Kconfig"
924 source "arch/arm/mach-gemini/Kconfig"
926 source "arch/arm/mach-h720x/Kconfig"
928 source "arch/arm/mach-integrator/Kconfig"
930 source "arch/arm/mach-iop32x/Kconfig"
932 source "arch/arm/mach-iop33x/Kconfig"
934 source "arch/arm/mach-iop13xx/Kconfig"
936 source "arch/arm/mach-ixp4xx/Kconfig"
938 source "arch/arm/mach-ixp2000/Kconfig"
940 source "arch/arm/mach-ixp23xx/Kconfig"
942 source "arch/arm/mach-kirkwood/Kconfig"
944 source "arch/arm/mach-ks8695/Kconfig"
946 source "arch/arm/mach-loki/Kconfig"
948 source "arch/arm/mach-lpc32xx/Kconfig"
950 source "arch/arm/mach-msm/Kconfig"
952 source "arch/arm/mach-mv78xx0/Kconfig"
954 source "arch/arm/plat-mxc/Kconfig"
956 source "arch/arm/mach-mxs/Kconfig"
958 source "arch/arm/mach-netx/Kconfig"
960 source "arch/arm/mach-nomadik/Kconfig"
961 source "arch/arm/plat-nomadik/Kconfig"
963 source "arch/arm/mach-nuc93x/Kconfig"
965 source "arch/arm/plat-omap/Kconfig"
967 source "arch/arm/mach-omap1/Kconfig"
969 source "arch/arm/mach-omap2/Kconfig"
971 source "arch/arm/mach-orion5x/Kconfig"
973 source "arch/arm/mach-pxa/Kconfig"
974 source "arch/arm/plat-pxa/Kconfig"
976 source "arch/arm/mach-mmp/Kconfig"
978 source "arch/arm/mach-realview/Kconfig"
980 source "arch/arm/mach-rk29/Kconfig"
982 source "arch/arm/mach-sa1100/Kconfig"
984 source "arch/arm/plat-samsung/Kconfig"
985 source "arch/arm/plat-s3c24xx/Kconfig"
986 source "arch/arm/plat-s5p/Kconfig"
988 source "arch/arm/plat-spear/Kconfig"
990 source "arch/arm/plat-tcc/Kconfig"
993 source "arch/arm/mach-s3c2400/Kconfig"
994 source "arch/arm/mach-s3c2410/Kconfig"
995 source "arch/arm/mach-s3c2412/Kconfig"
996 source "arch/arm/mach-s3c2416/Kconfig"
997 source "arch/arm/mach-s3c2440/Kconfig"
998 source "arch/arm/mach-s3c2443/Kconfig"
1002 source "arch/arm/mach-s3c64xx/Kconfig"
1005 source "arch/arm/mach-s5p64x0/Kconfig"
1007 source "arch/arm/mach-s5pc100/Kconfig"
1009 source "arch/arm/mach-s5pv210/Kconfig"
1011 source "arch/arm/mach-exynos4/Kconfig"
1013 source "arch/arm/mach-shmobile/Kconfig"
1015 source "arch/arm/mach-tegra/Kconfig"
1017 source "arch/arm/mach-u300/Kconfig"
1019 source "arch/arm/mach-ux500/Kconfig"
1021 source "arch/arm/mach-versatile/Kconfig"
1023 source "arch/arm/mach-vexpress/Kconfig"
1024 source "arch/arm/plat-versatile/Kconfig"
1026 source "arch/arm/mach-vt8500/Kconfig"
1028 source "arch/arm/mach-w90x900/Kconfig"
1030 # Definitions to make life easier
1036 select GENERIC_CLOCKEVENTS
1037 select HAVE_SCHED_CLOCK
1042 select GENERIC_IRQ_CHIP
1043 select HAVE_SCHED_CLOCK
1048 config PLAT_VERSATILE
1051 config ARM_TIMER_SP804
1055 source arch/arm/mm/Kconfig
1058 bool "Enable iWMMXt support"
1059 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1060 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1062 Enable support for iWMMXt context switching at run time if
1063 running on a CPU that supports it.
1065 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1068 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1072 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1073 (!ARCH_OMAP3 || OMAP3_EMU)
1077 config MULTI_IRQ_HANDLER
1080 Allow each machine to specify it's own IRQ handler at run time.
1083 source "arch/arm/Kconfig-nommu"
1086 config ARM_ERRATA_411920
1087 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1088 depends on CPU_V6 || CPU_V6K
1090 Invalidation of the Instruction Cache operation can
1091 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1092 It does not affect the MPCore. This option enables the ARM Ltd.
1093 recommended workaround.
1095 config ARM_ERRATA_430973
1096 bool "ARM errata: Stale prediction on replaced interworking branch"
1099 This option enables the workaround for the 430973 Cortex-A8
1100 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1101 interworking branch is replaced with another code sequence at the
1102 same virtual address, whether due to self-modifying code or virtual
1103 to physical address re-mapping, Cortex-A8 does not recover from the
1104 stale interworking branch prediction. This results in Cortex-A8
1105 executing the new code sequence in the incorrect ARM or Thumb state.
1106 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1107 and also flushes the branch target cache at every context switch.
1108 Note that setting specific bits in the ACTLR register may not be
1109 available in non-secure mode.
1111 config ARM_ERRATA_458693
1112 bool "ARM errata: Processor deadlock when a false hazard is created"
1115 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1116 erratum. For very specific sequences of memory operations, it is
1117 possible for a hazard condition intended for a cache line to instead
1118 be incorrectly associated with a different cache line. This false
1119 hazard might then cause a processor deadlock. The workaround enables
1120 the L1 caching of the NEON accesses and disables the PLD instruction
1121 in the ACTLR register. Note that setting specific bits in the ACTLR
1122 register may not be available in non-secure mode.
1124 config ARM_ERRATA_460075
1125 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1128 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1129 erratum. Any asynchronous access to the L2 cache may encounter a
1130 situation in which recent store transactions to the L2 cache are lost
1131 and overwritten with stale memory contents from external memory. The
1132 workaround disables the write-allocate mode for the L2 cache via the
1133 ACTLR register. Note that setting specific bits in the ACTLR register
1134 may not be available in non-secure mode.
1136 config ARM_ERRATA_742230
1137 bool "ARM errata: DMB operation may be faulty"
1138 depends on CPU_V7 && SMP
1140 This option enables the workaround for the 742230 Cortex-A9
1141 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1142 between two write operations may not ensure the correct visibility
1143 ordering of the two writes. This workaround sets a specific bit in
1144 the diagnostic register of the Cortex-A9 which causes the DMB
1145 instruction to behave as a DSB, ensuring the correct behaviour of
1148 config ARM_ERRATA_742231
1149 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1150 depends on CPU_V7 && SMP
1152 This option enables the workaround for the 742231 Cortex-A9
1153 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1154 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1155 accessing some data located in the same cache line, may get corrupted
1156 data due to bad handling of the address hazard when the line gets
1157 replaced from one of the CPUs at the same time as another CPU is
1158 accessing it. This workaround sets specific bits in the diagnostic
1159 register of the Cortex-A9 which reduces the linefill issuing
1160 capabilities of the processor.
1162 config PL310_ERRATA_588369
1163 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1164 depends on CACHE_L2X0
1166 The PL310 L2 cache controller implements three types of Clean &
1167 Invalidate maintenance operations: by Physical Address
1168 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1169 They are architecturally defined to behave as the execution of a
1170 clean operation followed immediately by an invalidate operation,
1171 both performing to the same memory location. This functionality
1172 is not correctly implemented in PL310 as clean lines are not
1173 invalidated as a result of these operations.
1175 config ARM_ERRATA_720789
1176 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1177 depends on CPU_V7 && SMP
1179 This option enables the workaround for the 720789 Cortex-A9 (prior to
1180 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1181 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1182 As a consequence of this erratum, some TLB entries which should be
1183 invalidated are not, resulting in an incoherency in the system page
1184 tables. The workaround changes the TLB flushing routines to invalidate
1185 entries regardless of the ASID.
1187 config PL310_ERRATA_727915
1188 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1189 depends on CACHE_L2X0
1191 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1192 operation (offset 0x7FC). This operation runs in background so that
1193 PL310 can handle normal accesses while it is in progress. Under very
1194 rare circumstances, due to this erratum, write data can be lost when
1195 PL310 treats a cacheable write transaction during a Clean &
1196 Invalidate by Way operation.
1198 config ARM_ERRATA_743622
1199 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1202 This option enables the workaround for the 743622 Cortex-A9
1203 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1204 optimisation in the Cortex-A9 Store Buffer may lead to data
1205 corruption. This workaround sets a specific bit in the diagnostic
1206 register of the Cortex-A9 which disables the Store Buffer
1207 optimisation, preventing the defect from occurring. This has no
1208 visible impact on the overall performance or power consumption of the
1211 config ARM_ERRATA_751472
1212 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1213 depends on CPU_V7 && SMP
1215 This option enables the workaround for the 751472 Cortex-A9 (prior
1216 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1217 completion of a following broadcasted operation if the second
1218 operation is received by a CPU before the ICIALLUIS has completed,
1219 potentially leading to corrupted entries in the cache or TLB.
1221 config ARM_ERRATA_753970
1222 bool "ARM errata: cache sync operation may be faulty"
1223 depends on CACHE_PL310
1225 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1227 Under some condition the effect of cache sync operation on
1228 the store buffer still remains when the operation completes.
1229 This means that the store buffer is always asked to drain and
1230 this prevents it from merging any further writes. The workaround
1231 is to replace the normal offset of cache sync operation (0x730)
1232 by another offset targeting an unmapped PL310 register 0x740.
1233 This has the same effect as the cache sync operation: store buffer
1234 drain and waiting for all buffers empty.
1236 config ARM_ERRATA_754322
1237 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1240 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1241 r3p*) erratum. A speculative memory access may cause a page table walk
1242 which starts prior to an ASID switch but completes afterwards. This
1243 can populate the micro-TLB with a stale entry which may be hit with
1244 the new ASID. This workaround places two dsb instructions in the mm
1245 switching code so that no page table walks can cross the ASID switch.
1247 config ARM_ERRATA_754327
1248 bool "ARM errata: no automatic Store Buffer drain"
1249 depends on CPU_V7 && SMP
1251 This option enables the workaround for the 754327 Cortex-A9 (prior to
1252 r2p0) erratum. The Store Buffer does not have any automatic draining
1253 mechanism and therefore a livelock may occur if an external agent
1254 continuously polls a memory location waiting to observe an update.
1255 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1256 written polling loops from denying visibility of updates to memory.
1260 source "arch/arm/common/Kconfig"
1270 Find out whether you have ISA slots on your motherboard. ISA is the
1271 name of a bus system, i.e. the way the CPU talks to the other stuff
1272 inside your box. Other bus systems are PCI, EISA, MicroChannel
1273 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1274 newer boards don't support it. If you have ISA, say Y, otherwise N.
1276 # Select ISA DMA controller support
1281 # Select ISA DMA interface
1286 bool "PCI support" if MIGHT_HAVE_PCI
1288 Find out whether you have a PCI motherboard. PCI is the name of a
1289 bus system, i.e. the way the CPU talks to the other stuff inside
1290 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1291 VESA. If you have PCI, say Y, otherwise N.
1297 config PCI_NANOENGINE
1298 bool "BSE nanoEngine PCI support"
1299 depends on SA1100_NANOENGINE
1301 Enable PCI on the BSE nanoEngine board.
1306 # Select the host bridge type
1307 config PCI_HOST_VIA82C505
1309 depends on PCI && ARCH_SHARK
1312 config PCI_HOST_ITE8152
1314 depends on PCI && MACH_ARMCORE
1318 source "drivers/pci/Kconfig"
1320 source "drivers/pcmcia/Kconfig"
1322 config ARM_ERRATA_764369
1323 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1324 depends on CPU_V7 && SMP
1326 This option enables the workaround for erratum 764369
1327 affecting Cortex-A9 MPCore with two or more processors (all
1328 current revisions). Under certain timing circumstances, a data
1329 cache line maintenance operation by MVA targeting an Inner
1330 Shareable memory region may fail to proceed up to either the
1331 Point of Coherency or to the Point of Unification of the
1332 system. This workaround adds a DSB instruction before the
1333 relevant cache maintenance functions and sets a specific bit
1334 in the diagnostic control register of the SCU.
1338 menu "Kernel Features"
1340 source "kernel/time/Kconfig"
1343 bool "Symmetric Multi-Processing"
1344 depends on CPU_V6K || CPU_V7
1345 depends on GENERIC_CLOCKEVENTS
1346 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1347 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1348 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1349 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1350 select USE_GENERIC_SMP_HELPERS
1351 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1353 This enables support for systems with more than one CPU. If you have
1354 a system with only one CPU, like most personal computers, say N. If
1355 you have a system with more than one CPU, say Y.
1357 If you say N here, the kernel will run on single and multiprocessor
1358 machines, but will use only one CPU of a multiprocessor machine. If
1359 you say Y here, the kernel will run on many, but not all, single
1360 processor machines. On a single processor machine, the kernel will
1361 run faster if you say N here.
1363 See also <file:Documentation/i386/IO-APIC.txt>,
1364 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1365 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1367 If you don't know what to do here, say N.
1370 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1371 depends on EXPERIMENTAL
1372 depends on SMP && !XIP_KERNEL
1375 SMP kernels contain instructions which fail on non-SMP processors.
1376 Enabling this option allows the kernel to modify itself to make
1377 these instructions safe. Disabling it allows about 1K of space
1380 If you don't know what to do here, say Y.
1386 This option enables support for the ARM system coherency unit
1393 This options enables support for the ARM timer and watchdog unit
1396 prompt "Memory split"
1399 Select the desired split between kernel and user memory.
1401 If you are not absolutely sure what you are doing, leave this
1405 bool "3G/1G user/kernel split"
1407 bool "2G/2G user/kernel split"
1409 bool "1G/3G user/kernel split"
1414 default 0x40000000 if VMSPLIT_1G
1415 default 0x80000000 if VMSPLIT_2G
1419 int "Maximum number of CPUs (2-32)"
1425 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1426 depends on SMP && HOTPLUG && EXPERIMENTAL
1428 Say Y here to experiment with turning CPUs off and on. CPUs
1429 can be controlled through /sys/devices/system/cpu.
1432 bool "Use local timer interrupts"
1435 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1437 Enable support for local timers on SMP platforms, rather then the
1438 legacy IPI broadcast method. Local timers allows the system
1439 accounting to be spread across the timer interval, preventing a
1440 "thundering herd" at every timer tick.
1442 source kernel/Kconfig.preempt
1446 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1447 ARCH_S5PV210 || ARCH_EXYNOS4
1448 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1449 default AT91_TIMER_HZ if ARCH_AT91
1450 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1453 config THUMB2_KERNEL
1454 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1455 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1457 select ARM_ASM_UNIFIED
1459 By enabling this option, the kernel will be compiled in
1460 Thumb-2 mode. A compiler/assembler that understand the unified
1461 ARM-Thumb syntax is needed.
1465 config THUMB2_AVOID_R_ARM_THM_JUMP11
1466 bool "Work around buggy Thumb-2 short branch relocations in gas"
1467 depends on THUMB2_KERNEL && MODULES
1470 Various binutils versions can resolve Thumb-2 branches to
1471 locally-defined, preemptible global symbols as short-range "b.n"
1472 branch instructions.
1474 This is a problem, because there's no guarantee the final
1475 destination of the symbol, or any candidate locations for a
1476 trampoline, are within range of the branch. For this reason, the
1477 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1478 relocation in modules at all, and it makes little sense to add
1481 The symptom is that the kernel fails with an "unsupported
1482 relocation" error when loading some modules.
1484 Until fixed tools are available, passing
1485 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1486 code which hits this problem, at the cost of a bit of extra runtime
1487 stack usage in some cases.
1489 The problem is described in more detail at:
1490 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1492 Only Thumb-2 kernels are affected.
1494 Unless you are sure your tools don't have this problem, say Y.
1496 config ARM_ASM_UNIFIED
1500 bool "Use the ARM EABI to compile the kernel"
1502 This option allows for the kernel to be compiled using the latest
1503 ARM ABI (aka EABI). This is only useful if you are using a user
1504 space environment that is also compiled with EABI.
1506 Since there are major incompatibilities between the legacy ABI and
1507 EABI, especially with regard to structure member alignment, this
1508 option also changes the kernel syscall calling convention to
1509 disambiguate both ABIs and allow for backward compatibility support
1510 (selected with CONFIG_OABI_COMPAT).
1512 To use this you need GCC version 4.0.0 or later.
1515 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1516 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1519 This option preserves the old syscall interface along with the
1520 new (ARM EABI) one. It also provides a compatibility layer to
1521 intercept syscalls that have structure arguments which layout
1522 in memory differs between the legacy ABI and the new ARM EABI
1523 (only for non "thumb" binaries). This option adds a tiny
1524 overhead to all syscalls and produces a slightly larger kernel.
1525 If you know you'll be using only pure EABI user space then you
1526 can say N here. If this option is not selected and you attempt
1527 to execute a legacy ABI binary then the result will be
1528 UNPREDICTABLE (in fact it can be predicted that it won't work
1529 at all). If in doubt say Y.
1531 config ARCH_HAS_HOLES_MEMORYMODEL
1534 config ARCH_SPARSEMEM_ENABLE
1537 config ARCH_SPARSEMEM_DEFAULT
1538 def_bool ARCH_SPARSEMEM_ENABLE
1540 config ARCH_SELECT_MEMORY_MODEL
1541 def_bool ARCH_SPARSEMEM_ENABLE
1543 config HAVE_ARCH_PFN_VALID
1544 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1547 bool "High Memory Support"
1550 The address space of ARM processors is only 4 Gigabytes large
1551 and it has to accommodate user address space, kernel address
1552 space as well as some memory mapped IO. That means that, if you
1553 have a large amount of physical memory and/or IO, not all of the
1554 memory can be "permanently mapped" by the kernel. The physical
1555 memory that is not permanently mapped is called "high memory".
1557 Depending on the selected kernel/user memory split, minimum
1558 vmalloc space and actual amount of RAM, you may not need this
1559 option which should result in a slightly faster kernel.
1564 bool "Allocate 2nd-level pagetables from highmem"
1567 config HW_PERF_EVENTS
1568 bool "Enable hardware performance counter support for perf events"
1569 depends on PERF_EVENTS && CPU_HAS_PMU
1572 Enable hardware performance counter support for perf events. If
1573 disabled, perf events will use software events only.
1577 config FORCE_MAX_ZONEORDER
1578 int "Maximum zone order" if ARCH_SHMOBILE
1579 range 11 64 if ARCH_SHMOBILE
1580 default "9" if SA1111
1583 The kernel memory allocator divides physically contiguous memory
1584 blocks into "zones", where each zone is a power of two number of
1585 pages. This option selects the largest power of two that the kernel
1586 keeps in the memory allocator. If you need to allocate very large
1587 blocks of physically contiguous memory, then you may need to
1588 increase this value.
1590 This config option is actually maximum order plus one. For example,
1591 a value of 11 means that the largest free memory block is 2^10 pages.
1594 bool "Timer and CPU usage LEDs"
1595 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1596 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1597 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1598 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1599 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1600 ARCH_AT91 || ARCH_DAVINCI || \
1601 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1603 If you say Y here, the LEDs on your machine will be used
1604 to provide useful information about your current system status.
1606 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1607 be able to select which LEDs are active using the options below. If
1608 you are compiling a kernel for the EBSA-110 or the LART however, the
1609 red LED will simply flash regularly to indicate that the system is
1610 still functional. It is safe to say Y here if you have a CATS
1611 system, but the driver will do nothing.
1614 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1615 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1616 || MACH_OMAP_PERSEUS2
1618 depends on !GENERIC_CLOCKEVENTS
1619 default y if ARCH_EBSA110
1621 If you say Y here, one of the system LEDs (the green one on the
1622 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1623 will flash regularly to indicate that the system is still
1624 operational. This is mainly useful to kernel hackers who are
1625 debugging unstable kernels.
1627 The LART uses the same LED for both Timer LED and CPU usage LED
1628 functions. You may choose to use both, but the Timer LED function
1629 will overrule the CPU usage LED.
1632 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1634 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1635 || MACH_OMAP_PERSEUS2
1638 If you say Y here, the red LED will be used to give a good real
1639 time indication of CPU usage, by lighting whenever the idle task
1640 is not currently executing.
1642 The LART uses the same LED for both Timer LED and CPU usage LED
1643 functions. You may choose to use both, but the Timer LED function
1644 will overrule the CPU usage LED.
1646 config ALIGNMENT_TRAP
1648 depends on CPU_CP15_MMU
1649 default y if !ARCH_EBSA110
1650 select HAVE_PROC_CPU if PROC_FS
1652 ARM processors cannot fetch/store information which is not
1653 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1654 address divisible by 4. On 32-bit ARM processors, these non-aligned
1655 fetch/store instructions will be emulated in software if you say
1656 here, which has a severe performance impact. This is necessary for
1657 correct operation of some network protocols. With an IP-only
1658 configuration it is safe to say N, otherwise say Y.
1660 config UACCESS_WITH_MEMCPY
1661 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1662 depends on MMU && EXPERIMENTAL
1663 default y if CPU_FEROCEON
1665 Implement faster copy_to_user and clear_user methods for CPU
1666 cores where a 8-word STM instruction give significantly higher
1667 memory write throughput than a sequence of individual 32bit stores.
1669 A possible side effect is a slight increase in scheduling latency
1670 between threads sharing the same address space if they invoke
1671 such copy operations with large buffers.
1673 However, if the CPU data cache is using a write-allocate mode,
1674 this option is unlikely to provide any performance gain.
1678 prompt "Enable seccomp to safely compute untrusted bytecode"
1680 This kernel feature is useful for number crunching applications
1681 that may need to compute untrusted bytecode during their
1682 execution. By using pipes or other transports made available to
1683 the process as file descriptors supporting the read/write
1684 syscalls, it's possible to isolate those applications in
1685 their own address space using seccomp. Once seccomp is
1686 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1687 and the task is only allowed to execute a few safe syscalls
1688 defined by each seccomp mode.
1690 config CC_STACKPROTECTOR
1691 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1692 depends on EXPERIMENTAL
1694 This option turns on the -fstack-protector GCC feature. This
1695 feature puts, at the beginning of functions, a canary value on
1696 the stack just before the return address, and validates
1697 the value just before actually returning. Stack based buffer
1698 overflows (that need to overwrite this return address) now also
1699 overwrite the canary, which gets detected and the attack is then
1700 neutralized via a kernel panic.
1701 This feature requires gcc version 4.2 or above.
1703 config DEPRECATED_PARAM_STRUCT
1704 bool "Provide old way to pass kernel parameters"
1706 This was deprecated in 2001 and announced to live on for 5 years.
1707 Some old boot loaders still use this way.
1709 config ARM_FLUSH_CONSOLE_ON_RESTART
1710 bool "Force flush the console on restart"
1712 If the console is locked while the system is rebooted, the messages
1713 in the temporary logbuffer would not have propogated to all the
1714 console drivers. This option forces the console lock to be
1715 released if it failed to be acquired, which will cause all the
1716 pending messages to be flushed.
1723 bool "Flattened Device Tree support"
1725 select OF_EARLY_FLATTREE
1727 Include support for flattened device tree machine descriptions.
1729 # Compressed boot loader in ROM. Yes, we really want to ask about
1730 # TEXT and BSS so we preserve their values in the config files.
1731 config ZBOOT_ROM_TEXT
1732 hex "Compressed ROM boot loader base address"
1735 The physical address at which the ROM-able zImage is to be
1736 placed in the target. Platforms which normally make use of
1737 ROM-able zImage formats normally set this to a suitable
1738 value in their defconfig file.
1740 If ZBOOT_ROM is not enabled, this has no effect.
1742 config ZBOOT_ROM_BSS
1743 hex "Compressed ROM boot loader BSS address"
1746 The base address of an area of read/write memory in the target
1747 for the ROM-able zImage which must be available while the
1748 decompressor is running. It must be large enough to hold the
1749 entire decompressed kernel plus an additional 128 KiB.
1750 Platforms which normally make use of ROM-able zImage formats
1751 normally set this to a suitable value in their defconfig file.
1753 If ZBOOT_ROM is not enabled, this has no effect.
1756 bool "Compressed boot loader in ROM/flash"
1757 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1759 Say Y here if you intend to execute your compressed kernel image
1760 (zImage) directly from ROM or flash. If unsure, say N.
1762 config ZBOOT_ROM_MMCIF
1763 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1764 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1766 Say Y here to include experimental MMCIF loading code in the
1767 ROM-able zImage. With this enabled it is possible to write the
1768 the ROM-able zImage kernel image to an MMC card and boot the
1769 kernel straight from the reset vector. At reset the processor
1770 Mask ROM will load the first part of the the ROM-able zImage
1771 which in turn loads the rest the kernel image to RAM using the
1772 MMCIF hardware block.
1775 string "Default kernel command string"
1778 On some architectures (EBSA110 and CATS), there is currently no way
1779 for the boot loader to pass arguments to the kernel. For these
1780 architectures, you should supply some command-line options at build
1781 time by entering them here. As a minimum, you should specify the
1782 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1785 prompt "Kernel command line type" if CMDLINE != ""
1786 default CMDLINE_FROM_BOOTLOADER
1788 config CMDLINE_FROM_BOOTLOADER
1789 bool "Use bootloader kernel arguments if available"
1791 Uses the command-line options passed by the boot loader. If
1792 the boot loader doesn't provide any, the default kernel command
1793 string provided in CMDLINE will be used.
1795 config CMDLINE_EXTEND
1796 bool "Extend bootloader kernel arguments"
1798 The command-line arguments provided by the boot loader will be
1799 appended to the default kernel command string.
1801 config CMDLINE_FORCE
1802 bool "Always use the default kernel command string"
1804 Always use the default kernel command string, even if the boot
1805 loader passes other arguments to the kernel.
1806 This is useful if you cannot or don't want to change the
1807 command-line options your boot loader passes to the kernel.
1811 bool "Kernel Execute-In-Place from ROM"
1812 depends on !ZBOOT_ROM
1814 Execute-In-Place allows the kernel to run from non-volatile storage
1815 directly addressable by the CPU, such as NOR flash. This saves RAM
1816 space since the text section of the kernel is not loaded from flash
1817 to RAM. Read-write sections, such as the data section and stack,
1818 are still copied to RAM. The XIP kernel is not compressed since
1819 it has to run directly from flash, so it will take more space to
1820 store it. The flash address used to link the kernel object files,
1821 and for storing it, is configuration dependent. Therefore, if you
1822 say Y here, you must know the proper physical address where to
1823 store the kernel image depending on your own flash memory usage.
1825 Also note that the make target becomes "make xipImage" rather than
1826 "make zImage" or "make Image". The final kernel binary to put in
1827 ROM memory will be arch/arm/boot/xipImage.
1831 config XIP_PHYS_ADDR
1832 hex "XIP Kernel Physical Location"
1833 depends on XIP_KERNEL
1834 default "0x00080000"
1836 This is the physical address in your flash memory the kernel will
1837 be linked for and stored to. This address is dependent on your
1841 bool "Kexec system call (EXPERIMENTAL)"
1842 depends on EXPERIMENTAL
1844 kexec is a system call that implements the ability to shutdown your
1845 current kernel, and to start another kernel. It is like a reboot
1846 but it is independent of the system firmware. And like a reboot
1847 you can start any kernel with it, not just Linux.
1849 It is an ongoing process to be certain the hardware in a machine
1850 is properly shutdown, so do not be surprised if this code does not
1851 initially work for you. It may help to enable device hotplugging
1855 bool "Export atags in procfs"
1859 Should the atags used to boot the kernel be exported in an "atags"
1860 file in procfs. Useful with kexec.
1863 bool "Build kdump crash kernel (EXPERIMENTAL)"
1864 depends on EXPERIMENTAL
1866 Generate crash dump after being started by kexec. This should
1867 be normally only set in special crash dump kernels which are
1868 loaded in the main kernel with kexec-tools into a specially
1869 reserved region and then later executed after a crash by
1870 kdump/kexec. The crash dump kernel must be compiled to a
1871 memory address not used by the main kernel
1873 For more details see Documentation/kdump/kdump.txt
1875 config AUTO_ZRELADDR
1876 bool "Auto calculation of the decompressed kernel image address"
1877 depends on !ZBOOT_ROM && !ARCH_U300
1879 ZRELADDR is the physical address where the decompressed kernel
1880 image will be placed. If AUTO_ZRELADDR is selected, the address
1881 will be determined at run-time by masking the current IP with
1882 0xf8000000. This assumes the zImage being placed in the first 128MB
1883 from start of memory.
1887 menu "CPU Power Management"
1891 source "drivers/cpufreq/Kconfig"
1894 tristate "CPUfreq driver for i.MX CPUs"
1895 depends on ARCH_MXC && CPU_FREQ
1897 This enables the CPUfreq driver for i.MX CPUs.
1899 config CPU_FREQ_SA1100
1902 config CPU_FREQ_SA1110
1905 config CPU_FREQ_INTEGRATOR
1906 tristate "CPUfreq driver for ARM Integrator CPUs"
1907 depends on ARCH_INTEGRATOR && CPU_FREQ
1910 This enables the CPUfreq driver for ARM Integrator CPUs.
1912 For details, take a look at <file:Documentation/cpu-freq>.
1918 depends on CPU_FREQ && ARCH_PXA && PXA25x
1920 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1922 config CPU_FREQ_S3C64XX
1923 bool "CPUfreq support for Samsung S3C64XX CPUs"
1924 depends on CPU_FREQ && CPU_S3C6410
1929 Internal configuration node for common cpufreq on Samsung SoC
1931 config CPU_FREQ_S3C24XX
1932 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1933 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1936 This enables the CPUfreq driver for the Samsung S3C24XX family
1939 For details, take a look at <file:Documentation/cpu-freq>.
1943 config CPU_FREQ_S3C24XX_PLL
1944 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1945 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1947 Compile in support for changing the PLL frequency from the
1948 S3C24XX series CPUfreq driver. The PLL takes time to settle
1949 after a frequency change, so by default it is not enabled.
1951 This also means that the PLL tables for the selected CPU(s) will
1952 be built which may increase the size of the kernel image.
1954 config CPU_FREQ_S3C24XX_DEBUG
1955 bool "Debug CPUfreq Samsung driver core"
1956 depends on CPU_FREQ_S3C24XX
1958 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1960 config CPU_FREQ_S3C24XX_IODEBUG
1961 bool "Debug CPUfreq Samsung driver IO timing"
1962 depends on CPU_FREQ_S3C24XX
1964 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1966 config CPU_FREQ_S3C24XX_DEBUGFS
1967 bool "Export debugfs for CPUFreq"
1968 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1970 Export status information via debugfs.
1974 source "drivers/cpuidle/Kconfig"
1978 menu "Floating point emulation"
1980 comment "At least one emulation must be selected"
1983 bool "NWFPE math emulation"
1984 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1986 Say Y to include the NWFPE floating point emulator in the kernel.
1987 This is necessary to run most binaries. Linux does not currently
1988 support floating point hardware so you need to say Y here even if
1989 your machine has an FPA or floating point co-processor podule.
1991 You may say N here if you are going to load the Acorn FPEmulator
1992 early in the bootup.
1995 bool "Support extended precision"
1996 depends on FPE_NWFPE
1998 Say Y to include 80-bit support in the kernel floating-point
1999 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2000 Note that gcc does not generate 80-bit operations by default,
2001 so in most cases this option only enlarges the size of the
2002 floating point emulator without any good reason.
2004 You almost surely want to say N here.
2007 bool "FastFPE math emulation (EXPERIMENTAL)"
2008 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2010 Say Y here to include the FAST floating point emulator in the kernel.
2011 This is an experimental much faster emulator which now also has full
2012 precision for the mantissa. It does not support any exceptions.
2013 It is very simple, and approximately 3-6 times faster than NWFPE.
2015 It should be sufficient for most programs. It may be not suitable
2016 for scientific calculations, but you have to check this for yourself.
2017 If you do not feel you need a faster FP emulation you should better
2021 bool "VFP-format floating point maths"
2022 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2024 Say Y to include VFP support code in the kernel. This is needed
2025 if your hardware includes a VFP unit.
2027 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2028 release notes and additional status information.
2030 Say N if your target does not have VFP hardware.
2038 bool "Advanced SIMD (NEON) Extension support"
2039 depends on VFPv3 && CPU_V7
2041 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2046 menu "Userspace binary formats"
2048 source "fs/Kconfig.binfmt"
2051 tristate "RISC OS personality"
2054 Say Y here to include the kernel code necessary if you want to run
2055 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2056 experimental; if this sounds frightening, say N and sleep in peace.
2057 You can also say M here to compile this support as a module (which
2058 will be called arthur).
2062 menu "Power management options"
2064 source "kernel/power/Kconfig"
2066 config ARCH_SUSPEND_POSSIBLE
2067 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2068 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2069 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2074 source "net/Kconfig"
2076 source "drivers/Kconfig"
2080 source "arch/arm/Kconfig.debug"
2082 source "security/Kconfig"
2084 source "crypto/Kconfig"
2086 source "lib/Kconfig"