4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
48 select GENERIC_STRNCPY_FROM_USER
49 select GENERIC_STRNLEN_USER
50 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
52 The ARM series is a line of low-power-consumption RISC chip designs
53 licensed by ARM Ltd and targeted at embedded applications and
54 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
55 manufactured, but legacy ARM-based PC hardware remains popular in
56 Europe. There is an ARM Linux project with a web page at
57 <http://www.arm.linux.org.uk/>.
59 config ARM_HAS_SG_CHAIN
62 config NEED_SG_DMA_LENGTH
65 config ARM_DMA_USE_IOMMU
66 select NEED_SG_DMA_LENGTH
67 select ARM_HAS_SG_CHAIN
76 config SYS_SUPPORTS_APM_EMULATION
84 select GENERIC_ALLOCATOR
95 The Extended Industry Standard Architecture (EISA) bus was
96 developed as an open alternative to the IBM MicroChannel bus.
98 The EISA bus provided some of the features of the IBM MicroChannel
99 bus while maintaining backward compatibility with cards made for
100 the older ISA bus. The EISA bus saw limited use between 1988 and
101 1995 when it was made obsolete by the PCI bus.
103 Say Y here if you are building a kernel for an EISA-based machine.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config GENERIC_LOCKBREAK
130 depends on SMP && PREEMPT
132 config RWSEM_GENERIC_SPINLOCK
136 config RWSEM_XCHGADD_ALGORITHM
139 config ARCH_HAS_ILOG2_U32
142 config ARCH_HAS_ILOG2_U64
145 config ARCH_HAS_CPUFREQ
148 Internal node to signify that the ARCH has CPUFREQ support
149 and that the relevant menu configurations are displayed for
152 config GENERIC_HWEIGHT
156 config GENERIC_CALIBRATE_DELAY
160 config ARCH_MAY_HAVE_PC_FDC
166 config NEED_DMA_MAP_STATE
169 config ARCH_HAS_DMA_SET_COHERENT_MASK
172 config GENERIC_ISA_DMA
178 config NEED_RET_TO_USER
186 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
187 default DRAM_BASE if REMAP_VECTORS_TO_RAM
190 The base address of exception vectors.
192 config ARM_PATCH_PHYS_VIRT
193 bool "Patch physical to virtual translations at runtime" if EMBEDDED
195 depends on !XIP_KERNEL && MMU
196 depends on !ARCH_REALVIEW || !SPARSEMEM
198 Patch phys-to-virt and virt-to-phys translation functions at
199 boot and module load time according to the position of the
200 kernel in system memory.
202 This can only be used with non-XIP MMU kernels where the base
203 of physical memory is at a 16MB boundary.
205 Only disable this option if you know that you do not require
206 this feature (eg, building a kernel for a single machine) and
207 you need to shrink the kernel to the minimal size.
209 config NEED_MACH_IO_H
212 Select this when mach/io.h is required to provide special
213 definitions for this platform. The need for mach/io.h should
214 be avoided when possible.
216 config NEED_MACH_MEMORY_H
219 Select this when mach/memory.h is required to provide special
220 definitions for this platform. The need for mach/memory.h should
221 be avoided when possible.
224 hex "Physical address of main memory" if MMU
225 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 default DRAM_BASE if !MMU
228 Please provide the physical address corresponding to the
229 location of main memory in your system.
235 source "init/Kconfig"
237 source "kernel/Kconfig.freezer"
242 bool "MMU-based Paged Memory Management Support"
245 Select if you want MMU-based virtualised addressing space
246 support by paged memory management. If unsure, say 'Y'.
249 # The "ARM system type" choice list is ordered alphabetically by option
250 # text. Please add new entries in the option alphabetic order.
253 prompt "ARM system type"
254 default ARCH_VERSATILE
256 config ARCH_INTEGRATOR
257 bool "ARM Ltd. Integrator family"
259 select ARCH_HAS_CPUFREQ
261 select HAVE_MACH_CLKDEV
264 select GENERIC_CLOCKEVENTS
265 select PLAT_VERSATILE
266 select PLAT_VERSATILE_FPGA_IRQ
267 select NEED_MACH_IO_H
268 select NEED_MACH_MEMORY_H
270 select MULTI_IRQ_HANDLER
272 Support for ARM's Integrator platform.
275 bool "ARM Ltd. RealView family"
278 select HAVE_MACH_CLKDEV
280 select GENERIC_CLOCKEVENTS
281 select ARCH_WANT_OPTIONAL_GPIOLIB
282 select PLAT_VERSATILE
283 select PLAT_VERSATILE_CLCD
284 select ARM_TIMER_SP804
285 select GPIO_PL061 if GPIOLIB
286 select NEED_MACH_MEMORY_H
288 This enables support for ARM Ltd RealView boards.
290 config ARCH_VERSATILE
291 bool "ARM Ltd. Versatile family"
295 select HAVE_MACH_CLKDEV
297 select GENERIC_CLOCKEVENTS
298 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select NEED_MACH_IO_H if PCI
300 select PLAT_VERSATILE
301 select PLAT_VERSATILE_CLCD
302 select PLAT_VERSATILE_FPGA_IRQ
303 select ARM_TIMER_SP804
305 This enables support for ARM Ltd Versatile board.
308 bool "ARM Ltd. Versatile Express family"
309 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_TIMER_SP804
313 select HAVE_MACH_CLKDEV
314 select GENERIC_CLOCKEVENTS
316 select HAVE_PATA_PLATFORM
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
322 This enables support for the ARM Ltd Versatile Express boards.
326 select ARCH_REQUIRE_GPIOLIB
330 select NEED_MACH_IO_H if PCCARD
332 This enables support for systems based on Atmel
333 AT91RM9200 and AT91SAM9* processors.
336 bool "Broadcom BCMRING"
340 select ARM_TIMER_SP804
342 select GENERIC_CLOCKEVENTS
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 Support for Broadcom's BCMRing platform.
348 bool "Calxeda Highbank-based"
349 select ARCH_WANT_OPTIONAL_GPIOLIB
352 select ARM_TIMER_SP804
356 select GENERIC_CLOCKEVENTS
362 Support for the Calxeda Highbank SoC based boards.
365 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
367 select ARCH_USES_GETTIMEOFFSET
368 select NEED_MACH_MEMORY_H
370 Support for Cirrus Logic 711x/721x/731x based boards.
373 bool "Cavium Networks CNS3XXX family"
375 select GENERIC_CLOCKEVENTS
377 select MIGHT_HAVE_CACHE_L2X0
378 select MIGHT_HAVE_PCI
379 select PCI_DOMAINS if PCI
381 Support for Cavium Networks CNS3XXX platform.
384 bool "Cortina Systems Gemini"
386 select ARCH_REQUIRE_GPIOLIB
387 select ARCH_USES_GETTIMEOFFSET
389 Support for the Cortina Systems Gemini family SoCs
392 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
395 select GENERIC_CLOCKEVENTS
397 select GENERIC_IRQ_CHIP
398 select MIGHT_HAVE_CACHE_L2X0
404 Support for CSR SiRFSoC ARM Cortex A9 Platform
411 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_IO_H
413 select NEED_MACH_MEMORY_H
415 This is an evaluation board for the StrongARM processor available
416 from Digital. It has limited hardware on-board, including an
417 Ethernet interface, two PCMCIA sockets, two serial ports and a
426 select ARCH_REQUIRE_GPIOLIB
427 select ARCH_HAS_HOLES_MEMORYMODEL
428 select ARCH_USES_GETTIMEOFFSET
429 select NEED_MACH_MEMORY_H
431 This enables support for the Cirrus EP93xx series of CPUs.
433 config ARCH_FOOTBRIDGE
437 select GENERIC_CLOCKEVENTS
439 select NEED_MACH_IO_H
440 select NEED_MACH_MEMORY_H
442 Support for systems based on the DC21285 companion chip
443 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
446 bool "Freescale MXC/iMX-based"
447 select GENERIC_CLOCKEVENTS
448 select ARCH_REQUIRE_GPIOLIB
451 select GENERIC_IRQ_CHIP
452 select MULTI_IRQ_HANDLER
454 Support for Freescale MXC/iMX-based family of processors
457 bool "Freescale MXS-based"
458 select GENERIC_CLOCKEVENTS
459 select ARCH_REQUIRE_GPIOLIB
463 select HAVE_CLK_PREPARE
467 Support for Freescale MXS-based family of processors
470 bool "Hilscher NetX based"
474 select GENERIC_CLOCKEVENTS
476 This enables support for systems based on the Hilscher NetX Soc
479 bool "Hynix HMS720x-based"
482 select ARCH_USES_GETTIMEOFFSET
484 This enables support for systems based on the Hynix HMS720x
492 select ARCH_SUPPORTS_MSI
494 select NEED_MACH_IO_H
495 select NEED_MACH_MEMORY_H
496 select NEED_RET_TO_USER
498 Support for Intel's IOP13XX (XScale) family of processors.
504 select NEED_MACH_IO_H
505 select NEED_RET_TO_USER
508 select ARCH_REQUIRE_GPIOLIB
510 Support for Intel's 80219 and IOP32X (XScale) family of
517 select NEED_MACH_IO_H
518 select NEED_RET_TO_USER
521 select ARCH_REQUIRE_GPIOLIB
523 Support for Intel's IOP33X (XScale) family of processors.
528 select ARCH_HAS_DMA_SET_COHERENT_MASK
531 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
533 select MIGHT_HAVE_PCI
534 select NEED_MACH_IO_H
535 select DMABOUNCE if PCI
537 Support for Intel's IXP4XX (XScale) family of processors.
543 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
545 select NEED_MACH_IO_H
548 Support for the Marvell Dove SoC 88AP510
551 bool "Marvell Kirkwood"
554 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_CLOCKEVENTS
556 select NEED_MACH_IO_H
559 Support for the following Marvell Kirkwood series SoCs:
560 88F6180, 88F6192 and 88F6281.
566 select ARCH_REQUIRE_GPIOLIB
569 select USB_ARCH_HAS_OHCI
571 select GENERIC_CLOCKEVENTS
574 Support for the NXP LPC32XX family of processors
577 bool "Marvell MV78xx0"
580 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
582 select NEED_MACH_IO_H
585 Support for the following Marvell MV78xx0 series SoCs:
593 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
595 select NEED_MACH_IO_H
598 Support for the following Marvell Orion 5x series SoCs:
599 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
600 Orion-2 (5281), Orion-1-90 (6183).
603 bool "Marvell PXA168/910/MMP2"
605 select ARCH_REQUIRE_GPIOLIB
607 select GENERIC_CLOCKEVENTS
612 select GENERIC_ALLOCATOR
614 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
617 bool "Micrel/Kendin KS8695"
619 select ARCH_REQUIRE_GPIOLIB
620 select ARCH_USES_GETTIMEOFFSET
621 select NEED_MACH_MEMORY_H
623 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
624 System-on-Chip devices.
627 bool "Nuvoton W90X900 CPU"
629 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
634 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
635 At present, the w90x900 has been renamed nuc900, regarding
636 the ARM series product line, you can login the following
637 link address to know more.
639 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
640 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
646 select GENERIC_CLOCKEVENTS
650 select MIGHT_HAVE_CACHE_L2X0
651 select NEED_MACH_IO_H if PCI
652 select ARCH_HAS_CPUFREQ
654 This enables support for NVIDIA Tegra based systems (Tegra APX,
655 Tegra 6xx and Tegra 2 series).
657 config ARCH_PICOXCELL
658 bool "Picochip picoXcell"
659 select ARCH_REQUIRE_GPIOLIB
660 select ARM_PATCH_PHYS_VIRT
664 select GENERIC_CLOCKEVENTS
671 This enables support for systems based on the Picochip picoXcell
672 family of Femtocell devices. The picoxcell support requires device tree
676 bool "Philips Nexperia PNX4008 Mobile"
679 select ARCH_USES_GETTIMEOFFSET
681 This enables support for Philips PNX4008 mobile platform.
684 bool "PXA2xx/PXA3xx-based"
687 select ARCH_HAS_CPUFREQ
690 select ARCH_REQUIRE_GPIOLIB
691 select GENERIC_CLOCKEVENTS
696 select MULTI_IRQ_HANDLER
697 select ARM_CPU_SUSPEND if PM
700 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
705 select GENERIC_CLOCKEVENTS
706 select ARCH_REQUIRE_GPIOLIB
709 Support for Qualcomm MSM/QSD based systems. This runs on the
710 apps processor of the MSM/QSD and depends on a shared memory
711 interface to the modem processor which runs the baseband
712 stack and controls some vital subsystems
713 (clock and power control, etc).
716 bool "Renesas SH-Mobile / R-Mobile"
719 select HAVE_MACH_CLKDEV
721 select GENERIC_CLOCKEVENTS
722 select MIGHT_HAVE_CACHE_L2X0
725 select MULTI_IRQ_HANDLER
726 select PM_GENERIC_DOMAINS if PM
727 select NEED_MACH_MEMORY_H
729 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
735 select ARCH_MAY_HAVE_PC_FDC
736 select HAVE_PATA_PLATFORM
739 select ARCH_SPARSEMEM_ENABLE
740 select ARCH_USES_GETTIMEOFFSET
742 select NEED_MACH_IO_H
743 select NEED_MACH_MEMORY_H
745 On the Acorn Risc-PC, Linux can support the internal IDE disk and
746 CD-ROM interface, serial and parallel port, and the floppy drive.
753 select ARCH_SPARSEMEM_ENABLE
755 select ARCH_HAS_CPUFREQ
757 select GENERIC_CLOCKEVENTS
759 select ARCH_REQUIRE_GPIOLIB
761 select NEED_MACH_MEMORY_H
764 Support for StrongARM 11x0 based boards.
767 bool "Samsung S3C24XX SoCs"
769 select ARCH_HAS_CPUFREQ
772 select ARCH_USES_GETTIMEOFFSET
773 select HAVE_S3C2410_I2C if I2C
774 select HAVE_S3C_RTC if RTC_CLASS
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 select NEED_MACH_IO_H
778 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
779 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
780 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
781 Samsung SMDK2410 development board (and derivatives).
784 bool "Samsung S3C64XX"
792 select ARCH_USES_GETTIMEOFFSET
793 select ARCH_HAS_CPUFREQ
794 select ARCH_REQUIRE_GPIOLIB
795 select SAMSUNG_CLKSRC
796 select SAMSUNG_IRQ_VIC_TIMER
797 select S3C_GPIO_TRACK
799 select USB_ARCH_HAS_OHCI
800 select SAMSUNG_GPIOLIB_4BIT
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 Samsung S3C64XX series based systems
807 bool "Samsung S5P6440 S5P6450"
813 select HAVE_S3C2410_WATCHDOG if WATCHDOG
814 select GENERIC_CLOCKEVENTS
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C_RTC if RTC_CLASS
818 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
822 bool "Samsung S5PC100"
827 select ARCH_USES_GETTIMEOFFSET
828 select HAVE_S3C2410_I2C if I2C
829 select HAVE_S3C_RTC if RTC_CLASS
830 select HAVE_S3C2410_WATCHDOG if WATCHDOG
832 Samsung S5PC100 series based systems
835 bool "Samsung S5PV210/S5PC110"
837 select ARCH_SPARSEMEM_ENABLE
838 select ARCH_HAS_HOLES_MEMORYMODEL
843 select ARCH_HAS_CPUFREQ
844 select GENERIC_CLOCKEVENTS
845 select HAVE_S3C2410_I2C if I2C
846 select HAVE_S3C_RTC if RTC_CLASS
847 select HAVE_S3C2410_WATCHDOG if WATCHDOG
848 select NEED_MACH_MEMORY_H
850 Samsung S5PV210/S5PC110 series based systems
853 bool "SAMSUNG EXYNOS"
855 select ARCH_SPARSEMEM_ENABLE
856 select ARCH_HAS_HOLES_MEMORYMODEL
860 select ARCH_HAS_CPUFREQ
861 select GENERIC_CLOCKEVENTS
862 select HAVE_S3C_RTC if RTC_CLASS
863 select HAVE_S3C2410_I2C if I2C
864 select HAVE_S3C2410_WATCHDOG if WATCHDOG
865 select NEED_MACH_MEMORY_H
867 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
876 select ARCH_USES_GETTIMEOFFSET
877 select NEED_MACH_MEMORY_H
878 select NEED_MACH_IO_H
880 Support for the StrongARM based Digital DNARD machine, also known
881 as "Shark" (<http://www.shark-linux.de/shark.html>).
884 bool "ST-Ericsson U300 Series"
890 select ARM_PATCH_PHYS_VIRT
892 select GENERIC_CLOCKEVENTS
894 select HAVE_MACH_CLKDEV
896 select ARCH_REQUIRE_GPIOLIB
898 Support for ST-Ericsson U300 series mobile platforms.
901 bool "ST-Ericsson U8500 Series"
905 select GENERIC_CLOCKEVENTS
907 select ARCH_REQUIRE_GPIOLIB
908 select ARCH_HAS_CPUFREQ
910 select MIGHT_HAVE_CACHE_L2X0
912 Support for ST-Ericsson's Ux500 architecture
915 bool "STMicroelectronics Nomadik"
920 select GENERIC_CLOCKEVENTS
922 select MIGHT_HAVE_CACHE_L2X0
923 select ARCH_REQUIRE_GPIOLIB
925 Support for the Nomadik platform by ST-Ericsson
929 select GENERIC_CLOCKEVENTS
930 select ARCH_REQUIRE_GPIOLIB
934 select GENERIC_ALLOCATOR
935 select GENERIC_IRQ_CHIP
936 select ARCH_HAS_HOLES_MEMORYMODEL
938 Support for TI's DaVinci platform.
943 select ARCH_REQUIRE_GPIOLIB
944 select ARCH_HAS_CPUFREQ
946 select GENERIC_CLOCKEVENTS
947 select ARCH_HAS_HOLES_MEMORYMODEL
949 Support for TI's OMAP platform (OMAP1/2/3/4).
954 select ARCH_REQUIRE_GPIOLIB
958 select GENERIC_CLOCKEVENTS
961 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
964 bool "VIA/WonderMedia 85xx"
967 select ARCH_HAS_CPUFREQ
968 select GENERIC_CLOCKEVENTS
969 select ARCH_REQUIRE_GPIOLIB
972 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
975 bool "Xilinx Zynq ARM Cortex A9 Platform"
977 select GENERIC_CLOCKEVENTS
982 select MIGHT_HAVE_CACHE_L2X0
985 Support for Xilinx Zynq ARM Cortex A9 Platform
989 # This is sorted alphabetically by mach-* pathname. However, plat-*
990 # Kconfigs may be included either alphabetically (according to the
991 # plat- suffix) or along side the corresponding mach-* source.
993 source "arch/arm/mach-at91/Kconfig"
995 source "arch/arm/mach-bcmring/Kconfig"
997 source "arch/arm/mach-clps711x/Kconfig"
999 source "arch/arm/mach-cns3xxx/Kconfig"
1001 source "arch/arm/mach-davinci/Kconfig"
1003 source "arch/arm/mach-dove/Kconfig"
1005 source "arch/arm/mach-ep93xx/Kconfig"
1007 source "arch/arm/mach-footbridge/Kconfig"
1009 source "arch/arm/mach-gemini/Kconfig"
1011 source "arch/arm/mach-h720x/Kconfig"
1013 source "arch/arm/mach-integrator/Kconfig"
1015 source "arch/arm/mach-iop32x/Kconfig"
1017 source "arch/arm/mach-iop33x/Kconfig"
1019 source "arch/arm/mach-iop13xx/Kconfig"
1021 source "arch/arm/mach-ixp4xx/Kconfig"
1023 source "arch/arm/mach-kirkwood/Kconfig"
1025 source "arch/arm/mach-ks8695/Kconfig"
1027 source "arch/arm/mach-lpc32xx/Kconfig"
1029 source "arch/arm/mach-msm/Kconfig"
1031 source "arch/arm/mach-mv78xx0/Kconfig"
1033 source "arch/arm/plat-mxc/Kconfig"
1035 source "arch/arm/mach-mxs/Kconfig"
1037 source "arch/arm/mach-netx/Kconfig"
1039 source "arch/arm/mach-nomadik/Kconfig"
1040 source "arch/arm/plat-nomadik/Kconfig"
1042 source "arch/arm/plat-omap/Kconfig"
1044 source "arch/arm/mach-omap1/Kconfig"
1046 source "arch/arm/mach-omap2/Kconfig"
1048 source "arch/arm/mach-orion5x/Kconfig"
1050 source "arch/arm/mach-pxa/Kconfig"
1051 source "arch/arm/plat-pxa/Kconfig"
1053 source "arch/arm/mach-mmp/Kconfig"
1055 source "arch/arm/mach-realview/Kconfig"
1057 source "arch/arm/mach-sa1100/Kconfig"
1059 source "arch/arm/plat-samsung/Kconfig"
1060 source "arch/arm/plat-s3c24xx/Kconfig"
1062 source "arch/arm/plat-spear/Kconfig"
1064 source "arch/arm/mach-s3c24xx/Kconfig"
1066 source "arch/arm/mach-s3c2412/Kconfig"
1067 source "arch/arm/mach-s3c2440/Kconfig"
1071 source "arch/arm/mach-s3c64xx/Kconfig"
1074 source "arch/arm/mach-s5p64x0/Kconfig"
1076 source "arch/arm/mach-s5pc100/Kconfig"
1078 source "arch/arm/mach-s5pv210/Kconfig"
1080 source "arch/arm/mach-exynos/Kconfig"
1082 source "arch/arm/mach-shmobile/Kconfig"
1084 source "arch/arm/mach-tegra/Kconfig"
1086 source "arch/arm/mach-u300/Kconfig"
1088 source "arch/arm/mach-ux500/Kconfig"
1090 source "arch/arm/mach-versatile/Kconfig"
1092 source "arch/arm/mach-vexpress/Kconfig"
1093 source "arch/arm/plat-versatile/Kconfig"
1095 source "arch/arm/mach-vt8500/Kconfig"
1097 source "arch/arm/mach-w90x900/Kconfig"
1099 # Definitions to make life easier
1105 select GENERIC_CLOCKEVENTS
1110 select GENERIC_IRQ_CHIP
1116 config PLAT_VERSATILE
1119 config ARM_TIMER_SP804
1122 select HAVE_SCHED_CLOCK
1124 source arch/arm/mm/Kconfig
1128 default 16 if ARCH_EP93XX
1132 bool "Enable iWMMXt support"
1133 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1134 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1136 Enable support for iWMMXt context switching at run time if
1137 running on a CPU that supports it.
1141 depends on CPU_XSCALE
1145 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1146 (!ARCH_OMAP3 || OMAP3_EMU)
1150 config MULTI_IRQ_HANDLER
1153 Allow each machine to specify it's own IRQ handler at run time.
1156 source "arch/arm/Kconfig-nommu"
1159 config ARM_ERRATA_326103
1160 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1163 Executing a SWP instruction to read-only memory does not set bit 11
1164 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1165 treat the access as a read, preventing a COW from occurring and
1166 causing the faulting task to livelock.
1168 config ARM_ERRATA_411920
1169 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1170 depends on CPU_V6 || CPU_V6K
1172 Invalidation of the Instruction Cache operation can
1173 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1174 It does not affect the MPCore. This option enables the ARM Ltd.
1175 recommended workaround.
1177 config ARM_ERRATA_430973
1178 bool "ARM errata: Stale prediction on replaced interworking branch"
1181 This option enables the workaround for the 430973 Cortex-A8
1182 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1183 interworking branch is replaced with another code sequence at the
1184 same virtual address, whether due to self-modifying code or virtual
1185 to physical address re-mapping, Cortex-A8 does not recover from the
1186 stale interworking branch prediction. This results in Cortex-A8
1187 executing the new code sequence in the incorrect ARM or Thumb state.
1188 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1189 and also flushes the branch target cache at every context switch.
1190 Note that setting specific bits in the ACTLR register may not be
1191 available in non-secure mode.
1193 config ARM_ERRATA_458693
1194 bool "ARM errata: Processor deadlock when a false hazard is created"
1197 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1198 erratum. For very specific sequences of memory operations, it is
1199 possible for a hazard condition intended for a cache line to instead
1200 be incorrectly associated with a different cache line. This false
1201 hazard might then cause a processor deadlock. The workaround enables
1202 the L1 caching of the NEON accesses and disables the PLD instruction
1203 in the ACTLR register. Note that setting specific bits in the ACTLR
1204 register may not be available in non-secure mode.
1206 config ARM_ERRATA_460075
1207 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1210 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1211 erratum. Any asynchronous access to the L2 cache may encounter a
1212 situation in which recent store transactions to the L2 cache are lost
1213 and overwritten with stale memory contents from external memory. The
1214 workaround disables the write-allocate mode for the L2 cache via the
1215 ACTLR register. Note that setting specific bits in the ACTLR register
1216 may not be available in non-secure mode.
1218 config ARM_ERRATA_742230
1219 bool "ARM errata: DMB operation may be faulty"
1220 depends on CPU_V7 && SMP
1222 This option enables the workaround for the 742230 Cortex-A9
1223 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1224 between two write operations may not ensure the correct visibility
1225 ordering of the two writes. This workaround sets a specific bit in
1226 the diagnostic register of the Cortex-A9 which causes the DMB
1227 instruction to behave as a DSB, ensuring the correct behaviour of
1230 config ARM_ERRATA_742231
1231 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1232 depends on CPU_V7 && SMP
1234 This option enables the workaround for the 742231 Cortex-A9
1235 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1236 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1237 accessing some data located in the same cache line, may get corrupted
1238 data due to bad handling of the address hazard when the line gets
1239 replaced from one of the CPUs at the same time as another CPU is
1240 accessing it. This workaround sets specific bits in the diagnostic
1241 register of the Cortex-A9 which reduces the linefill issuing
1242 capabilities of the processor.
1244 config PL310_ERRATA_588369
1245 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1246 depends on CACHE_L2X0
1248 The PL310 L2 cache controller implements three types of Clean &
1249 Invalidate maintenance operations: by Physical Address
1250 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1251 They are architecturally defined to behave as the execution of a
1252 clean operation followed immediately by an invalidate operation,
1253 both performing to the same memory location. This functionality
1254 is not correctly implemented in PL310 as clean lines are not
1255 invalidated as a result of these operations.
1257 config ARM_ERRATA_720789
1258 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1261 This option enables the workaround for the 720789 Cortex-A9 (prior to
1262 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1263 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1264 As a consequence of this erratum, some TLB entries which should be
1265 invalidated are not, resulting in an incoherency in the system page
1266 tables. The workaround changes the TLB flushing routines to invalidate
1267 entries regardless of the ASID.
1269 config PL310_ERRATA_727915
1270 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1271 depends on CACHE_L2X0
1273 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1274 operation (offset 0x7FC). This operation runs in background so that
1275 PL310 can handle normal accesses while it is in progress. Under very
1276 rare circumstances, due to this erratum, write data can be lost when
1277 PL310 treats a cacheable write transaction during a Clean &
1278 Invalidate by Way operation.
1280 config ARM_ERRATA_743622
1281 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1284 This option enables the workaround for the 743622 Cortex-A9
1285 (r2p*) erratum. Under very rare conditions, a faulty
1286 optimisation in the Cortex-A9 Store Buffer may lead to data
1287 corruption. This workaround sets a specific bit in the diagnostic
1288 register of the Cortex-A9 which disables the Store Buffer
1289 optimisation, preventing the defect from occurring. This has no
1290 visible impact on the overall performance or power consumption of the
1293 config ARM_ERRATA_751472
1294 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1297 This option enables the workaround for the 751472 Cortex-A9 (prior
1298 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1299 completion of a following broadcasted operation if the second
1300 operation is received by a CPU before the ICIALLUIS has completed,
1301 potentially leading to corrupted entries in the cache or TLB.
1303 config PL310_ERRATA_753970
1304 bool "PL310 errata: cache sync operation may be faulty"
1305 depends on CACHE_PL310
1307 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1309 Under some condition the effect of cache sync operation on
1310 the store buffer still remains when the operation completes.
1311 This means that the store buffer is always asked to drain and
1312 this prevents it from merging any further writes. The workaround
1313 is to replace the normal offset of cache sync operation (0x730)
1314 by another offset targeting an unmapped PL310 register 0x740.
1315 This has the same effect as the cache sync operation: store buffer
1316 drain and waiting for all buffers empty.
1318 config ARM_ERRATA_754322
1319 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1322 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1323 r3p*) erratum. A speculative memory access may cause a page table walk
1324 which starts prior to an ASID switch but completes afterwards. This
1325 can populate the micro-TLB with a stale entry which may be hit with
1326 the new ASID. This workaround places two dsb instructions in the mm
1327 switching code so that no page table walks can cross the ASID switch.
1329 config ARM_ERRATA_754327
1330 bool "ARM errata: no automatic Store Buffer drain"
1331 depends on CPU_V7 && SMP
1333 This option enables the workaround for the 754327 Cortex-A9 (prior to
1334 r2p0) erratum. The Store Buffer does not have any automatic draining
1335 mechanism and therefore a livelock may occur if an external agent
1336 continuously polls a memory location waiting to observe an update.
1337 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1338 written polling loops from denying visibility of updates to memory.
1340 config ARM_ERRATA_364296
1341 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1342 depends on CPU_V6 && !SMP
1344 This options enables the workaround for the 364296 ARM1136
1345 r0p2 erratum (possible cache data corruption with
1346 hit-under-miss enabled). It sets the undocumented bit 31 in
1347 the auxiliary control register and the FI bit in the control
1348 register, thus disabling hit-under-miss without putting the
1349 processor into full low interrupt latency mode. ARM11MPCore
1352 config ARM_ERRATA_764369
1353 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1354 depends on CPU_V7 && SMP
1356 This option enables the workaround for erratum 764369
1357 affecting Cortex-A9 MPCore with two or more processors (all
1358 current revisions). Under certain timing circumstances, a data
1359 cache line maintenance operation by MVA targeting an Inner
1360 Shareable memory region may fail to proceed up to either the
1361 Point of Coherency or to the Point of Unification of the
1362 system. This workaround adds a DSB instruction before the
1363 relevant cache maintenance functions and sets a specific bit
1364 in the diagnostic control register of the SCU.
1366 config PL310_ERRATA_769419
1367 bool "PL310 errata: no automatic Store Buffer drain"
1368 depends on CACHE_L2X0
1370 On revisions of the PL310 prior to r3p2, the Store Buffer does
1371 not automatically drain. This can cause normal, non-cacheable
1372 writes to be retained when the memory system is idle, leading
1373 to suboptimal I/O performance for drivers using coherent DMA.
1374 This option adds a write barrier to the cpu_idle loop so that,
1375 on systems with an outer cache, the store buffer is drained
1380 source "arch/arm/common/Kconfig"
1390 Find out whether you have ISA slots on your motherboard. ISA is the
1391 name of a bus system, i.e. the way the CPU talks to the other stuff
1392 inside your box. Other bus systems are PCI, EISA, MicroChannel
1393 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1394 newer boards don't support it. If you have ISA, say Y, otherwise N.
1396 # Select ISA DMA controller support
1401 # Select ISA DMA interface
1406 bool "PCI support" if MIGHT_HAVE_PCI
1408 Find out whether you have a PCI motherboard. PCI is the name of a
1409 bus system, i.e. the way the CPU talks to the other stuff inside
1410 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1411 VESA. If you have PCI, say Y, otherwise N.
1417 config PCI_NANOENGINE
1418 bool "BSE nanoEngine PCI support"
1419 depends on SA1100_NANOENGINE
1421 Enable PCI on the BSE nanoEngine board.
1426 # Select the host bridge type
1427 config PCI_HOST_VIA82C505
1429 depends on PCI && ARCH_SHARK
1432 config PCI_HOST_ITE8152
1434 depends on PCI && MACH_ARMCORE
1438 source "drivers/pci/Kconfig"
1440 source "drivers/pcmcia/Kconfig"
1444 menu "Kernel Features"
1449 This option should be selected by machines which have an SMP-
1452 The only effect of this option is to make the SMP-related
1453 options available to the user for configuration.
1456 bool "Symmetric Multi-Processing"
1457 depends on CPU_V6K || CPU_V7
1458 depends on GENERIC_CLOCKEVENTS
1461 select USE_GENERIC_SMP_HELPERS
1462 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1464 This enables support for systems with more than one CPU. If you have
1465 a system with only one CPU, like most personal computers, say N. If
1466 you have a system with more than one CPU, say Y.
1468 If you say N here, the kernel will run on single and multiprocessor
1469 machines, but will use only one CPU of a multiprocessor machine. If
1470 you say Y here, the kernel will run on many, but not all, single
1471 processor machines. On a single processor machine, the kernel will
1472 run faster if you say N here.
1474 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1475 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1476 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1478 If you don't know what to do here, say N.
1481 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1482 depends on EXPERIMENTAL
1483 depends on SMP && !XIP_KERNEL
1486 SMP kernels contain instructions which fail on non-SMP processors.
1487 Enabling this option allows the kernel to modify itself to make
1488 these instructions safe. Disabling it allows about 1K of space
1491 If you don't know what to do here, say Y.
1493 config ARM_CPU_TOPOLOGY
1494 bool "Support cpu topology definition"
1495 depends on SMP && CPU_V7
1498 Support ARM cpu topology definition. The MPIDR register defines
1499 affinity between processors which is then used to describe the cpu
1500 topology of an ARM System.
1503 bool "Multi-core scheduler support"
1504 depends on ARM_CPU_TOPOLOGY
1506 Multi-core scheduler support improves the CPU scheduler's decision
1507 making when dealing with multi-core CPU chips at a cost of slightly
1508 increased overhead in some places. If unsure say N here.
1511 bool "SMT scheduler support"
1512 depends on ARM_CPU_TOPOLOGY
1514 Improves the CPU scheduler's decision making when dealing with
1515 MultiThreading at a cost of slightly increased overhead in some
1516 places. If unsure say N here.
1521 This option enables support for the ARM system coherency unit
1523 config ARM_ARCH_TIMER
1524 bool "Architected timer support"
1527 This option enables support for the ARM architected timer
1533 This options enables support for the ARM timer and watchdog unit
1536 prompt "Memory split"
1539 Select the desired split between kernel and user memory.
1541 If you are not absolutely sure what you are doing, leave this
1545 bool "3G/1G user/kernel split"
1547 bool "2G/2G user/kernel split"
1549 bool "1G/3G user/kernel split"
1554 default 0x40000000 if VMSPLIT_1G
1555 default 0x80000000 if VMSPLIT_2G
1559 int "Maximum number of CPUs (2-32)"
1565 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1566 depends on SMP && HOTPLUG && EXPERIMENTAL
1568 Say Y here to experiment with turning CPUs off and on. CPUs
1569 can be controlled through /sys/devices/system/cpu.
1572 bool "Use local timer interrupts"
1575 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1577 Enable support for local timers on SMP platforms, rather then the
1578 legacy IPI broadcast method. Local timers allows the system
1579 accounting to be spread across the timer interval, preventing a
1580 "thundering herd" at every timer tick.
1584 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1585 default 355 if ARCH_U8500
1586 default 264 if MACH_H4700
1589 Maximum number of GPIOs in the system.
1591 If unsure, leave the default value.
1593 source kernel/Kconfig.preempt
1597 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1598 ARCH_S5PV210 || ARCH_EXYNOS4
1599 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1600 default AT91_TIMER_HZ if ARCH_AT91
1601 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1604 config THUMB2_KERNEL
1605 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1606 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1608 select ARM_ASM_UNIFIED
1611 By enabling this option, the kernel will be compiled in
1612 Thumb-2 mode. A compiler/assembler that understand the unified
1613 ARM-Thumb syntax is needed.
1617 config THUMB2_AVOID_R_ARM_THM_JUMP11
1618 bool "Work around buggy Thumb-2 short branch relocations in gas"
1619 depends on THUMB2_KERNEL && MODULES
1622 Various binutils versions can resolve Thumb-2 branches to
1623 locally-defined, preemptible global symbols as short-range "b.n"
1624 branch instructions.
1626 This is a problem, because there's no guarantee the final
1627 destination of the symbol, or any candidate locations for a
1628 trampoline, are within range of the branch. For this reason, the
1629 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1630 relocation in modules at all, and it makes little sense to add
1633 The symptom is that the kernel fails with an "unsupported
1634 relocation" error when loading some modules.
1636 Until fixed tools are available, passing
1637 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1638 code which hits this problem, at the cost of a bit of extra runtime
1639 stack usage in some cases.
1641 The problem is described in more detail at:
1642 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1644 Only Thumb-2 kernels are affected.
1646 Unless you are sure your tools don't have this problem, say Y.
1648 config ARM_ASM_UNIFIED
1652 bool "Use the ARM EABI to compile the kernel"
1654 This option allows for the kernel to be compiled using the latest
1655 ARM ABI (aka EABI). This is only useful if you are using a user
1656 space environment that is also compiled with EABI.
1658 Since there are major incompatibilities between the legacy ABI and
1659 EABI, especially with regard to structure member alignment, this
1660 option also changes the kernel syscall calling convention to
1661 disambiguate both ABIs and allow for backward compatibility support
1662 (selected with CONFIG_OABI_COMPAT).
1664 To use this you need GCC version 4.0.0 or later.
1667 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1668 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1671 This option preserves the old syscall interface along with the
1672 new (ARM EABI) one. It also provides a compatibility layer to
1673 intercept syscalls that have structure arguments which layout
1674 in memory differs between the legacy ABI and the new ARM EABI
1675 (only for non "thumb" binaries). This option adds a tiny
1676 overhead to all syscalls and produces a slightly larger kernel.
1677 If you know you'll be using only pure EABI user space then you
1678 can say N here. If this option is not selected and you attempt
1679 to execute a legacy ABI binary then the result will be
1680 UNPREDICTABLE (in fact it can be predicted that it won't work
1681 at all). If in doubt say Y.
1683 config ARCH_HAS_HOLES_MEMORYMODEL
1686 config ARCH_SPARSEMEM_ENABLE
1689 config ARCH_SPARSEMEM_DEFAULT
1690 def_bool ARCH_SPARSEMEM_ENABLE
1692 config ARCH_SELECT_MEMORY_MODEL
1693 def_bool ARCH_SPARSEMEM_ENABLE
1695 config HAVE_ARCH_PFN_VALID
1696 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1699 bool "High Memory Support"
1702 The address space of ARM processors is only 4 Gigabytes large
1703 and it has to accommodate user address space, kernel address
1704 space as well as some memory mapped IO. That means that, if you
1705 have a large amount of physical memory and/or IO, not all of the
1706 memory can be "permanently mapped" by the kernel. The physical
1707 memory that is not permanently mapped is called "high memory".
1709 Depending on the selected kernel/user memory split, minimum
1710 vmalloc space and actual amount of RAM, you may not need this
1711 option which should result in a slightly faster kernel.
1716 bool "Allocate 2nd-level pagetables from highmem"
1719 config HW_PERF_EVENTS
1720 bool "Enable hardware performance counter support for perf events"
1721 depends on PERF_EVENTS && CPU_HAS_PMU
1724 Enable hardware performance counter support for perf events. If
1725 disabled, perf events will use software events only.
1729 config FORCE_MAX_ZONEORDER
1730 int "Maximum zone order" if ARCH_SHMOBILE
1731 range 11 64 if ARCH_SHMOBILE
1732 default "9" if SA1111
1735 The kernel memory allocator divides physically contiguous memory
1736 blocks into "zones", where each zone is a power of two number of
1737 pages. This option selects the largest power of two that the kernel
1738 keeps in the memory allocator. If you need to allocate very large
1739 blocks of physically contiguous memory, then you may need to
1740 increase this value.
1742 This config option is actually maximum order plus one. For example,
1743 a value of 11 means that the largest free memory block is 2^10 pages.
1746 bool "Timer and CPU usage LEDs"
1747 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1748 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1749 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1750 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1751 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1752 ARCH_AT91 || ARCH_DAVINCI || \
1753 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1755 If you say Y here, the LEDs on your machine will be used
1756 to provide useful information about your current system status.
1758 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1759 be able to select which LEDs are active using the options below. If
1760 you are compiling a kernel for the EBSA-110 or the LART however, the
1761 red LED will simply flash regularly to indicate that the system is
1762 still functional. It is safe to say Y here if you have a CATS
1763 system, but the driver will do nothing.
1766 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1767 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1768 || MACH_OMAP_PERSEUS2
1770 depends on !GENERIC_CLOCKEVENTS
1771 default y if ARCH_EBSA110
1773 If you say Y here, one of the system LEDs (the green one on the
1774 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1775 will flash regularly to indicate that the system is still
1776 operational. This is mainly useful to kernel hackers who are
1777 debugging unstable kernels.
1779 The LART uses the same LED for both Timer LED and CPU usage LED
1780 functions. You may choose to use both, but the Timer LED function
1781 will overrule the CPU usage LED.
1784 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1786 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1787 || MACH_OMAP_PERSEUS2
1790 If you say Y here, the red LED will be used to give a good real
1791 time indication of CPU usage, by lighting whenever the idle task
1792 is not currently executing.
1794 The LART uses the same LED for both Timer LED and CPU usage LED
1795 functions. You may choose to use both, but the Timer LED function
1796 will overrule the CPU usage LED.
1798 config ALIGNMENT_TRAP
1800 depends on CPU_CP15_MMU
1801 default y if !ARCH_EBSA110
1802 select HAVE_PROC_CPU if PROC_FS
1804 ARM processors cannot fetch/store information which is not
1805 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1806 address divisible by 4. On 32-bit ARM processors, these non-aligned
1807 fetch/store instructions will be emulated in software if you say
1808 here, which has a severe performance impact. This is necessary for
1809 correct operation of some network protocols. With an IP-only
1810 configuration it is safe to say N, otherwise say Y.
1812 config UACCESS_WITH_MEMCPY
1813 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1814 depends on MMU && EXPERIMENTAL
1815 default y if CPU_FEROCEON
1817 Implement faster copy_to_user and clear_user methods for CPU
1818 cores where a 8-word STM instruction give significantly higher
1819 memory write throughput than a sequence of individual 32bit stores.
1821 A possible side effect is a slight increase in scheduling latency
1822 between threads sharing the same address space if they invoke
1823 such copy operations with large buffers.
1825 However, if the CPU data cache is using a write-allocate mode,
1826 this option is unlikely to provide any performance gain.
1830 prompt "Enable seccomp to safely compute untrusted bytecode"
1832 This kernel feature is useful for number crunching applications
1833 that may need to compute untrusted bytecode during their
1834 execution. By using pipes or other transports made available to
1835 the process as file descriptors supporting the read/write
1836 syscalls, it's possible to isolate those applications in
1837 their own address space using seccomp. Once seccomp is
1838 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1839 and the task is only allowed to execute a few safe syscalls
1840 defined by each seccomp mode.
1842 config CC_STACKPROTECTOR
1843 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1844 depends on EXPERIMENTAL
1846 This option turns on the -fstack-protector GCC feature. This
1847 feature puts, at the beginning of functions, a canary value on
1848 the stack just before the return address, and validates
1849 the value just before actually returning. Stack based buffer
1850 overflows (that need to overwrite this return address) now also
1851 overwrite the canary, which gets detected and the attack is then
1852 neutralized via a kernel panic.
1853 This feature requires gcc version 4.2 or above.
1855 config DEPRECATED_PARAM_STRUCT
1856 bool "Provide old way to pass kernel parameters"
1858 This was deprecated in 2001 and announced to live on for 5 years.
1859 Some old boot loaders still use this way.
1866 bool "Flattened Device Tree support"
1868 select OF_EARLY_FLATTREE
1871 Include support for flattened device tree machine descriptions.
1873 # Compressed boot loader in ROM. Yes, we really want to ask about
1874 # TEXT and BSS so we preserve their values in the config files.
1875 config ZBOOT_ROM_TEXT
1876 hex "Compressed ROM boot loader base address"
1879 The physical address at which the ROM-able zImage is to be
1880 placed in the target. Platforms which normally make use of
1881 ROM-able zImage formats normally set this to a suitable
1882 value in their defconfig file.
1884 If ZBOOT_ROM is not enabled, this has no effect.
1886 config ZBOOT_ROM_BSS
1887 hex "Compressed ROM boot loader BSS address"
1890 The base address of an area of read/write memory in the target
1891 for the ROM-able zImage which must be available while the
1892 decompressor is running. It must be large enough to hold the
1893 entire decompressed kernel plus an additional 128 KiB.
1894 Platforms which normally make use of ROM-able zImage formats
1895 normally set this to a suitable value in their defconfig file.
1897 If ZBOOT_ROM is not enabled, this has no effect.
1900 bool "Compressed boot loader in ROM/flash"
1901 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1903 Say Y here if you intend to execute your compressed kernel image
1904 (zImage) directly from ROM or flash. If unsure, say N.
1907 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1908 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1909 default ZBOOT_ROM_NONE
1911 Include experimental SD/MMC loading code in the ROM-able zImage.
1912 With this enabled it is possible to write the ROM-able zImage
1913 kernel image to an MMC or SD card and boot the kernel straight
1914 from the reset vector. At reset the processor Mask ROM will load
1915 the first part of the ROM-able zImage which in turn loads the
1916 rest the kernel image to RAM.
1918 config ZBOOT_ROM_NONE
1919 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1921 Do not load image from SD or MMC
1923 config ZBOOT_ROM_MMCIF
1924 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1926 Load image from MMCIF hardware block.
1928 config ZBOOT_ROM_SH_MOBILE_SDHI
1929 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1931 Load image from SDHI hardware block
1935 config ARM_APPENDED_DTB
1936 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1937 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1939 With this option, the boot code will look for a device tree binary
1940 (DTB) appended to zImage
1941 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1943 This is meant as a backward compatibility convenience for those
1944 systems with a bootloader that can't be upgraded to accommodate
1945 the documented boot protocol using a device tree.
1947 Beware that there is very little in terms of protection against
1948 this option being confused by leftover garbage in memory that might
1949 look like a DTB header after a reboot if no actual DTB is appended
1950 to zImage. Do not leave this option active in a production kernel
1951 if you don't intend to always append a DTB. Proper passing of the
1952 location into r2 of a bootloader provided DTB is always preferable
1955 config ARM_ATAG_DTB_COMPAT
1956 bool "Supplement the appended DTB with traditional ATAG information"
1957 depends on ARM_APPENDED_DTB
1959 Some old bootloaders can't be updated to a DTB capable one, yet
1960 they provide ATAGs with memory configuration, the ramdisk address,
1961 the kernel cmdline string, etc. Such information is dynamically
1962 provided by the bootloader and can't always be stored in a static
1963 DTB. To allow a device tree enabled kernel to be used with such
1964 bootloaders, this option allows zImage to extract the information
1965 from the ATAG list and store it at run time into the appended DTB.
1968 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1969 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1971 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1972 bool "Use bootloader kernel arguments if available"
1974 Uses the command-line options passed by the boot loader instead of
1975 the device tree bootargs property. If the boot loader doesn't provide
1976 any, the device tree bootargs property will be used.
1978 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1979 bool "Extend with bootloader kernel arguments"
1981 The command-line arguments provided by the boot loader will be
1982 appended to the the device tree bootargs property.
1987 string "Default kernel command string"
1990 On some architectures (EBSA110 and CATS), there is currently no way
1991 for the boot loader to pass arguments to the kernel. For these
1992 architectures, you should supply some command-line options at build
1993 time by entering them here. As a minimum, you should specify the
1994 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1997 prompt "Kernel command line type" if CMDLINE != ""
1998 default CMDLINE_FROM_BOOTLOADER
2000 config CMDLINE_FROM_BOOTLOADER
2001 bool "Use bootloader kernel arguments if available"
2003 Uses the command-line options passed by the boot loader. If
2004 the boot loader doesn't provide any, the default kernel command
2005 string provided in CMDLINE will be used.
2007 config CMDLINE_EXTEND
2008 bool "Extend bootloader kernel arguments"
2010 The command-line arguments provided by the boot loader will be
2011 appended to the default kernel command string.
2013 config CMDLINE_FORCE
2014 bool "Always use the default kernel command string"
2016 Always use the default kernel command string, even if the boot
2017 loader passes other arguments to the kernel.
2018 This is useful if you cannot or don't want to change the
2019 command-line options your boot loader passes to the kernel.
2023 bool "Kernel Execute-In-Place from ROM"
2024 depends on !ZBOOT_ROM && !ARM_LPAE
2026 Execute-In-Place allows the kernel to run from non-volatile storage
2027 directly addressable by the CPU, such as NOR flash. This saves RAM
2028 space since the text section of the kernel is not loaded from flash
2029 to RAM. Read-write sections, such as the data section and stack,
2030 are still copied to RAM. The XIP kernel is not compressed since
2031 it has to run directly from flash, so it will take more space to
2032 store it. The flash address used to link the kernel object files,
2033 and for storing it, is configuration dependent. Therefore, if you
2034 say Y here, you must know the proper physical address where to
2035 store the kernel image depending on your own flash memory usage.
2037 Also note that the make target becomes "make xipImage" rather than
2038 "make zImage" or "make Image". The final kernel binary to put in
2039 ROM memory will be arch/arm/boot/xipImage.
2043 config XIP_PHYS_ADDR
2044 hex "XIP Kernel Physical Location"
2045 depends on XIP_KERNEL
2046 default "0x00080000"
2048 This is the physical address in your flash memory the kernel will
2049 be linked for and stored to. This address is dependent on your
2053 bool "Kexec system call (EXPERIMENTAL)"
2054 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2056 kexec is a system call that implements the ability to shutdown your
2057 current kernel, and to start another kernel. It is like a reboot
2058 but it is independent of the system firmware. And like a reboot
2059 you can start any kernel with it, not just Linux.
2061 It is an ongoing process to be certain the hardware in a machine
2062 is properly shutdown, so do not be surprised if this code does not
2063 initially work for you. It may help to enable device hotplugging
2067 bool "Export atags in procfs"
2071 Should the atags used to boot the kernel be exported in an "atags"
2072 file in procfs. Useful with kexec.
2075 bool "Build kdump crash kernel (EXPERIMENTAL)"
2076 depends on EXPERIMENTAL
2078 Generate crash dump after being started by kexec. This should
2079 be normally only set in special crash dump kernels which are
2080 loaded in the main kernel with kexec-tools into a specially
2081 reserved region and then later executed after a crash by
2082 kdump/kexec. The crash dump kernel must be compiled to a
2083 memory address not used by the main kernel
2085 For more details see Documentation/kdump/kdump.txt
2087 config AUTO_ZRELADDR
2088 bool "Auto calculation of the decompressed kernel image address"
2089 depends on !ZBOOT_ROM && !ARCH_U300
2091 ZRELADDR is the physical address where the decompressed kernel
2092 image will be placed. If AUTO_ZRELADDR is selected, the address
2093 will be determined at run-time by masking the current IP with
2094 0xf8000000. This assumes the zImage being placed in the first 128MB
2095 from start of memory.
2099 menu "CPU Power Management"
2103 source "drivers/cpufreq/Kconfig"
2106 tristate "CPUfreq driver for i.MX CPUs"
2107 depends on ARCH_MXC && CPU_FREQ
2109 This enables the CPUfreq driver for i.MX CPUs.
2111 config CPU_FREQ_SA1100
2114 config CPU_FREQ_SA1110
2117 config CPU_FREQ_INTEGRATOR
2118 tristate "CPUfreq driver for ARM Integrator CPUs"
2119 depends on ARCH_INTEGRATOR && CPU_FREQ
2122 This enables the CPUfreq driver for ARM Integrator CPUs.
2124 For details, take a look at <file:Documentation/cpu-freq>.
2130 depends on CPU_FREQ && ARCH_PXA && PXA25x
2132 select CPU_FREQ_TABLE
2133 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2138 Internal configuration node for common cpufreq on Samsung SoC
2140 config CPU_FREQ_S3C24XX
2141 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2142 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2145 This enables the CPUfreq driver for the Samsung S3C24XX family
2148 For details, take a look at <file:Documentation/cpu-freq>.
2152 config CPU_FREQ_S3C24XX_PLL
2153 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2154 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2156 Compile in support for changing the PLL frequency from the
2157 S3C24XX series CPUfreq driver. The PLL takes time to settle
2158 after a frequency change, so by default it is not enabled.
2160 This also means that the PLL tables for the selected CPU(s) will
2161 be built which may increase the size of the kernel image.
2163 config CPU_FREQ_S3C24XX_DEBUG
2164 bool "Debug CPUfreq Samsung driver core"
2165 depends on CPU_FREQ_S3C24XX
2167 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2169 config CPU_FREQ_S3C24XX_IODEBUG
2170 bool "Debug CPUfreq Samsung driver IO timing"
2171 depends on CPU_FREQ_S3C24XX
2173 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2175 config CPU_FREQ_S3C24XX_DEBUGFS
2176 bool "Export debugfs for CPUFreq"
2177 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2179 Export status information via debugfs.
2183 source "drivers/cpuidle/Kconfig"
2187 menu "Floating point emulation"
2189 comment "At least one emulation must be selected"
2192 bool "NWFPE math emulation"
2193 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2195 Say Y to include the NWFPE floating point emulator in the kernel.
2196 This is necessary to run most binaries. Linux does not currently
2197 support floating point hardware so you need to say Y here even if
2198 your machine has an FPA or floating point co-processor podule.
2200 You may say N here if you are going to load the Acorn FPEmulator
2201 early in the bootup.
2204 bool "Support extended precision"
2205 depends on FPE_NWFPE
2207 Say Y to include 80-bit support in the kernel floating-point
2208 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2209 Note that gcc does not generate 80-bit operations by default,
2210 so in most cases this option only enlarges the size of the
2211 floating point emulator without any good reason.
2213 You almost surely want to say N here.
2216 bool "FastFPE math emulation (EXPERIMENTAL)"
2217 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2219 Say Y here to include the FAST floating point emulator in the kernel.
2220 This is an experimental much faster emulator which now also has full
2221 precision for the mantissa. It does not support any exceptions.
2222 It is very simple, and approximately 3-6 times faster than NWFPE.
2224 It should be sufficient for most programs. It may be not suitable
2225 for scientific calculations, but you have to check this for yourself.
2226 If you do not feel you need a faster FP emulation you should better
2230 bool "VFP-format floating point maths"
2231 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2233 Say Y to include VFP support code in the kernel. This is needed
2234 if your hardware includes a VFP unit.
2236 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2237 release notes and additional status information.
2239 Say N if your target does not have VFP hardware.
2247 bool "Advanced SIMD (NEON) Extension support"
2248 depends on VFPv3 && CPU_V7
2250 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2255 menu "Userspace binary formats"
2257 source "fs/Kconfig.binfmt"
2260 tristate "RISC OS personality"
2263 Say Y here to include the kernel code necessary if you want to run
2264 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2265 experimental; if this sounds frightening, say N and sleep in peace.
2266 You can also say M here to compile this support as a module (which
2267 will be called arthur).
2271 menu "Power management options"
2273 source "kernel/power/Kconfig"
2275 config ARCH_SUSPEND_POSSIBLE
2276 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2277 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2278 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2281 config ARM_CPU_SUSPEND
2286 source "net/Kconfig"
2288 source "drivers/Kconfig"
2292 source "arch/arm/Kconfig.debug"
2294 source "security/Kconfig"
2296 source "crypto/Kconfig"
2298 source "lib/Kconfig"