4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
18 select GENERIC_ALLOCATOR
19 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
20 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
21 select GENERIC_IDLE_POLL_SETUP
22 select GENERIC_IRQ_PROBE
23 select GENERIC_IRQ_SHOW
24 select GENERIC_IRQ_SHOW_LEVEL
25 select GENERIC_PCI_IOMAP
26 select GENERIC_SCHED_CLOCK
27 select GENERIC_SMP_IDLE_THREAD
28 select GENERIC_STRNCPY_FROM_USER
29 select GENERIC_STRNLEN_USER
30 select HANDLE_DOMAIN_IRQ
31 select HARDIRQS_SW_RESEND
32 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
33 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
34 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
36 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_TRACEHOOK
39 select HAVE_CC_STACKPROTECTOR
40 select HAVE_CONTEXT_TRACKING
41 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK
43 select HAVE_DMA_API_DEBUG
45 select HAVE_DMA_CONTIGUOUS if MMU
46 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
47 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
48 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
49 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
50 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
51 select HAVE_GENERIC_DMA_COHERENT
52 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
53 select HAVE_IDE if PCI || ISA || PCMCIA
54 select HAVE_IRQ_TIME_ACCOUNTING
55 select HAVE_KERNEL_GZIP
56 select HAVE_KERNEL_LZ4
57 select HAVE_KERNEL_LZMA
58 select HAVE_KERNEL_LZO
60 select HAVE_KPROBES if !XIP_KERNEL
61 select HAVE_KRETPROBES if (HAVE_KPROBES)
63 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
64 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
65 select HAVE_OPTPROBES if !THUMB2_KERNEL
66 select HAVE_PERF_EVENTS
68 select HAVE_PERF_USER_STACK_DUMP
69 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
70 select HAVE_REGS_AND_STACK_ACCESS_API
71 select HAVE_SYSCALL_TRACEPOINTS
73 select HAVE_VIRT_CPU_ACCOUNTING_GEN
74 select IRQ_FORCED_THREADING
75 select MODULES_USE_ELF_REL
78 select OLD_SIGSUSPEND3
79 select PERF_USE_VMALLOC
81 select SYS_SUPPORTS_APM_EMULATION
82 # Above selects are sorted alphabetically; please add new ones
83 # according to that. Thanks.
85 The ARM series is a line of low-power-consumption RISC chip designs
86 licensed by ARM Ltd and targeted at embedded applications and
87 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
88 manufactured, but legacy ARM-based PC hardware remains popular in
89 Europe. There is an ARM Linux project with a web page at
90 <http://www.arm.linux.org.uk/>.
92 config ARM_HAS_SG_CHAIN
93 select ARCH_HAS_SG_CHAIN
96 config NEED_SG_DMA_LENGTH
99 config ARM_DMA_USE_IOMMU
101 select ARM_HAS_SG_CHAIN
102 select NEED_SG_DMA_LENGTH
106 config ARM_DMA_IOMMU_ALIGNMENT
107 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
111 DMA mapping framework by default aligns all buffers to the smallest
112 PAGE_SIZE order which is greater than or equal to the requested buffer
113 size. This works well for buffers up to a few hundreds kilobytes, but
114 for larger buffers it just a waste of address space. Drivers which has
115 relatively small addressing window (like 64Mib) might run out of
116 virtual space with just a few allocations.
118 With this parameter you can specify the maximum PAGE_SIZE order for
119 DMA IOMMU buffers. Larger buffers will be aligned only to this
120 specified order. The order is expressed as a power of two multiplied
125 config MIGHT_HAVE_PCI
128 config SYS_SUPPORTS_APM_EMULATION
133 select GENERIC_ALLOCATOR
144 The Extended Industry Standard Architecture (EISA) bus was
145 developed as an open alternative to the IBM MicroChannel bus.
147 The EISA bus provided some of the features of the IBM MicroChannel
148 bus while maintaining backward compatibility with cards made for
149 the older ISA bus. The EISA bus saw limited use between 1988 and
150 1995 when it was made obsolete by the PCI bus.
152 Say Y here if you are building a kernel for an EISA-based machine.
159 config STACKTRACE_SUPPORT
163 config HAVE_LATENCYTOP_SUPPORT
168 config LOCKDEP_SUPPORT
172 config TRACE_IRQFLAGS_SUPPORT
176 config RWSEM_XCHGADD_ALGORITHM
180 config ARCH_HAS_ILOG2_U32
183 config ARCH_HAS_ILOG2_U64
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_SUPPORTS_UPROBES
209 config ARCH_HAS_DMA_SET_COHERENT_MASK
212 config GENERIC_ISA_DMA
218 config NEED_RET_TO_USER
226 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
227 default DRAM_BASE if REMAP_VECTORS_TO_RAM
230 The base address of exception vectors. This must be two pages
233 config ARM_PATCH_PHYS_VIRT
234 bool "Patch physical to virtual translations at runtime" if EMBEDDED
236 depends on !XIP_KERNEL && MMU
237 depends on !ARCH_REALVIEW || !SPARSEMEM
239 Patch phys-to-virt and virt-to-phys translation functions at
240 boot and module load time according to the position of the
241 kernel in system memory.
243 This can only be used with non-XIP MMU kernels where the base
244 of physical memory is at a 16MB boundary.
246 Only disable this option if you know that you do not require
247 this feature (eg, building a kernel for a single machine) and
248 you need to shrink the kernel to the minimal size.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT
267 default DRAM_BASE if !MMU
268 default 0x00000000 if ARCH_EBSA110 || \
269 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
274 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
275 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
276 default 0x20000000 if ARCH_S5PV210
277 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
278 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
279 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
280 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
281 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 config PGTABLE_LEVELS
292 default 3 if ARM_LPAE
295 source "init/Kconfig"
297 source "kernel/Kconfig.freezer"
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
306 support by paged memory management. If unsure, say 'Y'.
309 # The "ARM system type" choice list is ordered alphabetically by option
310 # text. Please add new entries in the option alphabetic order.
313 prompt "ARM system type"
314 default ARCH_VERSATILE if !MMU
315 default ARCH_MULTIPLATFORM if MMU
317 config ARCH_MULTIPLATFORM
318 bool "Allow multiple platforms to be selected"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_HAS_SG_CHAIN
322 select ARM_PATCH_PHYS_VIRT
326 select GENERIC_CLOCKEVENTS
327 select MIGHT_HAVE_PCI
328 select MULTI_IRQ_HANDLER
332 config ARM_SINGLE_ARMV7M
333 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
340 select GENERIC_CLOCKEVENTS
346 bool "ARM Ltd. RealView family"
347 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select ARM_TIMER_SP804
351 select COMMON_CLK_VERSATILE
352 select GENERIC_CLOCKEVENTS
353 select GPIO_PL061 if GPIOLIB
355 select NEED_MACH_MEMORY_H
356 select PLAT_VERSATILE
357 select PLAT_VERSATILE_SCHED_CLOCK
359 This enables support for ARM Ltd RealView boards.
361 config ARCH_VERSATILE
362 bool "ARM Ltd. Versatile family"
363 select ARCH_WANT_OPTIONAL_GPIOLIB
365 select ARM_TIMER_SP804
368 select GENERIC_CLOCKEVENTS
369 select HAVE_MACH_CLKDEV
371 select PLAT_VERSATILE
372 select PLAT_VERSATILE_CLOCK
373 select PLAT_VERSATILE_SCHED_CLOCK
374 select VERSATILE_FPGA_IRQ
376 This enables support for ARM Ltd Versatile board.
379 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
380 select ARCH_REQUIRE_GPIOLIB
385 select GENERIC_CLOCKEVENTS
389 Support for Cirrus Logic 711x/721x/731x based boards.
392 bool "Cortina Systems Gemini"
393 select ARCH_REQUIRE_GPIOLIB
396 select GENERIC_CLOCKEVENTS
398 Support for the Cortina Systems Gemini family SoCs
402 select ARCH_USES_GETTIMEOFFSET
405 select NEED_MACH_IO_H
406 select NEED_MACH_MEMORY_H
409 This is an evaluation board for the StrongARM processor available
410 from Digital. It has limited hardware on-board, including an
411 Ethernet interface, two PCMCIA sockets, two serial ports and a
415 bool "Energy Micro efm32"
417 select ARCH_REQUIRE_GPIOLIB
423 select GENERIC_CLOCKEVENTS
429 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
434 select ARCH_HAS_HOLES_MEMORYMODEL
435 select ARCH_REQUIRE_GPIOLIB
436 select ARCH_USES_GETTIMEOFFSET
442 This enables support for the Cirrus EP93xx series of CPUs.
444 config ARCH_FOOTBRIDGE
448 select GENERIC_CLOCKEVENTS
450 select NEED_MACH_IO_H if !MMU
451 select NEED_MACH_MEMORY_H
453 Support for systems based on the DC21285 companion chip
454 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
457 bool "Hilscher NetX based"
461 select GENERIC_CLOCKEVENTS
463 This enables support for systems based on the Hilscher NetX Soc
469 select NEED_MACH_MEMORY_H
470 select NEED_RET_TO_USER
476 Support for Intel's IOP13XX (XScale) family of processors.
481 select ARCH_REQUIRE_GPIOLIB
484 select NEED_RET_TO_USER
488 Support for Intel's 80219 and IOP32X (XScale) family of
494 select ARCH_REQUIRE_GPIOLIB
497 select NEED_RET_TO_USER
501 Support for Intel's IOP33X (XScale) family of processors.
506 select ARCH_HAS_DMA_SET_COHERENT_MASK
507 select ARCH_REQUIRE_GPIOLIB
508 select ARCH_SUPPORTS_BIG_ENDIAN
511 select DMABOUNCE if PCI
512 select GENERIC_CLOCKEVENTS
513 select MIGHT_HAVE_PCI
514 select NEED_MACH_IO_H
515 select USB_EHCI_BIG_ENDIAN_DESC
516 select USB_EHCI_BIG_ENDIAN_MMIO
518 Support for Intel's IXP4XX (XScale) family of processors.
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
525 select MIGHT_HAVE_PCI
529 select PLAT_ORION_LEGACY
531 Support for the Marvell Dove SoC 88AP510
534 bool "Marvell MV78xx0"
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
540 select PLAT_ORION_LEGACY
542 Support for the following Marvell MV78xx0 series SoCs:
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell Orion 5x series SoCs:
556 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
557 Orion-2 (5281), Orion-1-90 (6183).
560 bool "Marvell PXA168/910/MMP2"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_ALLOCATOR
565 select GENERIC_CLOCKEVENTS
568 select MULTI_IRQ_HANDLER
573 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
576 bool "Micrel/Kendin KS8695"
577 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
581 select NEED_MACH_MEMORY_H
583 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
584 System-on-Chip devices.
587 bool "Nuvoton W90X900 CPU"
588 select ARCH_REQUIRE_GPIOLIB
592 select GENERIC_CLOCKEVENTS
594 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
595 At present, the w90x900 has been renamed nuc900, regarding
596 the ARM series product line, you can login the following
597 link address to know more.
599 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
600 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
603 bool "NXP LPC18xx/LPC43xx"
605 select ARCH_HAS_RESET_CONTROLLER
606 select ARCH_REQUIRE_GPIOLIB
610 select CLKSRC_LPC32XX
613 select GENERIC_CLOCKEVENTS
619 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
620 high performance microcontrollers.
624 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
633 Support for the NXP LPC32XX family of processors
636 bool "PXA2xx/PXA3xx-based"
639 select ARCH_REQUIRE_GPIOLIB
640 select ARM_CPU_SUSPEND if PM
646 select GENERIC_CLOCKEVENTS
650 select MULTI_IRQ_HANDLER
654 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
656 config ARCH_SHMOBILE_LEGACY
657 bool "Renesas ARM SoCs (non-multiplatform)"
659 select ARM_PATCH_PHYS_VIRT if MMU
662 select GENERIC_CLOCKEVENTS
663 select HAVE_ARM_SCU if SMP
664 select HAVE_ARM_TWD if SMP
666 select MIGHT_HAVE_CACHE_L2X0
667 select MULTI_IRQ_HANDLER
670 select PM_GENERIC_DOMAINS if PM
674 Support for Renesas ARM SoC platforms using a non-multiplatform
675 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
681 select ARCH_MAY_HAVE_PC_FDC
682 select ARCH_SPARSEMEM_ENABLE
683 select ARCH_USES_GETTIMEOFFSET
687 select HAVE_PATA_PLATFORM
689 select NEED_MACH_IO_H
690 select NEED_MACH_MEMORY_H
694 On the Acorn Risc-PC, Linux can support the internal IDE disk and
695 CD-ROM interface, serial and parallel port, and the floppy drive.
700 select ARCH_REQUIRE_GPIOLIB
701 select ARCH_SPARSEMEM_ENABLE
706 select GENERIC_CLOCKEVENTS
710 select MULTI_IRQ_HANDLER
711 select NEED_MACH_MEMORY_H
714 Support for StrongARM 11x0 based boards.
717 bool "Samsung S3C24XX SoCs"
718 select ARCH_REQUIRE_GPIOLIB
721 select CLKSRC_SAMSUNG_PWM
722 select GENERIC_CLOCKEVENTS
724 select HAVE_S3C2410_I2C if I2C
725 select HAVE_S3C2410_WATCHDOG if WATCHDOG
726 select HAVE_S3C_RTC if RTC_CLASS
727 select MULTI_IRQ_HANDLER
728 select NEED_MACH_IO_H
731 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
732 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
733 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
734 Samsung SMDK2410 development board (and derivatives).
737 bool "Samsung S3C64XX"
738 select ARCH_REQUIRE_GPIOLIB
743 select CLKSRC_SAMSUNG_PWM
744 select COMMON_CLK_SAMSUNG
746 select GENERIC_CLOCKEVENTS
748 select HAVE_S3C2410_I2C if I2C
749 select HAVE_S3C2410_WATCHDOG if WATCHDOG
753 select PM_GENERIC_DOMAINS if PM
755 select S3C_GPIO_TRACK
757 select SAMSUNG_WAKEMASK
758 select SAMSUNG_WDT_RESET
760 Samsung S3C64XX series based systems
764 select ARCH_HAS_HOLES_MEMORYMODEL
765 select ARCH_REQUIRE_GPIOLIB
767 select GENERIC_ALLOCATOR
768 select GENERIC_CLOCKEVENTS
769 select GENERIC_IRQ_CHIP
775 Support for TI's DaVinci platform.
780 select ARCH_HAS_HOLES_MEMORYMODEL
782 select ARCH_REQUIRE_GPIOLIB
785 select GENERIC_CLOCKEVENTS
786 select GENERIC_IRQ_CHIP
789 select NEED_MACH_IO_H if PCCARD
790 select NEED_MACH_MEMORY_H
792 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
795 bool "STMicrolectronics STM32"
797 select ARCH_HAS_RESET_CONTROLLER
799 select ARMV7M_SYSTICK
804 select GENERIC_CLOCKEVENTS
806 select RESET_CONTROLLER
810 Support for STMicroelectronics STM32 processors.
814 menu "Multiple platform selection"
815 depends on ARCH_MULTIPLATFORM
817 comment "CPU Core family selection"
820 bool "ARMv4 based platforms (FA526)"
821 depends on !ARCH_MULTI_V6_V7
822 select ARCH_MULTI_V4_V5
825 config ARCH_MULTI_V4T
826 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
827 depends on !ARCH_MULTI_V6_V7
828 select ARCH_MULTI_V4_V5
829 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
830 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
831 CPU_ARM925T || CPU_ARM940T)
834 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
835 depends on !ARCH_MULTI_V6_V7
836 select ARCH_MULTI_V4_V5
837 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
838 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
839 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
841 config ARCH_MULTI_V4_V5
845 bool "ARMv6 based platforms (ARM11)"
846 select ARCH_MULTI_V6_V7
850 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
852 select ARCH_MULTI_V6_V7
856 config ARCH_MULTI_V6_V7
858 select MIGHT_HAVE_CACHE_L2X0
860 config ARCH_MULTI_CPU_AUTO
861 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
867 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
871 select HAVE_ARM_ARCH_TIMER
874 # This is sorted alphabetically by mach-* pathname. However, plat-*
875 # Kconfigs may be included either alphabetically (according to the
876 # plat- suffix) or along side the corresponding mach-* source.
878 source "arch/arm/mach-mvebu/Kconfig"
880 source "arch/arm/mach-alpine/Kconfig"
882 source "arch/arm/mach-asm9260/Kconfig"
884 source "arch/arm/mach-at91/Kconfig"
886 source "arch/arm/mach-axxia/Kconfig"
888 source "arch/arm/mach-bcm/Kconfig"
890 source "arch/arm/mach-berlin/Kconfig"
892 source "arch/arm/mach-clps711x/Kconfig"
894 source "arch/arm/mach-cns3xxx/Kconfig"
896 source "arch/arm/mach-davinci/Kconfig"
898 source "arch/arm/mach-digicolor/Kconfig"
900 source "arch/arm/mach-dove/Kconfig"
902 source "arch/arm/mach-ep93xx/Kconfig"
904 source "arch/arm/mach-footbridge/Kconfig"
906 source "arch/arm/mach-gemini/Kconfig"
908 source "arch/arm/mach-highbank/Kconfig"
910 source "arch/arm/mach-hisi/Kconfig"
912 source "arch/arm/mach-integrator/Kconfig"
914 source "arch/arm/mach-iop32x/Kconfig"
916 source "arch/arm/mach-iop33x/Kconfig"
918 source "arch/arm/mach-iop13xx/Kconfig"
920 source "arch/arm/mach-ixp4xx/Kconfig"
922 source "arch/arm/mach-keystone/Kconfig"
924 source "arch/arm/mach-ks8695/Kconfig"
926 source "arch/arm/mach-meson/Kconfig"
928 source "arch/arm/mach-moxart/Kconfig"
930 source "arch/arm/mach-mv78xx0/Kconfig"
932 source "arch/arm/mach-imx/Kconfig"
934 source "arch/arm/mach-mediatek/Kconfig"
936 source "arch/arm/mach-mxs/Kconfig"
938 source "arch/arm/mach-netx/Kconfig"
940 source "arch/arm/mach-nomadik/Kconfig"
942 source "arch/arm/mach-nspire/Kconfig"
944 source "arch/arm/plat-omap/Kconfig"
946 source "arch/arm/mach-omap1/Kconfig"
948 source "arch/arm/mach-omap2/Kconfig"
950 source "arch/arm/mach-orion5x/Kconfig"
952 source "arch/arm/mach-picoxcell/Kconfig"
954 source "arch/arm/mach-pxa/Kconfig"
955 source "arch/arm/plat-pxa/Kconfig"
957 source "arch/arm/mach-mmp/Kconfig"
959 source "arch/arm/mach-qcom/Kconfig"
961 source "arch/arm/mach-realview/Kconfig"
963 source "arch/arm/mach-rockchip/Kconfig"
965 source "arch/arm/mach-sa1100/Kconfig"
967 source "arch/arm/mach-socfpga/Kconfig"
969 source "arch/arm/mach-spear/Kconfig"
971 source "arch/arm/mach-sti/Kconfig"
973 source "arch/arm/mach-s3c24xx/Kconfig"
975 source "arch/arm/mach-s3c64xx/Kconfig"
977 source "arch/arm/mach-s5pv210/Kconfig"
979 source "arch/arm/mach-exynos/Kconfig"
980 source "arch/arm/plat-samsung/Kconfig"
982 source "arch/arm/mach-shmobile/Kconfig"
984 source "arch/arm/mach-sunxi/Kconfig"
986 source "arch/arm/mach-prima2/Kconfig"
988 source "arch/arm/mach-tegra/Kconfig"
990 source "arch/arm/mach-u300/Kconfig"
992 source "arch/arm/mach-uniphier/Kconfig"
994 source "arch/arm/mach-ux500/Kconfig"
996 source "arch/arm/mach-versatile/Kconfig"
998 source "arch/arm/mach-vexpress/Kconfig"
999 source "arch/arm/plat-versatile/Kconfig"
1001 source "arch/arm/mach-vt8500/Kconfig"
1003 source "arch/arm/mach-w90x900/Kconfig"
1005 source "arch/arm/mach-zx/Kconfig"
1007 source "arch/arm/mach-zynq/Kconfig"
1009 # Definitions to make life easier
1015 select GENERIC_CLOCKEVENTS
1021 select GENERIC_IRQ_CHIP
1024 config PLAT_ORION_LEGACY
1031 config PLAT_VERSATILE
1034 config ARM_TIMER_SP804
1037 select CLKSRC_OF if OF
1039 source "arch/arm/firmware/Kconfig"
1041 source arch/arm/mm/Kconfig
1044 bool "Enable iWMMXt support"
1045 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1046 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1048 Enable support for iWMMXt context switching at run time if
1049 running on a CPU that supports it.
1051 config MULTI_IRQ_HANDLER
1054 Allow each machine to specify it's own IRQ handler at run time.
1057 source "arch/arm/Kconfig-nommu"
1060 config PJ4B_ERRATA_4742
1061 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1062 depends on CPU_PJ4B && MACH_ARMADA_370
1065 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1066 Event (WFE) IDLE states, a specific timing sensitivity exists between
1067 the retiring WFI/WFE instructions and the newly issued subsequent
1068 instructions. This sensitivity can result in a CPU hang scenario.
1070 The software must insert either a Data Synchronization Barrier (DSB)
1071 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1074 config ARM_ERRATA_326103
1075 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1078 Executing a SWP instruction to read-only memory does not set bit 11
1079 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1080 treat the access as a read, preventing a COW from occurring and
1081 causing the faulting task to livelock.
1083 config ARM_ERRATA_411920
1084 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1085 depends on CPU_V6 || CPU_V6K
1087 Invalidation of the Instruction Cache operation can
1088 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1089 It does not affect the MPCore. This option enables the ARM Ltd.
1090 recommended workaround.
1092 config ARM_ERRATA_430973
1093 bool "ARM errata: Stale prediction on replaced interworking branch"
1096 This option enables the workaround for the 430973 Cortex-A8
1097 r1p* erratum. If a code sequence containing an ARM/Thumb
1098 interworking branch is replaced with another code sequence at the
1099 same virtual address, whether due to self-modifying code or virtual
1100 to physical address re-mapping, Cortex-A8 does not recover from the
1101 stale interworking branch prediction. This results in Cortex-A8
1102 executing the new code sequence in the incorrect ARM or Thumb state.
1103 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1104 and also flushes the branch target cache at every context switch.
1105 Note that setting specific bits in the ACTLR register may not be
1106 available in non-secure mode.
1108 config ARM_ERRATA_458693
1109 bool "ARM errata: Processor deadlock when a false hazard is created"
1111 depends on !ARCH_MULTIPLATFORM
1113 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1114 erratum. For very specific sequences of memory operations, it is
1115 possible for a hazard condition intended for a cache line to instead
1116 be incorrectly associated with a different cache line. This false
1117 hazard might then cause a processor deadlock. The workaround enables
1118 the L1 caching of the NEON accesses and disables the PLD instruction
1119 in the ACTLR register. Note that setting specific bits in the ACTLR
1120 register may not be available in non-secure mode.
1122 config ARM_ERRATA_460075
1123 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1125 depends on !ARCH_MULTIPLATFORM
1127 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1128 erratum. Any asynchronous access to the L2 cache may encounter a
1129 situation in which recent store transactions to the L2 cache are lost
1130 and overwritten with stale memory contents from external memory. The
1131 workaround disables the write-allocate mode for the L2 cache via the
1132 ACTLR register. Note that setting specific bits in the ACTLR register
1133 may not be available in non-secure mode.
1135 config ARM_ERRATA_742230
1136 bool "ARM errata: DMB operation may be faulty"
1137 depends on CPU_V7 && SMP
1138 depends on !ARCH_MULTIPLATFORM
1140 This option enables the workaround for the 742230 Cortex-A9
1141 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1142 between two write operations may not ensure the correct visibility
1143 ordering of the two writes. This workaround sets a specific bit in
1144 the diagnostic register of the Cortex-A9 which causes the DMB
1145 instruction to behave as a DSB, ensuring the correct behaviour of
1148 config ARM_ERRATA_742231
1149 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1150 depends on CPU_V7 && SMP
1151 depends on !ARCH_MULTIPLATFORM
1153 This option enables the workaround for the 742231 Cortex-A9
1154 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1155 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1156 accessing some data located in the same cache line, may get corrupted
1157 data due to bad handling of the address hazard when the line gets
1158 replaced from one of the CPUs at the same time as another CPU is
1159 accessing it. This workaround sets specific bits in the diagnostic
1160 register of the Cortex-A9 which reduces the linefill issuing
1161 capabilities of the processor.
1163 config ARM_ERRATA_643719
1164 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1165 depends on CPU_V7 && SMP
1168 This option enables the workaround for the 643719 Cortex-A9 (prior to
1169 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1170 register returns zero when it should return one. The workaround
1171 corrects this value, ensuring cache maintenance operations which use
1172 it behave as intended and avoiding data corruption.
1174 config ARM_ERRATA_720789
1175 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1178 This option enables the workaround for the 720789 Cortex-A9 (prior to
1179 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1180 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1181 As a consequence of this erratum, some TLB entries which should be
1182 invalidated are not, resulting in an incoherency in the system page
1183 tables. The workaround changes the TLB flushing routines to invalidate
1184 entries regardless of the ASID.
1186 config ARM_ERRATA_743622
1187 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1189 depends on !ARCH_MULTIPLATFORM
1191 This option enables the workaround for the 743622 Cortex-A9
1192 (r2p*) erratum. Under very rare conditions, a faulty
1193 optimisation in the Cortex-A9 Store Buffer may lead to data
1194 corruption. This workaround sets a specific bit in the diagnostic
1195 register of the Cortex-A9 which disables the Store Buffer
1196 optimisation, preventing the defect from occurring. This has no
1197 visible impact on the overall performance or power consumption of the
1200 config ARM_ERRATA_751472
1201 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1203 depends on !ARCH_MULTIPLATFORM
1205 This option enables the workaround for the 751472 Cortex-A9 (prior
1206 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1207 completion of a following broadcasted operation if the second
1208 operation is received by a CPU before the ICIALLUIS has completed,
1209 potentially leading to corrupted entries in the cache or TLB.
1211 config ARM_ERRATA_754322
1212 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1215 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1216 r3p*) erratum. A speculative memory access may cause a page table walk
1217 which starts prior to an ASID switch but completes afterwards. This
1218 can populate the micro-TLB with a stale entry which may be hit with
1219 the new ASID. This workaround places two dsb instructions in the mm
1220 switching code so that no page table walks can cross the ASID switch.
1222 config ARM_ERRATA_754327
1223 bool "ARM errata: no automatic Store Buffer drain"
1224 depends on CPU_V7 && SMP
1226 This option enables the workaround for the 754327 Cortex-A9 (prior to
1227 r2p0) erratum. The Store Buffer does not have any automatic draining
1228 mechanism and therefore a livelock may occur if an external agent
1229 continuously polls a memory location waiting to observe an update.
1230 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1231 written polling loops from denying visibility of updates to memory.
1233 config ARM_ERRATA_364296
1234 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1237 This options enables the workaround for the 364296 ARM1136
1238 r0p2 erratum (possible cache data corruption with
1239 hit-under-miss enabled). It sets the undocumented bit 31 in
1240 the auxiliary control register and the FI bit in the control
1241 register, thus disabling hit-under-miss without putting the
1242 processor into full low interrupt latency mode. ARM11MPCore
1245 config ARM_ERRATA_764369
1246 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1247 depends on CPU_V7 && SMP
1249 This option enables the workaround for erratum 764369
1250 affecting Cortex-A9 MPCore with two or more processors (all
1251 current revisions). Under certain timing circumstances, a data
1252 cache line maintenance operation by MVA targeting an Inner
1253 Shareable memory region may fail to proceed up to either the
1254 Point of Coherency or to the Point of Unification of the
1255 system. This workaround adds a DSB instruction before the
1256 relevant cache maintenance functions and sets a specific bit
1257 in the diagnostic control register of the SCU.
1259 config ARM_ERRATA_775420
1260 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1263 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1264 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1265 operation aborts with MMU exception, it might cause the processor
1266 to deadlock. This workaround puts DSB before executing ISB if
1267 an abort may occur on cache maintenance.
1269 config ARM_ERRATA_798181
1270 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1271 depends on CPU_V7 && SMP
1273 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1274 adequately shooting down all use of the old entries. This
1275 option enables the Linux kernel workaround for this erratum
1276 which sends an IPI to the CPUs that are running the same ASID
1277 as the one being invalidated.
1279 config ARM_ERRATA_773022
1280 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1283 This option enables the workaround for the 773022 Cortex-A15
1284 (up to r0p4) erratum. In certain rare sequences of code, the
1285 loop buffer may deliver incorrect instructions. This
1286 workaround disables the loop buffer to avoid the erratum.
1290 source "arch/arm/common/Kconfig"
1297 Find out whether you have ISA slots on your motherboard. ISA is the
1298 name of a bus system, i.e. the way the CPU talks to the other stuff
1299 inside your box. Other bus systems are PCI, EISA, MicroChannel
1300 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1301 newer boards don't support it. If you have ISA, say Y, otherwise N.
1303 # Select ISA DMA controller support
1308 # Select ISA DMA interface
1313 bool "PCI support" if MIGHT_HAVE_PCI
1315 Find out whether you have a PCI motherboard. PCI is the name of a
1316 bus system, i.e. the way the CPU talks to the other stuff inside
1317 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1318 VESA. If you have PCI, say Y, otherwise N.
1324 config PCI_DOMAINS_GENERIC
1325 def_bool PCI_DOMAINS
1327 config PCI_NANOENGINE
1328 bool "BSE nanoEngine PCI support"
1329 depends on SA1100_NANOENGINE
1331 Enable PCI on the BSE nanoEngine board.
1336 config PCI_HOST_ITE8152
1338 depends on PCI && MACH_ARMCORE
1342 source "drivers/pci/Kconfig"
1343 source "drivers/pci/pcie/Kconfig"
1345 source "drivers/pcmcia/Kconfig"
1349 menu "Kernel Features"
1354 This option should be selected by machines which have an SMP-
1357 The only effect of this option is to make the SMP-related
1358 options available to the user for configuration.
1361 bool "Symmetric Multi-Processing"
1362 depends on CPU_V6K || CPU_V7
1363 depends on GENERIC_CLOCKEVENTS
1365 depends on MMU || ARM_MPU
1367 This enables support for systems with more than one CPU. If you have
1368 a system with only one CPU, say N. If you have a system with more
1369 than one CPU, say Y.
1371 If you say N here, the kernel will run on uni- and multiprocessor
1372 machines, but will use only one CPU of a multiprocessor machine. If
1373 you say Y here, the kernel will run on many, but not all,
1374 uniprocessor machines. On a uniprocessor machine, the kernel
1375 will run faster if you say N here.
1377 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1378 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1379 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1381 If you don't know what to do here, say N.
1384 bool "Allow booting SMP kernel on uniprocessor systems"
1385 depends on SMP && !XIP_KERNEL && MMU
1388 SMP kernels contain instructions which fail on non-SMP processors.
1389 Enabling this option allows the kernel to modify itself to make
1390 these instructions safe. Disabling it allows about 1K of space
1393 If you don't know what to do here, say Y.
1395 config ARM_CPU_TOPOLOGY
1396 bool "Support cpu topology definition"
1397 depends on SMP && CPU_V7
1400 Support ARM cpu topology definition. The MPIDR register defines
1401 affinity between processors which is then used to describe the cpu
1402 topology of an ARM System.
1405 bool "Multi-core scheduler support"
1406 depends on ARM_CPU_TOPOLOGY
1408 Multi-core scheduler support improves the CPU scheduler's decision
1409 making when dealing with multi-core CPU chips at a cost of slightly
1410 increased overhead in some places. If unsure say N here.
1413 bool "SMT scheduler support"
1414 depends on ARM_CPU_TOPOLOGY
1416 Improves the CPU scheduler's decision making when dealing with
1417 MultiThreading at a cost of slightly increased overhead in some
1418 places. If unsure say N here.
1423 This option enables support for the ARM system coherency unit
1425 config HAVE_ARM_ARCH_TIMER
1426 bool "Architected timer support"
1428 select ARM_ARCH_TIMER
1429 select GENERIC_CLOCKEVENTS
1431 This option enables support for the ARM architected timer
1436 select CLKSRC_OF if OF
1438 This options enables support for the ARM timer and watchdog unit
1441 bool "Multi-Cluster Power Management"
1442 depends on CPU_V7 && SMP
1444 This option provides the common power management infrastructure
1445 for (multi-)cluster based systems, such as big.LITTLE based
1448 config MCPM_QUAD_CLUSTER
1452 To avoid wasting resources unnecessarily, MCPM only supports up
1453 to 2 clusters by default.
1454 Platforms with 3 or 4 clusters that use MCPM must select this
1455 option to allow the additional clusters to be managed.
1458 bool "big.LITTLE support (Experimental)"
1459 depends on CPU_V7 && SMP
1462 This option enables support selections for the big.LITTLE
1463 system architecture.
1466 bool "big.LITTLE switcher support"
1467 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1468 select ARM_CPU_SUSPEND
1471 The big.LITTLE "switcher" provides the core functionality to
1472 transparently handle transition between a cluster of A15's
1473 and a cluster of A7's in a big.LITTLE system.
1475 config BL_SWITCHER_DUMMY_IF
1476 tristate "Simple big.LITTLE switcher user interface"
1477 depends on BL_SWITCHER && DEBUG_KERNEL
1479 This is a simple and dummy char dev interface to control
1480 the big.LITTLE switcher core code. It is meant for
1481 debugging purposes only.
1484 prompt "Memory split"
1488 Select the desired split between kernel and user memory.
1490 If you are not absolutely sure what you are doing, leave this
1494 bool "3G/1G user/kernel split"
1496 bool "2G/2G user/kernel split"
1498 bool "1G/3G user/kernel split"
1503 default PHYS_OFFSET if !MMU
1504 default 0x40000000 if VMSPLIT_1G
1505 default 0x80000000 if VMSPLIT_2G
1509 int "Maximum number of CPUs (2-32)"
1515 bool "Support for hot-pluggable CPUs"
1518 Say Y here to experiment with turning CPUs off and on. CPUs
1519 can be controlled through /sys/devices/system/cpu.
1522 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1525 Say Y here if you want Linux to communicate with system firmware
1526 implementing the PSCI specification for CPU-centric power
1527 management operations described in ARM document number ARM DEN
1528 0022A ("Power State Coordination Interface System Software on
1531 # The GPIO number here must be sorted by descending number. In case of
1532 # a multiplatform kernel, we just want the highest value required by the
1533 # selected platforms.
1536 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1537 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1538 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1539 default 416 if ARCH_SUNXI
1540 default 392 if ARCH_U8500
1541 default 352 if ARCH_VT8500
1542 default 288 if ARCH_ROCKCHIP
1543 default 264 if MACH_H4700
1546 Maximum number of GPIOs in the system.
1548 If unsure, leave the default value.
1550 source kernel/Kconfig.preempt
1554 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1555 ARCH_S5PV210 || ARCH_EXYNOS4
1556 default 128 if SOC_AT91RM9200
1557 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1561 depends on HZ_FIXED = 0
1562 prompt "Timer frequency"
1586 default HZ_FIXED if HZ_FIXED != 0
1587 default 100 if HZ_100
1588 default 200 if HZ_200
1589 default 250 if HZ_250
1590 default 300 if HZ_300
1591 default 500 if HZ_500
1595 def_bool HIGH_RES_TIMERS
1597 config THUMB2_KERNEL
1598 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1599 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1600 default y if CPU_THUMBONLY
1602 select ARM_ASM_UNIFIED
1605 By enabling this option, the kernel will be compiled in
1606 Thumb-2 mode. A compiler/assembler that understand the unified
1607 ARM-Thumb syntax is needed.
1611 config THUMB2_AVOID_R_ARM_THM_JUMP11
1612 bool "Work around buggy Thumb-2 short branch relocations in gas"
1613 depends on THUMB2_KERNEL && MODULES
1616 Various binutils versions can resolve Thumb-2 branches to
1617 locally-defined, preemptible global symbols as short-range "b.n"
1618 branch instructions.
1620 This is a problem, because there's no guarantee the final
1621 destination of the symbol, or any candidate locations for a
1622 trampoline, are within range of the branch. For this reason, the
1623 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1624 relocation in modules at all, and it makes little sense to add
1627 The symptom is that the kernel fails with an "unsupported
1628 relocation" error when loading some modules.
1630 Until fixed tools are available, passing
1631 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1632 code which hits this problem, at the cost of a bit of extra runtime
1633 stack usage in some cases.
1635 The problem is described in more detail at:
1636 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1638 Only Thumb-2 kernels are affected.
1640 Unless you are sure your tools don't have this problem, say Y.
1642 config ARM_ASM_UNIFIED
1646 bool "Use the ARM EABI to compile the kernel"
1648 This option allows for the kernel to be compiled using the latest
1649 ARM ABI (aka EABI). This is only useful if you are using a user
1650 space environment that is also compiled with EABI.
1652 Since there are major incompatibilities between the legacy ABI and
1653 EABI, especially with regard to structure member alignment, this
1654 option also changes the kernel syscall calling convention to
1655 disambiguate both ABIs and allow for backward compatibility support
1656 (selected with CONFIG_OABI_COMPAT).
1658 To use this you need GCC version 4.0.0 or later.
1661 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1662 depends on AEABI && !THUMB2_KERNEL
1664 This option preserves the old syscall interface along with the
1665 new (ARM EABI) one. It also provides a compatibility layer to
1666 intercept syscalls that have structure arguments which layout
1667 in memory differs between the legacy ABI and the new ARM EABI
1668 (only for non "thumb" binaries). This option adds a tiny
1669 overhead to all syscalls and produces a slightly larger kernel.
1671 The seccomp filter system will not be available when this is
1672 selected, since there is no way yet to sensibly distinguish
1673 between calling conventions during filtering.
1675 If you know you'll be using only pure EABI user space then you
1676 can say N here. If this option is not selected and you attempt
1677 to execute a legacy ABI binary then the result will be
1678 UNPREDICTABLE (in fact it can be predicted that it won't work
1679 at all). If in doubt say N.
1681 config ARCH_HAS_HOLES_MEMORYMODEL
1684 config ARCH_SPARSEMEM_ENABLE
1687 config ARCH_SPARSEMEM_DEFAULT
1688 def_bool ARCH_SPARSEMEM_ENABLE
1690 config ARCH_SELECT_MEMORY_MODEL
1691 def_bool ARCH_SPARSEMEM_ENABLE
1693 config HAVE_ARCH_PFN_VALID
1694 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1696 config HAVE_GENERIC_RCU_GUP
1701 bool "High Memory Support"
1704 The address space of ARM processors is only 4 Gigabytes large
1705 and it has to accommodate user address space, kernel address
1706 space as well as some memory mapped IO. That means that, if you
1707 have a large amount of physical memory and/or IO, not all of the
1708 memory can be "permanently mapped" by the kernel. The physical
1709 memory that is not permanently mapped is called "high memory".
1711 Depending on the selected kernel/user memory split, minimum
1712 vmalloc space and actual amount of RAM, you may not need this
1713 option which should result in a slightly faster kernel.
1718 bool "Allocate 2nd-level pagetables from highmem"
1721 config HW_PERF_EVENTS
1722 bool "Enable hardware performance counter support for perf events"
1723 depends on PERF_EVENTS
1726 Enable hardware performance counter support for perf events. If
1727 disabled, perf events will use software events only.
1729 config SYS_SUPPORTS_HUGETLBFS
1733 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1737 config ARCH_WANT_GENERAL_HUGETLB
1742 config FORCE_MAX_ZONEORDER
1743 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1744 range 11 64 if ARCH_SHMOBILE_LEGACY
1745 default "12" if SOC_AM33XX
1746 default "9" if SA1111 || ARCH_EFM32
1749 The kernel memory allocator divides physically contiguous memory
1750 blocks into "zones", where each zone is a power of two number of
1751 pages. This option selects the largest power of two that the kernel
1752 keeps in the memory allocator. If you need to allocate very large
1753 blocks of physically contiguous memory, then you may need to
1754 increase this value.
1756 This config option is actually maximum order plus one. For example,
1757 a value of 11 means that the largest free memory block is 2^10 pages.
1759 config ALIGNMENT_TRAP
1761 depends on CPU_CP15_MMU
1762 default y if !ARCH_EBSA110
1763 select HAVE_PROC_CPU if PROC_FS
1765 ARM processors cannot fetch/store information which is not
1766 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1767 address divisible by 4. On 32-bit ARM processors, these non-aligned
1768 fetch/store instructions will be emulated in software if you say
1769 here, which has a severe performance impact. This is necessary for
1770 correct operation of some network protocols. With an IP-only
1771 configuration it is safe to say N, otherwise say Y.
1773 config UACCESS_WITH_MEMCPY
1774 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1776 default y if CPU_FEROCEON
1778 Implement faster copy_to_user and clear_user methods for CPU
1779 cores where a 8-word STM instruction give significantly higher
1780 memory write throughput than a sequence of individual 32bit stores.
1782 A possible side effect is a slight increase in scheduling latency
1783 between threads sharing the same address space if they invoke
1784 such copy operations with large buffers.
1786 However, if the CPU data cache is using a write-allocate mode,
1787 this option is unlikely to provide any performance gain.
1791 prompt "Enable seccomp to safely compute untrusted bytecode"
1793 This kernel feature is useful for number crunching applications
1794 that may need to compute untrusted bytecode during their
1795 execution. By using pipes or other transports made available to
1796 the process as file descriptors supporting the read/write
1797 syscalls, it's possible to isolate those applications in
1798 their own address space using seccomp. Once seccomp is
1799 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1800 and the task is only allowed to execute a few safe syscalls
1801 defined by each seccomp mode.
1814 bool "Xen guest support on ARM"
1815 depends on ARM && AEABI && OF
1816 depends on CPU_V7 && !CPU_V6
1817 depends on !GENERIC_ATOMIC64
1819 select ARCH_DMA_ADDR_T_64BIT
1823 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1830 bool "Flattened Device Tree support"
1833 select OF_EARLY_FLATTREE
1834 select OF_RESERVED_MEM
1836 Include support for flattened device tree machine descriptions.
1839 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1842 This is the traditional way of passing data to the kernel at boot
1843 time. If you are solely relying on the flattened device tree (or
1844 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1845 to remove ATAGS support from your kernel binary. If unsure,
1848 config DEPRECATED_PARAM_STRUCT
1849 bool "Provide old way to pass kernel parameters"
1852 This was deprecated in 2001 and announced to live on for 5 years.
1853 Some old boot loaders still use this way.
1855 # Compressed boot loader in ROM. Yes, we really want to ask about
1856 # TEXT and BSS so we preserve their values in the config files.
1857 config ZBOOT_ROM_TEXT
1858 hex "Compressed ROM boot loader base address"
1861 The physical address at which the ROM-able zImage is to be
1862 placed in the target. Platforms which normally make use of
1863 ROM-able zImage formats normally set this to a suitable
1864 value in their defconfig file.
1866 If ZBOOT_ROM is not enabled, this has no effect.
1868 config ZBOOT_ROM_BSS
1869 hex "Compressed ROM boot loader BSS address"
1872 The base address of an area of read/write memory in the target
1873 for the ROM-able zImage which must be available while the
1874 decompressor is running. It must be large enough to hold the
1875 entire decompressed kernel plus an additional 128 KiB.
1876 Platforms which normally make use of ROM-able zImage formats
1877 normally set this to a suitable value in their defconfig file.
1879 If ZBOOT_ROM is not enabled, this has no effect.
1882 bool "Compressed boot loader in ROM/flash"
1883 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1884 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1886 Say Y here if you intend to execute your compressed kernel image
1887 (zImage) directly from ROM or flash. If unsure, say N.
1889 config ARM_APPENDED_DTB
1890 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1893 With this option, the boot code will look for a device tree binary
1894 (DTB) appended to zImage
1895 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1897 This is meant as a backward compatibility convenience for those
1898 systems with a bootloader that can't be upgraded to accommodate
1899 the documented boot protocol using a device tree.
1901 Beware that there is very little in terms of protection against
1902 this option being confused by leftover garbage in memory that might
1903 look like a DTB header after a reboot if no actual DTB is appended
1904 to zImage. Do not leave this option active in a production kernel
1905 if you don't intend to always append a DTB. Proper passing of the
1906 location into r2 of a bootloader provided DTB is always preferable
1909 config ARM_ATAG_DTB_COMPAT
1910 bool "Supplement the appended DTB with traditional ATAG information"
1911 depends on ARM_APPENDED_DTB
1913 Some old bootloaders can't be updated to a DTB capable one, yet
1914 they provide ATAGs with memory configuration, the ramdisk address,
1915 the kernel cmdline string, etc. Such information is dynamically
1916 provided by the bootloader and can't always be stored in a static
1917 DTB. To allow a device tree enabled kernel to be used with such
1918 bootloaders, this option allows zImage to extract the information
1919 from the ATAG list and store it at run time into the appended DTB.
1922 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1923 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1925 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1926 bool "Use bootloader kernel arguments if available"
1928 Uses the command-line options passed by the boot loader instead of
1929 the device tree bootargs property. If the boot loader doesn't provide
1930 any, the device tree bootargs property will be used.
1932 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1933 bool "Extend with bootloader kernel arguments"
1935 The command-line arguments provided by the boot loader will be
1936 appended to the the device tree bootargs property.
1941 string "Default kernel command string"
1944 On some architectures (EBSA110 and CATS), there is currently no way
1945 for the boot loader to pass arguments to the kernel. For these
1946 architectures, you should supply some command-line options at build
1947 time by entering them here. As a minimum, you should specify the
1948 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1951 prompt "Kernel command line type" if CMDLINE != ""
1952 default CMDLINE_FROM_BOOTLOADER
1955 config CMDLINE_FROM_BOOTLOADER
1956 bool "Use bootloader kernel arguments if available"
1958 Uses the command-line options passed by the boot loader. If
1959 the boot loader doesn't provide any, the default kernel command
1960 string provided in CMDLINE will be used.
1962 config CMDLINE_EXTEND
1963 bool "Extend bootloader kernel arguments"
1965 The command-line arguments provided by the boot loader will be
1966 appended to the default kernel command string.
1968 config CMDLINE_FORCE
1969 bool "Always use the default kernel command string"
1971 Always use the default kernel command string, even if the boot
1972 loader passes other arguments to the kernel.
1973 This is useful if you cannot or don't want to change the
1974 command-line options your boot loader passes to the kernel.
1978 bool "Kernel Execute-In-Place from ROM"
1979 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1981 Execute-In-Place allows the kernel to run from non-volatile storage
1982 directly addressable by the CPU, such as NOR flash. This saves RAM
1983 space since the text section of the kernel is not loaded from flash
1984 to RAM. Read-write sections, such as the data section and stack,
1985 are still copied to RAM. The XIP kernel is not compressed since
1986 it has to run directly from flash, so it will take more space to
1987 store it. The flash address used to link the kernel object files,
1988 and for storing it, is configuration dependent. Therefore, if you
1989 say Y here, you must know the proper physical address where to
1990 store the kernel image depending on your own flash memory usage.
1992 Also note that the make target becomes "make xipImage" rather than
1993 "make zImage" or "make Image". The final kernel binary to put in
1994 ROM memory will be arch/arm/boot/xipImage.
1998 config XIP_PHYS_ADDR
1999 hex "XIP Kernel Physical Location"
2000 depends on XIP_KERNEL
2001 default "0x00080000"
2003 This is the physical address in your flash memory the kernel will
2004 be linked for and stored to. This address is dependent on your
2008 bool "Kexec system call (EXPERIMENTAL)"
2009 depends on (!SMP || PM_SLEEP_SMP)
2011 kexec is a system call that implements the ability to shutdown your
2012 current kernel, and to start another kernel. It is like a reboot
2013 but it is independent of the system firmware. And like a reboot
2014 you can start any kernel with it, not just Linux.
2016 It is an ongoing process to be certain the hardware in a machine
2017 is properly shutdown, so do not be surprised if this code does not
2018 initially work for you.
2021 bool "Export atags in procfs"
2022 depends on ATAGS && KEXEC
2025 Should the atags used to boot the kernel be exported in an "atags"
2026 file in procfs. Useful with kexec.
2029 bool "Build kdump crash kernel (EXPERIMENTAL)"
2031 Generate crash dump after being started by kexec. This should
2032 be normally only set in special crash dump kernels which are
2033 loaded in the main kernel with kexec-tools into a specially
2034 reserved region and then later executed after a crash by
2035 kdump/kexec. The crash dump kernel must be compiled to a
2036 memory address not used by the main kernel
2038 For more details see Documentation/kdump/kdump.txt
2040 config AUTO_ZRELADDR
2041 bool "Auto calculation of the decompressed kernel image address"
2043 ZRELADDR is the physical address where the decompressed kernel
2044 image will be placed. If AUTO_ZRELADDR is selected, the address
2045 will be determined at run-time by masking the current IP with
2046 0xf8000000. This assumes the zImage being placed in the first 128MB
2047 from start of memory.
2051 menu "CPU Power Management"
2053 source "drivers/cpufreq/Kconfig"
2055 source "drivers/cpuidle/Kconfig"
2059 menu "Floating point emulation"
2061 comment "At least one emulation must be selected"
2064 bool "NWFPE math emulation"
2065 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2067 Say Y to include the NWFPE floating point emulator in the kernel.
2068 This is necessary to run most binaries. Linux does not currently
2069 support floating point hardware so you need to say Y here even if
2070 your machine has an FPA or floating point co-processor podule.
2072 You may say N here if you are going to load the Acorn FPEmulator
2073 early in the bootup.
2076 bool "Support extended precision"
2077 depends on FPE_NWFPE
2079 Say Y to include 80-bit support in the kernel floating-point
2080 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2081 Note that gcc does not generate 80-bit operations by default,
2082 so in most cases this option only enlarges the size of the
2083 floating point emulator without any good reason.
2085 You almost surely want to say N here.
2088 bool "FastFPE math emulation (EXPERIMENTAL)"
2089 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2091 Say Y here to include the FAST floating point emulator in the kernel.
2092 This is an experimental much faster emulator which now also has full
2093 precision for the mantissa. It does not support any exceptions.
2094 It is very simple, and approximately 3-6 times faster than NWFPE.
2096 It should be sufficient for most programs. It may be not suitable
2097 for scientific calculations, but you have to check this for yourself.
2098 If you do not feel you need a faster FP emulation you should better
2102 bool "VFP-format floating point maths"
2103 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2105 Say Y to include VFP support code in the kernel. This is needed
2106 if your hardware includes a VFP unit.
2108 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2109 release notes and additional status information.
2111 Say N if your target does not have VFP hardware.
2119 bool "Advanced SIMD (NEON) Extension support"
2120 depends on VFPv3 && CPU_V7
2122 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2125 config KERNEL_MODE_NEON
2126 bool "Support for NEON in kernel mode"
2127 depends on NEON && AEABI
2129 Say Y to include support for NEON in kernel mode.
2133 menu "Userspace binary formats"
2135 source "fs/Kconfig.binfmt"
2139 menu "Power management options"
2141 source "kernel/power/Kconfig"
2143 config ARCH_SUSPEND_POSSIBLE
2144 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2145 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2148 config ARM_CPU_SUSPEND
2151 config ARCH_HIBERNATION_POSSIBLE
2154 default y if ARCH_SUSPEND_POSSIBLE
2158 source "net/Kconfig"
2160 source "drivers/Kconfig"
2162 source "drivers/firmware/Kconfig"
2166 source "arch/arm/Kconfig.debug"
2168 source "security/Kconfig"
2170 source "crypto/Kconfig"
2172 source "arch/arm/crypto/Kconfig"
2175 source "lib/Kconfig"
2177 source "arch/arm/kvm/Kconfig"