4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_CMPXCHG_LOCKREF
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CLONE_BACKWARDS
13 select CPU_PM if (SUSPEND || CPU_IDLE)
14 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
15 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
16 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
17 select GENERIC_IDLE_POLL_SETUP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_SCHED_CLOCK
22 select GENERIC_SMP_IDLE_THREAD
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select HARDIRQS_SW_RESEND
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
28 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_TRACEHOOK
31 select HAVE_CONTEXT_TRACKING
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_DEBUG_KMEMLEAK
35 select HAVE_DMA_API_DEBUG
37 select HAVE_DMA_CONTIGUOUS if MMU
38 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
39 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
40 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
41 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
42 select HAVE_GENERIC_DMA_COHERENT
43 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
44 select HAVE_IDE if PCI || ISA || PCMCIA
45 select HAVE_IRQ_TIME_ACCOUNTING
46 select HAVE_KERNEL_GZIP
47 select HAVE_KERNEL_LZ4
48 select HAVE_KERNEL_LZMA
49 select HAVE_KERNEL_LZO
51 select HAVE_KPROBES if !XIP_KERNEL
52 select HAVE_KRETPROBES if (HAVE_KPROBES)
54 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
55 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
56 select HAVE_PERF_EVENTS
58 select HAVE_PERF_USER_STACK_DUMP
59 select HAVE_REGS_AND_STACK_ACCESS_API
60 select HAVE_SYSCALL_TRACEPOINTS
62 select HAVE_VIRT_CPU_ACCOUNTING_GEN
63 select IRQ_FORCED_THREADING
65 select MODULES_USE_ELF_REL
67 select OLD_SIGSUSPEND3
68 select PERF_USE_VMALLOC
70 select SYS_SUPPORTS_APM_EMULATION
71 # Above selects are sorted alphabetically; please add new ones
72 # according to that. Thanks.
74 The ARM series is a line of low-power-consumption RISC chip designs
75 licensed by ARM Ltd and targeted at embedded applications and
76 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
77 manufactured, but legacy ARM-based PC hardware remains popular in
78 Europe. There is an ARM Linux project with a web page at
79 <http://www.arm.linux.org.uk/>.
81 config ARM_HAS_SG_CHAIN
84 config NEED_SG_DMA_LENGTH
87 config ARM_DMA_USE_IOMMU
89 select ARM_HAS_SG_CHAIN
90 select NEED_SG_DMA_LENGTH
94 config ARM_DMA_IOMMU_ALIGNMENT
95 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
99 DMA mapping framework by default aligns all buffers to the smallest
100 PAGE_SIZE order which is greater than or equal to the requested buffer
101 size. This works well for buffers up to a few hundreds kilobytes, but
102 for larger buffers it just a waste of address space. Drivers which has
103 relatively small addressing window (like 64Mib) might run out of
104 virtual space with just a few allocations.
106 With this parameter you can specify the maximum PAGE_SIZE order for
107 DMA IOMMU buffers. Larger buffers will be aligned only to this
108 specified order. The order is expressed as a power of two multiplied
116 config MIGHT_HAVE_PCI
119 config SYS_SUPPORTS_APM_EMULATION
124 select GENERIC_ALLOCATOR
135 The Extended Industry Standard Architecture (EISA) bus was
136 developed as an open alternative to the IBM MicroChannel bus.
138 The EISA bus provided some of the features of the IBM MicroChannel
139 bus while maintaining backward compatibility with cards made for
140 the older ISA bus. The EISA bus saw limited use between 1988 and
141 1995 when it was made obsolete by the PCI bus.
143 Say Y here if you are building a kernel for an EISA-based machine.
150 config STACKTRACE_SUPPORT
154 config HAVE_LATENCYTOP_SUPPORT
159 config LOCKDEP_SUPPORT
163 config TRACE_IRQFLAGS_SUPPORT
167 config RWSEM_GENERIC_SPINLOCK
171 config RWSEM_XCHGADD_ALGORITHM
174 config ARCH_HAS_ILOG2_U32
177 config ARCH_HAS_ILOG2_U64
180 config ARCH_HAS_CPUFREQ
183 Internal node to signify that the ARCH has CPUFREQ support
184 and that the relevant menu configurations are displayed for
187 config ARCH_HAS_BANDGAP
190 config GENERIC_HWEIGHT
194 config GENERIC_CALIBRATE_DELAY
198 config ARCH_MAY_HAVE_PC_FDC
204 config NEED_DMA_MAP_STATE
207 config ARCH_HAS_DMA_SET_COHERENT_MASK
210 config GENERIC_ISA_DMA
216 config NEED_RET_TO_USER
224 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
225 default DRAM_BASE if REMAP_VECTORS_TO_RAM
228 The base address of exception vectors. This must be two pages
231 config ARM_PATCH_PHYS_VIRT
232 bool "Patch physical to virtual translations at runtime" if EMBEDDED
234 depends on !XIP_KERNEL && MMU
235 depends on !ARCH_REALVIEW || !SPARSEMEM
237 Patch phys-to-virt and virt-to-phys translation functions at
238 boot and module load time according to the position of the
239 kernel in system memory.
241 This can only be used with non-XIP MMU kernels where the base
242 of physical memory is at a 16MB boundary.
244 Only disable this option if you know that you do not require
245 this feature (eg, building a kernel for a single machine) and
246 you need to shrink the kernel to the minimal size.
248 config NEED_MACH_GPIO_H
251 Select this when mach/gpio.h is required to provide special
252 definitions for this platform. The need for mach/gpio.h should
253 be avoided when possible.
255 config NEED_MACH_IO_H
258 Select this when mach/io.h is required to provide special
259 definitions for this platform. The need for mach/io.h should
260 be avoided when possible.
262 config NEED_MACH_MEMORY_H
265 Select this when mach/memory.h is required to provide special
266 definitions for this platform. The need for mach/memory.h should
267 be avoided when possible.
270 hex "Physical address of main memory" if MMU
271 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
272 default DRAM_BASE if !MMU
274 Please provide the physical address corresponding to the
275 location of main memory in your system.
281 source "init/Kconfig"
283 source "kernel/Kconfig.freezer"
288 bool "MMU-based Paged Memory Management Support"
291 Select if you want MMU-based virtualised addressing space
292 support by paged memory management. If unsure, say 'Y'.
295 # The "ARM system type" choice list is ordered alphabetically by option
296 # text. Please add new entries in the option alphabetic order.
299 prompt "ARM system type"
300 default ARCH_VERSATILE if !MMU
301 default ARCH_MULTIPLATFORM if MMU
303 config ARCH_MULTIPLATFORM
304 bool "Allow multiple platforms to be selected"
306 select ARM_PATCH_PHYS_VIRT
309 select MULTI_IRQ_HANDLER
313 config ARCH_INTEGRATOR
314 bool "ARM Ltd. Integrator family"
315 select ARCH_HAS_CPUFREQ
318 select COMMON_CLK_VERSATILE
319 select GENERIC_CLOCKEVENTS
322 select MULTI_IRQ_HANDLER
323 select NEED_MACH_MEMORY_H
324 select PLAT_VERSATILE
327 select VERSATILE_FPGA_IRQ
329 Support for ARM's Integrator platform.
332 bool "ARM Ltd. RealView family"
333 select ARCH_WANT_OPTIONAL_GPIOLIB
335 select ARM_TIMER_SP804
337 select COMMON_CLK_VERSATILE
338 select GENERIC_CLOCKEVENTS
339 select GPIO_PL061 if GPIOLIB
341 select NEED_MACH_MEMORY_H
342 select PLAT_VERSATILE
343 select PLAT_VERSATILE_CLCD
345 This enables support for ARM Ltd RealView boards.
347 config ARCH_VERSATILE
348 bool "ARM Ltd. Versatile family"
349 select ARCH_WANT_OPTIONAL_GPIOLIB
351 select ARM_TIMER_SP804
354 select GENERIC_CLOCKEVENTS
355 select HAVE_MACH_CLKDEV
357 select PLAT_VERSATILE
358 select PLAT_VERSATILE_CLCD
359 select PLAT_VERSATILE_CLOCK
360 select VERSATILE_FPGA_IRQ
362 This enables support for ARM Ltd Versatile board.
366 select ARCH_REQUIRE_GPIOLIB
369 select NEED_MACH_GPIO_H
370 select NEED_MACH_IO_H if PCCARD
372 select PINCTRL_AT91 if USE_OF
374 This enables support for systems based on Atmel
375 AT91RM9200 and AT91SAM9* processors.
378 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
379 select ARCH_REQUIRE_GPIOLIB
384 select GENERIC_CLOCKEVENTS
386 select MULTI_IRQ_HANDLER
389 Support for Cirrus Logic 711x/721x/731x based boards.
392 bool "Cortina Systems Gemini"
393 select ARCH_REQUIRE_GPIOLIB
396 select GENERIC_CLOCKEVENTS
398 Support for the Cortina Systems Gemini family SoCs
402 select ARCH_USES_GETTIMEOFFSET
405 select NEED_MACH_IO_H
406 select NEED_MACH_MEMORY_H
409 This is an evaluation board for the StrongARM processor available
410 from Digital. It has limited hardware on-board, including an
411 Ethernet interface, two PCMCIA sockets, two serial ports and a
416 select ARCH_HAS_HOLES_MEMORYMODEL
417 select ARCH_REQUIRE_GPIOLIB
418 select ARCH_USES_GETTIMEOFFSET
423 select NEED_MACH_MEMORY_H
425 This enables support for the Cirrus EP93xx series of CPUs.
427 config ARCH_FOOTBRIDGE
431 select GENERIC_CLOCKEVENTS
433 select NEED_MACH_IO_H if !MMU
434 select NEED_MACH_MEMORY_H
436 Support for systems based on the DC21285 companion chip
437 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
440 bool "Hilscher NetX based"
444 select GENERIC_CLOCKEVENTS
446 This enables support for systems based on the Hilscher NetX Soc
452 select NEED_MACH_MEMORY_H
453 select NEED_RET_TO_USER
458 Support for Intel's IOP13XX (XScale) family of processors.
463 select ARCH_REQUIRE_GPIOLIB
466 select NEED_RET_TO_USER
470 Support for Intel's 80219 and IOP32X (XScale) family of
476 select ARCH_REQUIRE_GPIOLIB
479 select NEED_RET_TO_USER
483 Support for Intel's IOP33X (XScale) family of processors.
488 select ARCH_HAS_DMA_SET_COHERENT_MASK
489 select ARCH_SUPPORTS_BIG_ENDIAN
490 select ARCH_REQUIRE_GPIOLIB
493 select DMABOUNCE if PCI
494 select GENERIC_CLOCKEVENTS
495 select MIGHT_HAVE_PCI
496 select NEED_MACH_IO_H
497 select USB_EHCI_BIG_ENDIAN_DESC
498 select USB_EHCI_BIG_ENDIAN_MMIO
500 Support for Intel's IXP4XX (XScale) family of processors.
504 select ARCH_REQUIRE_GPIOLIB
506 select GENERIC_CLOCKEVENTS
507 select MIGHT_HAVE_PCI
511 select PLAT_ORION_LEGACY
512 select USB_ARCH_HAS_EHCI
514 Support for the Marvell Dove SoC 88AP510
517 bool "Marvell Kirkwood"
518 select ARCH_HAS_CPUFREQ
519 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
526 select PINCTRL_KIRKWOOD
527 select PLAT_ORION_LEGACY
529 Support for the following Marvell Kirkwood series SoCs:
530 88F6180, 88F6192 and 88F6281.
533 bool "Marvell MV78xx0"
534 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
539 select PLAT_ORION_LEGACY
541 Support for the following Marvell MV78xx0 series SoCs:
547 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
552 select PLAT_ORION_LEGACY
554 Support for the following Marvell Orion 5x series SoCs:
555 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
556 Orion-2 (5281), Orion-1-90 (6183).
559 bool "Marvell PXA168/910/MMP2"
561 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_ALLOCATOR
564 select GENERIC_CLOCKEVENTS
567 select MULTI_IRQ_HANDLER
572 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
575 bool "Micrel/Kendin KS8695"
576 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
580 select NEED_MACH_MEMORY_H
582 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
583 System-on-Chip devices.
586 bool "Nuvoton W90X900 CPU"
587 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_CLOCKEVENTS
593 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
594 At present, the w90x900 has been renamed nuc900, regarding
595 the ARM series product line, you can login the following
596 link address to know more.
598 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
599 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
603 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
611 select USB_ARCH_HAS_OHCI
614 Support for the NXP LPC32XX family of processors
617 bool "PXA2xx/PXA3xx-based"
619 select ARCH_HAS_CPUFREQ
621 select ARCH_REQUIRE_GPIOLIB
622 select ARM_CPU_SUSPEND if PM
626 select GENERIC_CLOCKEVENTS
629 select MULTI_IRQ_HANDLER
633 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
637 select ARCH_REQUIRE_GPIOLIB
638 select CLKSRC_OF if OF
640 select GENERIC_CLOCKEVENTS
642 Support for Qualcomm MSM/QSD based systems. This runs on the
643 apps processor of the MSM/QSD and depends on a shared memory
644 interface to the modem processor which runs the baseband
645 stack and controls some vital subsystems
646 (clock and power control, etc).
649 bool "Renesas SH-Mobile / R-Mobile"
650 select ARM_PATCH_PHYS_VIRT
652 select GENERIC_CLOCKEVENTS
653 select HAVE_ARM_SCU if SMP
654 select HAVE_ARM_TWD if SMP
655 select HAVE_MACH_CLKDEV
657 select MIGHT_HAVE_CACHE_L2X0
658 select MULTI_IRQ_HANDLER
661 select PM_GENERIC_DOMAINS if PM
664 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
669 select ARCH_MAY_HAVE_PC_FDC
670 select ARCH_SPARSEMEM_ENABLE
671 select ARCH_USES_GETTIMEOFFSET
674 select HAVE_PATA_PLATFORM
676 select NEED_MACH_IO_H
677 select NEED_MACH_MEMORY_H
681 On the Acorn Risc-PC, Linux can support the internal IDE disk and
682 CD-ROM interface, serial and parallel port, and the floppy drive.
686 select ARCH_HAS_CPUFREQ
688 select ARCH_REQUIRE_GPIOLIB
689 select ARCH_SPARSEMEM_ENABLE
694 select GENERIC_CLOCKEVENTS
697 select NEED_MACH_MEMORY_H
700 Support for StrongARM 11x0 based boards.
703 bool "Samsung S3C24XX SoCs"
704 select ARCH_HAS_CPUFREQ
705 select ARCH_REQUIRE_GPIOLIB
707 select CLKSRC_SAMSUNG_PWM
708 select GENERIC_CLOCKEVENTS
710 select HAVE_S3C2410_I2C if I2C
711 select HAVE_S3C2410_WATCHDOG if WATCHDOG
712 select HAVE_S3C_RTC if RTC_CLASS
713 select MULTI_IRQ_HANDLER
714 select NEED_MACH_IO_H
717 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
718 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
719 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
720 Samsung SMDK2410 development board (and derivatives).
723 bool "Samsung S3C64XX"
724 select ARCH_HAS_CPUFREQ
725 select ARCH_REQUIRE_GPIOLIB
728 select CLKSRC_SAMSUNG_PWM
731 select GENERIC_CLOCKEVENTS
733 select HAVE_S3C2410_I2C if I2C
734 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select PM_GENERIC_DOMAINS
740 select S3C_GPIO_TRACK
742 select SAMSUNG_GPIOLIB_4BIT
743 select SAMSUNG_WAKEMASK
744 select SAMSUNG_WDT_RESET
745 select USB_ARCH_HAS_OHCI
747 Samsung S3C64XX series based systems
750 bool "Samsung S5P6440 S5P6450"
752 select CLKSRC_SAMSUNG_PWM
754 select GENERIC_CLOCKEVENTS
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C2410_WATCHDOG if WATCHDOG
758 select HAVE_S3C_RTC if RTC_CLASS
759 select NEED_MACH_GPIO_H
761 select SAMSUNG_WDT_RESET
763 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
767 bool "Samsung S5PC100"
768 select ARCH_REQUIRE_GPIOLIB
770 select CLKSRC_SAMSUNG_PWM
772 select GENERIC_CLOCKEVENTS
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 select HAVE_S3C_RTC if RTC_CLASS
777 select NEED_MACH_GPIO_H
779 select SAMSUNG_WDT_RESET
781 Samsung S5PC100 series based systems
784 bool "Samsung S5PV210/S5PC110"
785 select ARCH_HAS_CPUFREQ
786 select ARCH_HAS_HOLES_MEMORYMODEL
787 select ARCH_SPARSEMEM_ENABLE
789 select CLKSRC_SAMSUNG_PWM
791 select GENERIC_CLOCKEVENTS
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C2410_WATCHDOG if WATCHDOG
795 select HAVE_S3C_RTC if RTC_CLASS
796 select NEED_MACH_GPIO_H
797 select NEED_MACH_MEMORY_H
800 Samsung S5PV210/S5PC110 series based systems
803 bool "Samsung EXYNOS"
804 select ARCH_HAS_CPUFREQ
805 select ARCH_HAS_HOLES_MEMORYMODEL
806 select ARCH_REQUIRE_GPIOLIB
807 select ARCH_SPARSEMEM_ENABLE
811 select GENERIC_CLOCKEVENTS
812 select HAVE_S3C2410_I2C if I2C
813 select HAVE_S3C2410_WATCHDOG if WATCHDOG
814 select HAVE_S3C_RTC if RTC_CLASS
815 select NEED_MACH_MEMORY_H
819 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
823 select ARCH_HAS_HOLES_MEMORYMODEL
824 select ARCH_REQUIRE_GPIOLIB
826 select GENERIC_ALLOCATOR
827 select GENERIC_CLOCKEVENTS
828 select GENERIC_IRQ_CHIP
834 Support for TI's DaVinci platform.
839 select ARCH_HAS_CPUFREQ
840 select ARCH_HAS_HOLES_MEMORYMODEL
842 select ARCH_REQUIRE_GPIOLIB
845 select GENERIC_CLOCKEVENTS
846 select GENERIC_IRQ_CHIP
849 select NEED_MACH_IO_H if PCCARD
850 select NEED_MACH_MEMORY_H
852 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
856 menu "Multiple platform selection"
857 depends on ARCH_MULTIPLATFORM
859 comment "CPU Core family selection"
861 config ARCH_MULTI_V4T
862 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
863 depends on !ARCH_MULTI_V6_V7
864 select ARCH_MULTI_V4_V5
865 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
866 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
867 CPU_ARM925T || CPU_ARM940T)
870 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
871 depends on !ARCH_MULTI_V6_V7
872 select ARCH_MULTI_V4_V5
873 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
874 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
875 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
877 config ARCH_MULTI_V4_V5
881 bool "ARMv6 based platforms (ARM11)"
882 select ARCH_MULTI_V6_V7
886 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
888 select ARCH_MULTI_V6_V7
891 config ARCH_MULTI_V6_V7
894 config ARCH_MULTI_CPU_AUTO
895 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
901 # This is sorted alphabetically by mach-* pathname. However, plat-*
902 # Kconfigs may be included either alphabetically (according to the
903 # plat- suffix) or along side the corresponding mach-* source.
905 source "arch/arm/mach-mvebu/Kconfig"
907 source "arch/arm/mach-at91/Kconfig"
909 source "arch/arm/mach-bcm/Kconfig"
911 source "arch/arm/mach-bcm2835/Kconfig"
913 source "arch/arm/mach-clps711x/Kconfig"
915 source "arch/arm/mach-cns3xxx/Kconfig"
917 source "arch/arm/mach-davinci/Kconfig"
919 source "arch/arm/mach-dove/Kconfig"
921 source "arch/arm/mach-ep93xx/Kconfig"
923 source "arch/arm/mach-footbridge/Kconfig"
925 source "arch/arm/mach-gemini/Kconfig"
927 source "arch/arm/mach-highbank/Kconfig"
929 source "arch/arm/mach-integrator/Kconfig"
931 source "arch/arm/mach-iop32x/Kconfig"
933 source "arch/arm/mach-iop33x/Kconfig"
935 source "arch/arm/mach-iop13xx/Kconfig"
937 source "arch/arm/mach-ixp4xx/Kconfig"
939 source "arch/arm/mach-keystone/Kconfig"
941 source "arch/arm/mach-kirkwood/Kconfig"
943 source "arch/arm/mach-ks8695/Kconfig"
945 source "arch/arm/mach-msm/Kconfig"
947 source "arch/arm/mach-mv78xx0/Kconfig"
949 source "arch/arm/mach-imx/Kconfig"
951 source "arch/arm/mach-mxs/Kconfig"
953 source "arch/arm/mach-netx/Kconfig"
955 source "arch/arm/mach-nomadik/Kconfig"
957 source "arch/arm/mach-nspire/Kconfig"
959 source "arch/arm/plat-omap/Kconfig"
961 source "arch/arm/mach-omap1/Kconfig"
963 source "arch/arm/mach-omap2/Kconfig"
965 source "arch/arm/mach-orion5x/Kconfig"
967 source "arch/arm/mach-picoxcell/Kconfig"
969 source "arch/arm/mach-pxa/Kconfig"
970 source "arch/arm/plat-pxa/Kconfig"
972 source "arch/arm/mach-mmp/Kconfig"
974 source "arch/arm/mach-realview/Kconfig"
976 source "arch/arm/mach-rockchip/Kconfig"
978 source "arch/arm/mach-sa1100/Kconfig"
980 source "arch/arm/plat-samsung/Kconfig"
982 source "arch/arm/mach-socfpga/Kconfig"
984 source "arch/arm/mach-spear/Kconfig"
986 source "arch/arm/mach-sti/Kconfig"
988 source "arch/arm/mach-s3c24xx/Kconfig"
990 source "arch/arm/mach-s3c64xx/Kconfig"
992 source "arch/arm/mach-s5p64x0/Kconfig"
994 source "arch/arm/mach-s5pc100/Kconfig"
996 source "arch/arm/mach-s5pv210/Kconfig"
998 source "arch/arm/mach-exynos/Kconfig"
1000 source "arch/arm/mach-shmobile/Kconfig"
1002 source "arch/arm/mach-sunxi/Kconfig"
1004 source "arch/arm/mach-prima2/Kconfig"
1006 source "arch/arm/mach-tegra/Kconfig"
1008 source "arch/arm/mach-u300/Kconfig"
1010 source "arch/arm/mach-ux500/Kconfig"
1012 source "arch/arm/mach-versatile/Kconfig"
1014 source "arch/arm/mach-vexpress/Kconfig"
1015 source "arch/arm/plat-versatile/Kconfig"
1017 source "arch/arm/mach-virt/Kconfig"
1019 source "arch/arm/mach-vt8500/Kconfig"
1021 source "arch/arm/mach-w90x900/Kconfig"
1023 source "arch/arm/mach-zynq/Kconfig"
1025 # Definitions to make life easier
1031 select GENERIC_CLOCKEVENTS
1037 select GENERIC_IRQ_CHIP
1040 config PLAT_ORION_LEGACY
1047 config PLAT_VERSATILE
1050 config ARM_TIMER_SP804
1053 select CLKSRC_OF if OF
1055 source arch/arm/mm/Kconfig
1059 default 16 if ARCH_EP93XX
1063 bool "Enable iWMMXt support" if !CPU_PJ4
1064 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1065 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1067 Enable support for iWMMXt context switching at run time if
1068 running on a CPU that supports it.
1070 config MULTI_IRQ_HANDLER
1073 Allow each machine to specify it's own IRQ handler at run time.
1076 source "arch/arm/Kconfig-nommu"
1079 config PJ4B_ERRATA_4742
1080 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1081 depends on CPU_PJ4B && MACH_ARMADA_370
1084 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1085 Event (WFE) IDLE states, a specific timing sensitivity exists between
1086 the retiring WFI/WFE instructions and the newly issued subsequent
1087 instructions. This sensitivity can result in a CPU hang scenario.
1089 The software must insert either a Data Synchronization Barrier (DSB)
1090 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1093 config ARM_ERRATA_326103
1094 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1097 Executing a SWP instruction to read-only memory does not set bit 11
1098 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1099 treat the access as a read, preventing a COW from occurring and
1100 causing the faulting task to livelock.
1102 config ARM_ERRATA_411920
1103 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1104 depends on CPU_V6 || CPU_V6K
1106 Invalidation of the Instruction Cache operation can
1107 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1108 It does not affect the MPCore. This option enables the ARM Ltd.
1109 recommended workaround.
1111 config ARM_ERRATA_430973
1112 bool "ARM errata: Stale prediction on replaced interworking branch"
1115 This option enables the workaround for the 430973 Cortex-A8
1116 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1117 interworking branch is replaced with another code sequence at the
1118 same virtual address, whether due to self-modifying code or virtual
1119 to physical address re-mapping, Cortex-A8 does not recover from the
1120 stale interworking branch prediction. This results in Cortex-A8
1121 executing the new code sequence in the incorrect ARM or Thumb state.
1122 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1123 and also flushes the branch target cache at every context switch.
1124 Note that setting specific bits in the ACTLR register may not be
1125 available in non-secure mode.
1127 config ARM_ERRATA_458693
1128 bool "ARM errata: Processor deadlock when a false hazard is created"
1130 depends on !ARCH_MULTIPLATFORM
1132 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1133 erratum. For very specific sequences of memory operations, it is
1134 possible for a hazard condition intended for a cache line to instead
1135 be incorrectly associated with a different cache line. This false
1136 hazard might then cause a processor deadlock. The workaround enables
1137 the L1 caching of the NEON accesses and disables the PLD instruction
1138 in the ACTLR register. Note that setting specific bits in the ACTLR
1139 register may not be available in non-secure mode.
1141 config ARM_ERRATA_460075
1142 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1144 depends on !ARCH_MULTIPLATFORM
1146 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1147 erratum. Any asynchronous access to the L2 cache may encounter a
1148 situation in which recent store transactions to the L2 cache are lost
1149 and overwritten with stale memory contents from external memory. The
1150 workaround disables the write-allocate mode for the L2 cache via the
1151 ACTLR register. Note that setting specific bits in the ACTLR register
1152 may not be available in non-secure mode.
1154 config ARM_ERRATA_742230
1155 bool "ARM errata: DMB operation may be faulty"
1156 depends on CPU_V7 && SMP
1157 depends on !ARCH_MULTIPLATFORM
1159 This option enables the workaround for the 742230 Cortex-A9
1160 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1161 between two write operations may not ensure the correct visibility
1162 ordering of the two writes. This workaround sets a specific bit in
1163 the diagnostic register of the Cortex-A9 which causes the DMB
1164 instruction to behave as a DSB, ensuring the correct behaviour of
1167 config ARM_ERRATA_742231
1168 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1169 depends on CPU_V7 && SMP
1170 depends on !ARCH_MULTIPLATFORM
1172 This option enables the workaround for the 742231 Cortex-A9
1173 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1174 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1175 accessing some data located in the same cache line, may get corrupted
1176 data due to bad handling of the address hazard when the line gets
1177 replaced from one of the CPUs at the same time as another CPU is
1178 accessing it. This workaround sets specific bits in the diagnostic
1179 register of the Cortex-A9 which reduces the linefill issuing
1180 capabilities of the processor.
1182 config PL310_ERRATA_588369
1183 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1184 depends on CACHE_L2X0
1186 The PL310 L2 cache controller implements three types of Clean &
1187 Invalidate maintenance operations: by Physical Address
1188 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1189 They are architecturally defined to behave as the execution of a
1190 clean operation followed immediately by an invalidate operation,
1191 both performing to the same memory location. This functionality
1192 is not correctly implemented in PL310 as clean lines are not
1193 invalidated as a result of these operations.
1195 config ARM_ERRATA_643719
1196 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1197 depends on CPU_V7 && SMP
1199 This option enables the workaround for the 643719 Cortex-A9 (prior to
1200 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1201 register returns zero when it should return one. The workaround
1202 corrects this value, ensuring cache maintenance operations which use
1203 it behave as intended and avoiding data corruption.
1205 config ARM_ERRATA_720789
1206 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1209 This option enables the workaround for the 720789 Cortex-A9 (prior to
1210 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1211 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1212 As a consequence of this erratum, some TLB entries which should be
1213 invalidated are not, resulting in an incoherency in the system page
1214 tables. The workaround changes the TLB flushing routines to invalidate
1215 entries regardless of the ASID.
1217 config PL310_ERRATA_727915
1218 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1219 depends on CACHE_L2X0
1221 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1222 operation (offset 0x7FC). This operation runs in background so that
1223 PL310 can handle normal accesses while it is in progress. Under very
1224 rare circumstances, due to this erratum, write data can be lost when
1225 PL310 treats a cacheable write transaction during a Clean &
1226 Invalidate by Way operation.
1228 config ARM_ERRATA_743622
1229 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1231 depends on !ARCH_MULTIPLATFORM
1233 This option enables the workaround for the 743622 Cortex-A9
1234 (r2p*) erratum. Under very rare conditions, a faulty
1235 optimisation in the Cortex-A9 Store Buffer may lead to data
1236 corruption. This workaround sets a specific bit in the diagnostic
1237 register of the Cortex-A9 which disables the Store Buffer
1238 optimisation, preventing the defect from occurring. This has no
1239 visible impact on the overall performance or power consumption of the
1242 config ARM_ERRATA_751472
1243 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1245 depends on !ARCH_MULTIPLATFORM
1247 This option enables the workaround for the 751472 Cortex-A9 (prior
1248 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1249 completion of a following broadcasted operation if the second
1250 operation is received by a CPU before the ICIALLUIS has completed,
1251 potentially leading to corrupted entries in the cache or TLB.
1253 config PL310_ERRATA_753970
1254 bool "PL310 errata: cache sync operation may be faulty"
1255 depends on CACHE_PL310
1257 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1259 Under some condition the effect of cache sync operation on
1260 the store buffer still remains when the operation completes.
1261 This means that the store buffer is always asked to drain and
1262 this prevents it from merging any further writes. The workaround
1263 is to replace the normal offset of cache sync operation (0x730)
1264 by another offset targeting an unmapped PL310 register 0x740.
1265 This has the same effect as the cache sync operation: store buffer
1266 drain and waiting for all buffers empty.
1268 config ARM_ERRATA_754322
1269 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1272 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1273 r3p*) erratum. A speculative memory access may cause a page table walk
1274 which starts prior to an ASID switch but completes afterwards. This
1275 can populate the micro-TLB with a stale entry which may be hit with
1276 the new ASID. This workaround places two dsb instructions in the mm
1277 switching code so that no page table walks can cross the ASID switch.
1279 config ARM_ERRATA_754327
1280 bool "ARM errata: no automatic Store Buffer drain"
1281 depends on CPU_V7 && SMP
1283 This option enables the workaround for the 754327 Cortex-A9 (prior to
1284 r2p0) erratum. The Store Buffer does not have any automatic draining
1285 mechanism and therefore a livelock may occur if an external agent
1286 continuously polls a memory location waiting to observe an update.
1287 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1288 written polling loops from denying visibility of updates to memory.
1290 config ARM_ERRATA_364296
1291 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1294 This options enables the workaround for the 364296 ARM1136
1295 r0p2 erratum (possible cache data corruption with
1296 hit-under-miss enabled). It sets the undocumented bit 31 in
1297 the auxiliary control register and the FI bit in the control
1298 register, thus disabling hit-under-miss without putting the
1299 processor into full low interrupt latency mode. ARM11MPCore
1302 config ARM_ERRATA_764369
1303 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1304 depends on CPU_V7 && SMP
1306 This option enables the workaround for erratum 764369
1307 affecting Cortex-A9 MPCore with two or more processors (all
1308 current revisions). Under certain timing circumstances, a data
1309 cache line maintenance operation by MVA targeting an Inner
1310 Shareable memory region may fail to proceed up to either the
1311 Point of Coherency or to the Point of Unification of the
1312 system. This workaround adds a DSB instruction before the
1313 relevant cache maintenance functions and sets a specific bit
1314 in the diagnostic control register of the SCU.
1316 config PL310_ERRATA_769419
1317 bool "PL310 errata: no automatic Store Buffer drain"
1318 depends on CACHE_L2X0
1320 On revisions of the PL310 prior to r3p2, the Store Buffer does
1321 not automatically drain. This can cause normal, non-cacheable
1322 writes to be retained when the memory system is idle, leading
1323 to suboptimal I/O performance for drivers using coherent DMA.
1324 This option adds a write barrier to the cpu_idle loop so that,
1325 on systems with an outer cache, the store buffer is drained
1328 config ARM_ERRATA_775420
1329 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1332 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1333 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1334 operation aborts with MMU exception, it might cause the processor
1335 to deadlock. This workaround puts DSB before executing ISB if
1336 an abort may occur on cache maintenance.
1338 config ARM_ERRATA_798181
1339 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1340 depends on CPU_V7 && SMP
1342 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1343 adequately shooting down all use of the old entries. This
1344 option enables the Linux kernel workaround for this erratum
1345 which sends an IPI to the CPUs that are running the same ASID
1346 as the one being invalidated.
1348 config ARM_ERRATA_773022
1349 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1352 This option enables the workaround for the 773022 Cortex-A15
1353 (up to r0p4) erratum. In certain rare sequences of code, the
1354 loop buffer may deliver incorrect instructions. This
1355 workaround disables the loop buffer to avoid the erratum.
1359 source "arch/arm/common/Kconfig"
1369 Find out whether you have ISA slots on your motherboard. ISA is the
1370 name of a bus system, i.e. the way the CPU talks to the other stuff
1371 inside your box. Other bus systems are PCI, EISA, MicroChannel
1372 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1373 newer boards don't support it. If you have ISA, say Y, otherwise N.
1375 # Select ISA DMA controller support
1380 # Select ISA DMA interface
1385 bool "PCI support" if MIGHT_HAVE_PCI
1387 Find out whether you have a PCI motherboard. PCI is the name of a
1388 bus system, i.e. the way the CPU talks to the other stuff inside
1389 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1390 VESA. If you have PCI, say Y, otherwise N.
1396 config PCI_NANOENGINE
1397 bool "BSE nanoEngine PCI support"
1398 depends on SA1100_NANOENGINE
1400 Enable PCI on the BSE nanoEngine board.
1405 config PCI_HOST_ITE8152
1407 depends on PCI && MACH_ARMCORE
1411 source "drivers/pci/Kconfig"
1412 source "drivers/pci/pcie/Kconfig"
1414 source "drivers/pcmcia/Kconfig"
1418 menu "Kernel Features"
1423 This option should be selected by machines which have an SMP-
1426 The only effect of this option is to make the SMP-related
1427 options available to the user for configuration.
1430 bool "Symmetric Multi-Processing"
1431 depends on CPU_V6K || CPU_V7
1432 depends on GENERIC_CLOCKEVENTS
1434 depends on MMU || ARM_MPU
1436 This enables support for systems with more than one CPU. If you have
1437 a system with only one CPU, like most personal computers, say N. If
1438 you have a system with more than one CPU, say Y.
1440 If you say N here, the kernel will run on single and multiprocessor
1441 machines, but will use only one CPU of a multiprocessor machine. If
1442 you say Y here, the kernel will run on many, but not all, single
1443 processor machines. On a single processor machine, the kernel will
1444 run faster if you say N here.
1446 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1447 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1448 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1450 If you don't know what to do here, say N.
1453 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1454 depends on SMP && !XIP_KERNEL && MMU
1457 SMP kernels contain instructions which fail on non-SMP processors.
1458 Enabling this option allows the kernel to modify itself to make
1459 these instructions safe. Disabling it allows about 1K of space
1462 If you don't know what to do here, say Y.
1464 config ARM_CPU_TOPOLOGY
1465 bool "Support cpu topology definition"
1466 depends on SMP && CPU_V7
1469 Support ARM cpu topology definition. The MPIDR register defines
1470 affinity between processors which is then used to describe the cpu
1471 topology of an ARM System.
1474 bool "Multi-core scheduler support"
1475 depends on ARM_CPU_TOPOLOGY
1477 Multi-core scheduler support improves the CPU scheduler's decision
1478 making when dealing with multi-core CPU chips at a cost of slightly
1479 increased overhead in some places. If unsure say N here.
1482 bool "SMT scheduler support"
1483 depends on ARM_CPU_TOPOLOGY
1485 Improves the CPU scheduler's decision making when dealing with
1486 MultiThreading at a cost of slightly increased overhead in some
1487 places. If unsure say N here.
1492 This option enables support for the ARM system coherency unit
1494 config HAVE_ARM_ARCH_TIMER
1495 bool "Architected timer support"
1497 select ARM_ARCH_TIMER
1498 select GENERIC_CLOCKEVENTS
1500 This option enables support for the ARM architected timer
1505 select CLKSRC_OF if OF
1507 This options enables support for the ARM timer and watchdog unit
1510 bool "Multi-Cluster Power Management"
1511 depends on CPU_V7 && SMP
1513 This option provides the common power management infrastructure
1514 for (multi-)cluster based systems, such as big.LITTLE based
1518 bool "big.LITTLE support (Experimental)"
1519 depends on CPU_V7 && SMP
1522 This option enables support selections for the big.LITTLE
1523 system architecture.
1526 bool "big.LITTLE switcher support"
1527 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1529 select ARM_CPU_SUSPEND
1531 The big.LITTLE "switcher" provides the core functionality to
1532 transparently handle transition between a cluster of A15's
1533 and a cluster of A7's in a big.LITTLE system.
1535 config BL_SWITCHER_DUMMY_IF
1536 tristate "Simple big.LITTLE switcher user interface"
1537 depends on BL_SWITCHER && DEBUG_KERNEL
1539 This is a simple and dummy char dev interface to control
1540 the big.LITTLE switcher core code. It is meant for
1541 debugging purposes only.
1544 prompt "Memory split"
1547 Select the desired split between kernel and user memory.
1549 If you are not absolutely sure what you are doing, leave this
1553 bool "3G/1G user/kernel split"
1555 bool "2G/2G user/kernel split"
1557 bool "1G/3G user/kernel split"
1562 default 0x40000000 if VMSPLIT_1G
1563 default 0x80000000 if VMSPLIT_2G
1567 int "Maximum number of CPUs (2-32)"
1573 bool "Support for hot-pluggable CPUs"
1576 Say Y here to experiment with turning CPUs off and on. CPUs
1577 can be controlled through /sys/devices/system/cpu.
1580 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1583 Say Y here if you want Linux to communicate with system firmware
1584 implementing the PSCI specification for CPU-centric power
1585 management operations described in ARM document number ARM DEN
1586 0022A ("Power State Coordination Interface System Software on
1589 # The GPIO number here must be sorted by descending number. In case of
1590 # a multiplatform kernel, we just want the highest value required by the
1591 # selected platforms.
1594 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1595 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1596 default 392 if ARCH_U8500
1597 default 352 if ARCH_VT8500
1598 default 288 if ARCH_SUNXI
1599 default 264 if MACH_H4700
1602 Maximum number of GPIOs in the system.
1604 If unsure, leave the default value.
1606 source kernel/Kconfig.preempt
1610 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1611 ARCH_S5PV210 || ARCH_EXYNOS4
1612 default AT91_TIMER_HZ if ARCH_AT91
1613 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1617 depends on HZ_FIXED = 0
1618 prompt "Timer frequency"
1642 default HZ_FIXED if HZ_FIXED != 0
1643 default 100 if HZ_100
1644 default 200 if HZ_200
1645 default 250 if HZ_250
1646 default 300 if HZ_300
1647 default 500 if HZ_500
1651 def_bool HIGH_RES_TIMERS
1654 def_bool HIGH_RES_TIMERS
1656 config THUMB2_KERNEL
1657 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1658 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1659 default y if CPU_THUMBONLY
1661 select ARM_ASM_UNIFIED
1664 By enabling this option, the kernel will be compiled in
1665 Thumb-2 mode. A compiler/assembler that understand the unified
1666 ARM-Thumb syntax is needed.
1670 config THUMB2_AVOID_R_ARM_THM_JUMP11
1671 bool "Work around buggy Thumb-2 short branch relocations in gas"
1672 depends on THUMB2_KERNEL && MODULES
1675 Various binutils versions can resolve Thumb-2 branches to
1676 locally-defined, preemptible global symbols as short-range "b.n"
1677 branch instructions.
1679 This is a problem, because there's no guarantee the final
1680 destination of the symbol, or any candidate locations for a
1681 trampoline, are within range of the branch. For this reason, the
1682 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1683 relocation in modules at all, and it makes little sense to add
1686 The symptom is that the kernel fails with an "unsupported
1687 relocation" error when loading some modules.
1689 Until fixed tools are available, passing
1690 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1691 code which hits this problem, at the cost of a bit of extra runtime
1692 stack usage in some cases.
1694 The problem is described in more detail at:
1695 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1697 Only Thumb-2 kernels are affected.
1699 Unless you are sure your tools don't have this problem, say Y.
1701 config ARM_ASM_UNIFIED
1705 bool "Use the ARM EABI to compile the kernel"
1707 This option allows for the kernel to be compiled using the latest
1708 ARM ABI (aka EABI). This is only useful if you are using a user
1709 space environment that is also compiled with EABI.
1711 Since there are major incompatibilities between the legacy ABI and
1712 EABI, especially with regard to structure member alignment, this
1713 option also changes the kernel syscall calling convention to
1714 disambiguate both ABIs and allow for backward compatibility support
1715 (selected with CONFIG_OABI_COMPAT).
1717 To use this you need GCC version 4.0.0 or later.
1720 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1721 depends on AEABI && !THUMB2_KERNEL
1723 This option preserves the old syscall interface along with the
1724 new (ARM EABI) one. It also provides a compatibility layer to
1725 intercept syscalls that have structure arguments which layout
1726 in memory differs between the legacy ABI and the new ARM EABI
1727 (only for non "thumb" binaries). This option adds a tiny
1728 overhead to all syscalls and produces a slightly larger kernel.
1730 The seccomp filter system will not be available when this is
1731 selected, since there is no way yet to sensibly distinguish
1732 between calling conventions during filtering.
1734 If you know you'll be using only pure EABI user space then you
1735 can say N here. If this option is not selected and you attempt
1736 to execute a legacy ABI binary then the result will be
1737 UNPREDICTABLE (in fact it can be predicted that it won't work
1738 at all). If in doubt say N.
1740 config ARCH_HAS_HOLES_MEMORYMODEL
1743 config ARCH_SPARSEMEM_ENABLE
1746 config ARCH_SPARSEMEM_DEFAULT
1747 def_bool ARCH_SPARSEMEM_ENABLE
1749 config ARCH_SELECT_MEMORY_MODEL
1750 def_bool ARCH_SPARSEMEM_ENABLE
1752 config HAVE_ARCH_PFN_VALID
1753 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1756 bool "High Memory Support"
1759 The address space of ARM processors is only 4 Gigabytes large
1760 and it has to accommodate user address space, kernel address
1761 space as well as some memory mapped IO. That means that, if you
1762 have a large amount of physical memory and/or IO, not all of the
1763 memory can be "permanently mapped" by the kernel. The physical
1764 memory that is not permanently mapped is called "high memory".
1766 Depending on the selected kernel/user memory split, minimum
1767 vmalloc space and actual amount of RAM, you may not need this
1768 option which should result in a slightly faster kernel.
1773 bool "Allocate 2nd-level pagetables from highmem"
1776 config HW_PERF_EVENTS
1777 bool "Enable hardware performance counter support for perf events"
1778 depends on PERF_EVENTS
1781 Enable hardware performance counter support for perf events. If
1782 disabled, perf events will use software events only.
1784 config SYS_SUPPORTS_HUGETLBFS
1788 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1792 config ARCH_WANT_GENERAL_HUGETLB
1797 config FORCE_MAX_ZONEORDER
1798 int "Maximum zone order" if ARCH_SHMOBILE
1799 range 11 64 if ARCH_SHMOBILE
1800 default "12" if SOC_AM33XX
1801 default "9" if SA1111
1804 The kernel memory allocator divides physically contiguous memory
1805 blocks into "zones", where each zone is a power of two number of
1806 pages. This option selects the largest power of two that the kernel
1807 keeps in the memory allocator. If you need to allocate very large
1808 blocks of physically contiguous memory, then you may need to
1809 increase this value.
1811 This config option is actually maximum order plus one. For example,
1812 a value of 11 means that the largest free memory block is 2^10 pages.
1814 config ALIGNMENT_TRAP
1816 depends on CPU_CP15_MMU
1817 default y if !ARCH_EBSA110
1818 select HAVE_PROC_CPU if PROC_FS
1820 ARM processors cannot fetch/store information which is not
1821 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1822 address divisible by 4. On 32-bit ARM processors, these non-aligned
1823 fetch/store instructions will be emulated in software if you say
1824 here, which has a severe performance impact. This is necessary for
1825 correct operation of some network protocols. With an IP-only
1826 configuration it is safe to say N, otherwise say Y.
1828 config UACCESS_WITH_MEMCPY
1829 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1831 default y if CPU_FEROCEON
1833 Implement faster copy_to_user and clear_user methods for CPU
1834 cores where a 8-word STM instruction give significantly higher
1835 memory write throughput than a sequence of individual 32bit stores.
1837 A possible side effect is a slight increase in scheduling latency
1838 between threads sharing the same address space if they invoke
1839 such copy operations with large buffers.
1841 However, if the CPU data cache is using a write-allocate mode,
1842 this option is unlikely to provide any performance gain.
1846 prompt "Enable seccomp to safely compute untrusted bytecode"
1848 This kernel feature is useful for number crunching applications
1849 that may need to compute untrusted bytecode during their
1850 execution. By using pipes or other transports made available to
1851 the process as file descriptors supporting the read/write
1852 syscalls, it's possible to isolate those applications in
1853 their own address space using seccomp. Once seccomp is
1854 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1855 and the task is only allowed to execute a few safe syscalls
1856 defined by each seccomp mode.
1869 bool "Xen guest support on ARM (EXPERIMENTAL)"
1870 depends on ARM && AEABI && OF
1871 depends on CPU_V7 && !CPU_V6
1872 depends on !GENERIC_ATOMIC64
1876 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1883 bool "Flattened Device Tree support"
1886 select OF_EARLY_FLATTREE
1888 Include support for flattened device tree machine descriptions.
1891 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1894 This is the traditional way of passing data to the kernel at boot
1895 time. If you are solely relying on the flattened device tree (or
1896 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1897 to remove ATAGS support from your kernel binary. If unsure,
1900 config DEPRECATED_PARAM_STRUCT
1901 bool "Provide old way to pass kernel parameters"
1904 This was deprecated in 2001 and announced to live on for 5 years.
1905 Some old boot loaders still use this way.
1907 # Compressed boot loader in ROM. Yes, we really want to ask about
1908 # TEXT and BSS so we preserve their values in the config files.
1909 config ZBOOT_ROM_TEXT
1910 hex "Compressed ROM boot loader base address"
1913 The physical address at which the ROM-able zImage is to be
1914 placed in the target. Platforms which normally make use of
1915 ROM-able zImage formats normally set this to a suitable
1916 value in their defconfig file.
1918 If ZBOOT_ROM is not enabled, this has no effect.
1920 config ZBOOT_ROM_BSS
1921 hex "Compressed ROM boot loader BSS address"
1924 The base address of an area of read/write memory in the target
1925 for the ROM-able zImage which must be available while the
1926 decompressor is running. It must be large enough to hold the
1927 entire decompressed kernel plus an additional 128 KiB.
1928 Platforms which normally make use of ROM-able zImage formats
1929 normally set this to a suitable value in their defconfig file.
1931 If ZBOOT_ROM is not enabled, this has no effect.
1934 bool "Compressed boot loader in ROM/flash"
1935 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1937 Say Y here if you intend to execute your compressed kernel image
1938 (zImage) directly from ROM or flash. If unsure, say N.
1941 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1942 depends on ZBOOT_ROM && ARCH_SH7372
1943 default ZBOOT_ROM_NONE
1945 Include experimental SD/MMC loading code in the ROM-able zImage.
1946 With this enabled it is possible to write the ROM-able zImage
1947 kernel image to an MMC or SD card and boot the kernel straight
1948 from the reset vector. At reset the processor Mask ROM will load
1949 the first part of the ROM-able zImage which in turn loads the
1950 rest the kernel image to RAM.
1952 config ZBOOT_ROM_NONE
1953 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1955 Do not load image from SD or MMC
1957 config ZBOOT_ROM_MMCIF
1958 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1960 Load image from MMCIF hardware block.
1962 config ZBOOT_ROM_SH_MOBILE_SDHI
1963 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1965 Load image from SDHI hardware block
1969 config ARM_APPENDED_DTB
1970 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1971 depends on OF && !ZBOOT_ROM
1973 With this option, the boot code will look for a device tree binary
1974 (DTB) appended to zImage
1975 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1977 This is meant as a backward compatibility convenience for those
1978 systems with a bootloader that can't be upgraded to accommodate
1979 the documented boot protocol using a device tree.
1981 Beware that there is very little in terms of protection against
1982 this option being confused by leftover garbage in memory that might
1983 look like a DTB header after a reboot if no actual DTB is appended
1984 to zImage. Do not leave this option active in a production kernel
1985 if you don't intend to always append a DTB. Proper passing of the
1986 location into r2 of a bootloader provided DTB is always preferable
1989 config ARM_ATAG_DTB_COMPAT
1990 bool "Supplement the appended DTB with traditional ATAG information"
1991 depends on ARM_APPENDED_DTB
1993 Some old bootloaders can't be updated to a DTB capable one, yet
1994 they provide ATAGs with memory configuration, the ramdisk address,
1995 the kernel cmdline string, etc. Such information is dynamically
1996 provided by the bootloader and can't always be stored in a static
1997 DTB. To allow a device tree enabled kernel to be used with such
1998 bootloaders, this option allows zImage to extract the information
1999 from the ATAG list and store it at run time into the appended DTB.
2002 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2003 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2005 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2006 bool "Use bootloader kernel arguments if available"
2008 Uses the command-line options passed by the boot loader instead of
2009 the device tree bootargs property. If the boot loader doesn't provide
2010 any, the device tree bootargs property will be used.
2012 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2013 bool "Extend with bootloader kernel arguments"
2015 The command-line arguments provided by the boot loader will be
2016 appended to the the device tree bootargs property.
2021 string "Default kernel command string"
2024 On some architectures (EBSA110 and CATS), there is currently no way
2025 for the boot loader to pass arguments to the kernel. For these
2026 architectures, you should supply some command-line options at build
2027 time by entering them here. As a minimum, you should specify the
2028 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2031 prompt "Kernel command line type" if CMDLINE != ""
2032 default CMDLINE_FROM_BOOTLOADER
2035 config CMDLINE_FROM_BOOTLOADER
2036 bool "Use bootloader kernel arguments if available"
2038 Uses the command-line options passed by the boot loader. If
2039 the boot loader doesn't provide any, the default kernel command
2040 string provided in CMDLINE will be used.
2042 config CMDLINE_EXTEND
2043 bool "Extend bootloader kernel arguments"
2045 The command-line arguments provided by the boot loader will be
2046 appended to the default kernel command string.
2048 config CMDLINE_FORCE
2049 bool "Always use the default kernel command string"
2051 Always use the default kernel command string, even if the boot
2052 loader passes other arguments to the kernel.
2053 This is useful if you cannot or don't want to change the
2054 command-line options your boot loader passes to the kernel.
2058 bool "Kernel Execute-In-Place from ROM"
2059 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2061 Execute-In-Place allows the kernel to run from non-volatile storage
2062 directly addressable by the CPU, such as NOR flash. This saves RAM
2063 space since the text section of the kernel is not loaded from flash
2064 to RAM. Read-write sections, such as the data section and stack,
2065 are still copied to RAM. The XIP kernel is not compressed since
2066 it has to run directly from flash, so it will take more space to
2067 store it. The flash address used to link the kernel object files,
2068 and for storing it, is configuration dependent. Therefore, if you
2069 say Y here, you must know the proper physical address where to
2070 store the kernel image depending on your own flash memory usage.
2072 Also note that the make target becomes "make xipImage" rather than
2073 "make zImage" or "make Image". The final kernel binary to put in
2074 ROM memory will be arch/arm/boot/xipImage.
2078 config XIP_PHYS_ADDR
2079 hex "XIP Kernel Physical Location"
2080 depends on XIP_KERNEL
2081 default "0x00080000"
2083 This is the physical address in your flash memory the kernel will
2084 be linked for and stored to. This address is dependent on your
2088 bool "Kexec system call (EXPERIMENTAL)"
2089 depends on (!SMP || PM_SLEEP_SMP)
2091 kexec is a system call that implements the ability to shutdown your
2092 current kernel, and to start another kernel. It is like a reboot
2093 but it is independent of the system firmware. And like a reboot
2094 you can start any kernel with it, not just Linux.
2096 It is an ongoing process to be certain the hardware in a machine
2097 is properly shutdown, so do not be surprised if this code does not
2098 initially work for you.
2101 bool "Export atags in procfs"
2102 depends on ATAGS && KEXEC
2105 Should the atags used to boot the kernel be exported in an "atags"
2106 file in procfs. Useful with kexec.
2109 bool "Build kdump crash kernel (EXPERIMENTAL)"
2111 Generate crash dump after being started by kexec. This should
2112 be normally only set in special crash dump kernels which are
2113 loaded in the main kernel with kexec-tools into a specially
2114 reserved region and then later executed after a crash by
2115 kdump/kexec. The crash dump kernel must be compiled to a
2116 memory address not used by the main kernel
2118 For more details see Documentation/kdump/kdump.txt
2120 config AUTO_ZRELADDR
2121 bool "Auto calculation of the decompressed kernel image address"
2122 depends on !ZBOOT_ROM
2124 ZRELADDR is the physical address where the decompressed kernel
2125 image will be placed. If AUTO_ZRELADDR is selected, the address
2126 will be determined at run-time by masking the current IP with
2127 0xf8000000. This assumes the zImage being placed in the first 128MB
2128 from start of memory.
2132 menu "CPU Power Management"
2135 source "drivers/cpufreq/Kconfig"
2138 source "drivers/cpuidle/Kconfig"
2142 menu "Floating point emulation"
2144 comment "At least one emulation must be selected"
2147 bool "NWFPE math emulation"
2148 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2150 Say Y to include the NWFPE floating point emulator in the kernel.
2151 This is necessary to run most binaries. Linux does not currently
2152 support floating point hardware so you need to say Y here even if
2153 your machine has an FPA or floating point co-processor podule.
2155 You may say N here if you are going to load the Acorn FPEmulator
2156 early in the bootup.
2159 bool "Support extended precision"
2160 depends on FPE_NWFPE
2162 Say Y to include 80-bit support in the kernel floating-point
2163 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2164 Note that gcc does not generate 80-bit operations by default,
2165 so in most cases this option only enlarges the size of the
2166 floating point emulator without any good reason.
2168 You almost surely want to say N here.
2171 bool "FastFPE math emulation (EXPERIMENTAL)"
2172 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2174 Say Y here to include the FAST floating point emulator in the kernel.
2175 This is an experimental much faster emulator which now also has full
2176 precision for the mantissa. It does not support any exceptions.
2177 It is very simple, and approximately 3-6 times faster than NWFPE.
2179 It should be sufficient for most programs. It may be not suitable
2180 for scientific calculations, but you have to check this for yourself.
2181 If you do not feel you need a faster FP emulation you should better
2185 bool "VFP-format floating point maths"
2186 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2188 Say Y to include VFP support code in the kernel. This is needed
2189 if your hardware includes a VFP unit.
2191 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2192 release notes and additional status information.
2194 Say N if your target does not have VFP hardware.
2202 bool "Advanced SIMD (NEON) Extension support"
2203 depends on VFPv3 && CPU_V7
2205 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2208 config KERNEL_MODE_NEON
2209 bool "Support for NEON in kernel mode"
2210 depends on NEON && AEABI
2212 Say Y to include support for NEON in kernel mode.
2216 menu "Userspace binary formats"
2218 source "fs/Kconfig.binfmt"
2221 tristate "RISC OS personality"
2224 Say Y here to include the kernel code necessary if you want to run
2225 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2226 experimental; if this sounds frightening, say N and sleep in peace.
2227 You can also say M here to compile this support as a module (which
2228 will be called arthur).
2232 menu "Power management options"
2234 source "kernel/power/Kconfig"
2236 config ARCH_SUSPEND_POSSIBLE
2237 depends on !ARCH_S5PC100
2238 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2239 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2242 config ARM_CPU_SUSPEND
2247 source "net/Kconfig"
2249 source "drivers/Kconfig"
2253 source "arch/arm/Kconfig.debug"
2255 source "security/Kconfig"
2257 source "crypto/Kconfig"
2259 source "lib/Kconfig"
2261 source "arch/arm/kvm/Kconfig"