4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
59 config NEED_SG_DMA_LENGTH
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
73 config SYS_SUPPORTS_APM_EMULATION
81 select GENERIC_ALLOCATOR
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config GENERIC_LOCKBREAK
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
254 bool "Altera SOCFPGA family"
255 select ARCH_WANT_OPTIONAL_GPIOLIB
263 select DW_APB_TIMER_OF
264 select GENERIC_CLOCKEVENTS
265 select GPIO_PL061 if GPIOLIB
270 This enables support for Altera SOCFPGA Cyclone V platform
272 config ARCH_INTEGRATOR
273 bool "ARM Ltd. Integrator family"
275 select ARCH_HAS_CPUFREQ
280 select GENERIC_CLOCKEVENTS
281 select PLAT_VERSATILE
282 select PLAT_VERSATILE_CLOCK
283 select PLAT_VERSATILE_FPGA_IRQ
284 select NEED_MACH_IO_H
285 select NEED_MACH_MEMORY_H
287 select MULTI_IRQ_HANDLER
289 Support for ARM's Integrator platform.
292 bool "ARM Ltd. RealView family"
295 select HAVE_MACH_CLKDEV
297 select GENERIC_CLOCKEVENTS
298 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select PLAT_VERSATILE
300 select PLAT_VERSATILE_CLOCK
301 select PLAT_VERSATILE_CLCD
302 select ARM_TIMER_SP804
303 select GPIO_PL061 if GPIOLIB
304 select NEED_MACH_MEMORY_H
306 This enables support for ARM Ltd RealView boards.
308 config ARCH_VERSATILE
309 bool "ARM Ltd. Versatile family"
313 select HAVE_MACH_CLKDEV
315 select GENERIC_CLOCKEVENTS
316 select ARCH_WANT_OPTIONAL_GPIOLIB
317 select NEED_MACH_IO_H if PCI
318 select PLAT_VERSATILE
319 select PLAT_VERSATILE_CLOCK
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_FPGA_IRQ
322 select ARM_TIMER_SP804
324 This enables support for ARM Ltd Versatile board.
327 bool "ARM Ltd. Versatile Express family"
328 select ARCH_WANT_OPTIONAL_GPIOLIB
330 select ARM_TIMER_SP804
333 select GENERIC_CLOCKEVENTS
335 select HAVE_PATA_PLATFORM
338 select PLAT_VERSATILE
339 select PLAT_VERSATILE_CLOCK
340 select PLAT_VERSATILE_CLCD
341 select REGULATOR_FIXED_VOLTAGE if REGULATOR
343 This enables support for the ARM Ltd Versatile Express boards.
347 select ARCH_REQUIRE_GPIOLIB
351 select NEED_MACH_IO_H if PCCARD
353 This enables support for systems based on Atmel
354 AT91RM9200 and AT91SAM9* processors.
357 bool "Broadcom BCMRING"
361 select ARM_TIMER_SP804
363 select GENERIC_CLOCKEVENTS
364 select ARCH_WANT_OPTIONAL_GPIOLIB
366 Support for Broadcom's BCMRing platform.
369 bool "Calxeda Highbank-based"
370 select ARCH_WANT_OPTIONAL_GPIOLIB
373 select ARM_TIMER_SP804
378 select GENERIC_CLOCKEVENTS
384 Support for the Calxeda Highbank SoC based boards.
387 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
389 select ARCH_USES_GETTIMEOFFSET
390 select NEED_MACH_MEMORY_H
392 Support for Cirrus Logic 711x/721x/731x based boards.
395 bool "Cavium Networks CNS3XXX family"
397 select GENERIC_CLOCKEVENTS
399 select MIGHT_HAVE_CACHE_L2X0
400 select MIGHT_HAVE_PCI
401 select PCI_DOMAINS if PCI
403 Support for Cavium Networks CNS3XXX platform.
406 bool "Cortina Systems Gemini"
408 select ARCH_REQUIRE_GPIOLIB
409 select ARCH_USES_GETTIMEOFFSET
411 Support for the Cortina Systems Gemini family SoCs
414 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
417 select ARCH_REQUIRE_GPIOLIB
418 select GENERIC_CLOCKEVENTS
420 select GENERIC_IRQ_CHIP
421 select MIGHT_HAVE_CACHE_L2X0
427 Support for CSR SiRFSoC ARM Cortex A9 Platform
434 select ARCH_USES_GETTIMEOFFSET
435 select NEED_MACH_IO_H
436 select NEED_MACH_MEMORY_H
438 This is an evaluation board for the StrongARM processor available
439 from Digital. It has limited hardware on-board, including an
440 Ethernet interface, two PCMCIA sockets, two serial ports and a
449 select ARCH_REQUIRE_GPIOLIB
450 select ARCH_HAS_HOLES_MEMORYMODEL
451 select ARCH_USES_GETTIMEOFFSET
452 select NEED_MACH_MEMORY_H
454 This enables support for the Cirrus EP93xx series of CPUs.
456 config ARCH_FOOTBRIDGE
460 select GENERIC_CLOCKEVENTS
462 select NEED_MACH_IO_H
463 select NEED_MACH_MEMORY_H
465 Support for systems based on the DC21285 companion chip
466 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
469 bool "Freescale MXC/iMX-based"
470 select GENERIC_CLOCKEVENTS
471 select ARCH_REQUIRE_GPIOLIB
474 select GENERIC_IRQ_CHIP
475 select MULTI_IRQ_HANDLER
479 Support for Freescale MXC/iMX-based family of processors
482 bool "Freescale MXS-based"
483 select GENERIC_CLOCKEVENTS
484 select ARCH_REQUIRE_GPIOLIB
488 select HAVE_CLK_PREPARE
492 Support for Freescale MXS-based family of processors
495 bool "Hilscher NetX based"
499 select GENERIC_CLOCKEVENTS
501 This enables support for systems based on the Hilscher NetX Soc
504 bool "Hynix HMS720x-based"
507 select ARCH_USES_GETTIMEOFFSET
509 This enables support for systems based on the Hynix HMS720x
517 select ARCH_SUPPORTS_MSI
519 select NEED_MACH_IO_H
520 select NEED_MACH_MEMORY_H
521 select NEED_RET_TO_USER
523 Support for Intel's IOP13XX (XScale) family of processors.
529 select NEED_MACH_IO_H
530 select NEED_RET_TO_USER
533 select ARCH_REQUIRE_GPIOLIB
535 Support for Intel's 80219 and IOP32X (XScale) family of
542 select NEED_MACH_IO_H
543 select NEED_RET_TO_USER
546 select ARCH_REQUIRE_GPIOLIB
548 Support for Intel's IOP33X (XScale) family of processors.
553 select ARCH_HAS_DMA_SET_COHERENT_MASK
556 select ARCH_REQUIRE_GPIOLIB
557 select GENERIC_CLOCKEVENTS
558 select MIGHT_HAVE_PCI
559 select NEED_MACH_IO_H
560 select DMABOUNCE if PCI
562 Support for Intel's IXP4XX (XScale) family of processors.
565 bool "Marvell SOCs with Device Tree support"
566 select GENERIC_CLOCKEVENTS
567 select MULTI_IRQ_HANDLER
570 select GENERIC_IRQ_CHIP
574 Support for the Marvell SoC Family with device tree support
580 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
582 select NEED_MACH_IO_H
585 Support for the Marvell Dove SoC 88AP510
588 bool "Marvell Kirkwood"
591 select ARCH_REQUIRE_GPIOLIB
592 select GENERIC_CLOCKEVENTS
593 select NEED_MACH_IO_H
596 Support for the following Marvell Kirkwood series SoCs:
597 88F6180, 88F6192 and 88F6281.
603 select ARCH_REQUIRE_GPIOLIB
606 select USB_ARCH_HAS_OHCI
608 select GENERIC_CLOCKEVENTS
612 Support for the NXP LPC32XX family of processors
615 bool "Marvell MV78xx0"
618 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
620 select NEED_MACH_IO_H
623 Support for the following Marvell MV78xx0 series SoCs:
631 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
633 select NEED_MACH_IO_H
636 Support for the following Marvell Orion 5x series SoCs:
637 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
638 Orion-2 (5281), Orion-1-90 (6183).
641 bool "Marvell PXA168/910/MMP2"
643 select ARCH_REQUIRE_GPIOLIB
645 select GENERIC_CLOCKEVENTS
650 select GENERIC_ALLOCATOR
652 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
655 bool "Micrel/Kendin KS8695"
657 select ARCH_REQUIRE_GPIOLIB
658 select ARCH_USES_GETTIMEOFFSET
659 select NEED_MACH_MEMORY_H
661 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
662 System-on-Chip devices.
665 bool "Nuvoton W90X900 CPU"
667 select ARCH_REQUIRE_GPIOLIB
670 select GENERIC_CLOCKEVENTS
672 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
673 At present, the w90x900 has been renamed nuc900, regarding
674 the ARM series product line, you can login the following
675 link address to know more.
677 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
678 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
684 select GENERIC_CLOCKEVENTS
688 select MIGHT_HAVE_CACHE_L2X0
689 select NEED_MACH_IO_H if PCI
690 select ARCH_HAS_CPUFREQ
693 This enables support for NVIDIA Tegra based systems (Tegra APX,
694 Tegra 6xx and Tegra 2 series).
696 config ARCH_PICOXCELL
697 bool "Picochip picoXcell"
698 select ARCH_REQUIRE_GPIOLIB
699 select ARM_PATCH_PHYS_VIRT
703 select DW_APB_TIMER_OF
704 select GENERIC_CLOCKEVENTS
711 This enables support for systems based on the Picochip picoXcell
712 family of Femtocell devices. The picoxcell support requires device tree
716 bool "Philips Nexperia PNX4008 Mobile"
719 select ARCH_USES_GETTIMEOFFSET
721 This enables support for Philips PNX4008 mobile platform.
724 bool "PXA2xx/PXA3xx-based"
727 select ARCH_HAS_CPUFREQ
730 select ARCH_REQUIRE_GPIOLIB
731 select GENERIC_CLOCKEVENTS
736 select MULTI_IRQ_HANDLER
737 select ARM_CPU_SUSPEND if PM
740 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
745 select GENERIC_CLOCKEVENTS
746 select ARCH_REQUIRE_GPIOLIB
749 Support for Qualcomm MSM/QSD based systems. This runs on the
750 apps processor of the MSM/QSD and depends on a shared memory
751 interface to the modem processor which runs the baseband
752 stack and controls some vital subsystems
753 (clock and power control, etc).
756 bool "Renesas SH-Mobile / R-Mobile"
759 select HAVE_MACH_CLKDEV
761 select GENERIC_CLOCKEVENTS
762 select MIGHT_HAVE_CACHE_L2X0
765 select MULTI_IRQ_HANDLER
766 select PM_GENERIC_DOMAINS if PM
767 select NEED_MACH_MEMORY_H
769 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
775 select ARCH_MAY_HAVE_PC_FDC
776 select HAVE_PATA_PLATFORM
779 select ARCH_SPARSEMEM_ENABLE
780 select ARCH_USES_GETTIMEOFFSET
782 select NEED_MACH_IO_H
783 select NEED_MACH_MEMORY_H
785 On the Acorn Risc-PC, Linux can support the internal IDE disk and
786 CD-ROM interface, serial and parallel port, and the floppy drive.
793 select ARCH_SPARSEMEM_ENABLE
795 select ARCH_HAS_CPUFREQ
797 select GENERIC_CLOCKEVENTS
799 select ARCH_REQUIRE_GPIOLIB
801 select NEED_MACH_MEMORY_H
804 Support for StrongARM 11x0 based boards.
807 bool "Samsung S3C24XX SoCs"
809 select ARCH_HAS_CPUFREQ
812 select ARCH_USES_GETTIMEOFFSET
813 select HAVE_S3C2410_I2C if I2C
814 select HAVE_S3C_RTC if RTC_CLASS
815 select HAVE_S3C2410_WATCHDOG if WATCHDOG
816 select NEED_MACH_IO_H
818 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
819 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
820 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
821 Samsung SMDK2410 development board (and derivatives).
824 bool "Samsung S3C64XX"
832 select ARCH_USES_GETTIMEOFFSET
833 select ARCH_HAS_CPUFREQ
834 select ARCH_REQUIRE_GPIOLIB
835 select SAMSUNG_CLKSRC
836 select SAMSUNG_IRQ_VIC_TIMER
837 select S3C_GPIO_TRACK
839 select USB_ARCH_HAS_OHCI
840 select SAMSUNG_GPIOLIB_4BIT
841 select HAVE_S3C2410_I2C if I2C
842 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 Samsung S3C64XX series based systems
847 bool "Samsung S5P6440 S5P6450"
853 select HAVE_S3C2410_WATCHDOG if WATCHDOG
854 select GENERIC_CLOCKEVENTS
855 select HAVE_S3C2410_I2C if I2C
856 select HAVE_S3C_RTC if RTC_CLASS
858 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
862 bool "Samsung S5PC100"
867 select ARCH_USES_GETTIMEOFFSET
868 select HAVE_S3C2410_I2C if I2C
869 select HAVE_S3C_RTC if RTC_CLASS
870 select HAVE_S3C2410_WATCHDOG if WATCHDOG
872 Samsung S5PC100 series based systems
875 bool "Samsung S5PV210/S5PC110"
877 select ARCH_SPARSEMEM_ENABLE
878 select ARCH_HAS_HOLES_MEMORYMODEL
883 select ARCH_HAS_CPUFREQ
884 select GENERIC_CLOCKEVENTS
885 select HAVE_S3C2410_I2C if I2C
886 select HAVE_S3C_RTC if RTC_CLASS
887 select HAVE_S3C2410_WATCHDOG if WATCHDOG
888 select NEED_MACH_MEMORY_H
890 Samsung S5PV210/S5PC110 series based systems
893 bool "SAMSUNG EXYNOS"
895 select ARCH_SPARSEMEM_ENABLE
896 select ARCH_HAS_HOLES_MEMORYMODEL
900 select ARCH_HAS_CPUFREQ
901 select GENERIC_CLOCKEVENTS
902 select HAVE_S3C_RTC if RTC_CLASS
903 select HAVE_S3C2410_I2C if I2C
904 select HAVE_S3C2410_WATCHDOG if WATCHDOG
905 select NEED_MACH_MEMORY_H
907 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
916 select ARCH_USES_GETTIMEOFFSET
917 select NEED_MACH_MEMORY_H
918 select NEED_MACH_IO_H
920 Support for the StrongARM based Digital DNARD machine, also known
921 as "Shark" (<http://www.shark-linux.de/shark.html>).
924 bool "ST-Ericsson U300 Series"
930 select ARM_PATCH_PHYS_VIRT
932 select GENERIC_CLOCKEVENTS
936 select ARCH_REQUIRE_GPIOLIB
938 Support for ST-Ericsson U300 series mobile platforms.
941 bool "ST-Ericsson U8500 Series"
945 select GENERIC_CLOCKEVENTS
947 select ARCH_REQUIRE_GPIOLIB
948 select ARCH_HAS_CPUFREQ
950 select MIGHT_HAVE_CACHE_L2X0
952 Support for ST-Ericsson's Ux500 architecture
955 bool "STMicroelectronics Nomadik"
960 select GENERIC_CLOCKEVENTS
962 select MIGHT_HAVE_CACHE_L2X0
963 select ARCH_REQUIRE_GPIOLIB
965 Support for the Nomadik platform by ST-Ericsson
969 select GENERIC_CLOCKEVENTS
970 select ARCH_REQUIRE_GPIOLIB
974 select GENERIC_ALLOCATOR
975 select GENERIC_IRQ_CHIP
976 select ARCH_HAS_HOLES_MEMORYMODEL
978 Support for TI's DaVinci platform.
984 select ARCH_REQUIRE_GPIOLIB
985 select ARCH_HAS_CPUFREQ
987 select GENERIC_CLOCKEVENTS
988 select ARCH_HAS_HOLES_MEMORYMODEL
990 Support for TI's OMAP platform (OMAP1/2/3/4).
995 select ARCH_REQUIRE_GPIOLIB
999 select GENERIC_CLOCKEVENTS
1002 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1005 bool "VIA/WonderMedia 85xx"
1008 select ARCH_HAS_CPUFREQ
1009 select GENERIC_CLOCKEVENTS
1010 select ARCH_REQUIRE_GPIOLIB
1013 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1016 bool "Xilinx Zynq ARM Cortex A9 Platform"
1018 select GENERIC_CLOCKEVENTS
1019 select CLKDEV_LOOKUP
1023 select MIGHT_HAVE_CACHE_L2X0
1026 Support for Xilinx Zynq ARM Cortex A9 Platform
1030 # This is sorted alphabetically by mach-* pathname. However, plat-*
1031 # Kconfigs may be included either alphabetically (according to the
1032 # plat- suffix) or along side the corresponding mach-* source.
1034 source "arch/arm/mach-mvebu/Kconfig"
1036 source "arch/arm/mach-at91/Kconfig"
1038 source "arch/arm/mach-bcmring/Kconfig"
1040 source "arch/arm/mach-clps711x/Kconfig"
1042 source "arch/arm/mach-cns3xxx/Kconfig"
1044 source "arch/arm/mach-davinci/Kconfig"
1046 source "arch/arm/mach-dove/Kconfig"
1048 source "arch/arm/mach-ep93xx/Kconfig"
1050 source "arch/arm/mach-footbridge/Kconfig"
1052 source "arch/arm/mach-gemini/Kconfig"
1054 source "arch/arm/mach-h720x/Kconfig"
1056 source "arch/arm/mach-integrator/Kconfig"
1058 source "arch/arm/mach-iop32x/Kconfig"
1060 source "arch/arm/mach-iop33x/Kconfig"
1062 source "arch/arm/mach-iop13xx/Kconfig"
1064 source "arch/arm/mach-ixp4xx/Kconfig"
1066 source "arch/arm/mach-kirkwood/Kconfig"
1068 source "arch/arm/mach-ks8695/Kconfig"
1070 source "arch/arm/mach-msm/Kconfig"
1072 source "arch/arm/mach-mv78xx0/Kconfig"
1074 source "arch/arm/plat-mxc/Kconfig"
1076 source "arch/arm/mach-mxs/Kconfig"
1078 source "arch/arm/mach-netx/Kconfig"
1080 source "arch/arm/mach-nomadik/Kconfig"
1081 source "arch/arm/plat-nomadik/Kconfig"
1083 source "arch/arm/plat-omap/Kconfig"
1085 source "arch/arm/mach-omap1/Kconfig"
1087 source "arch/arm/mach-omap2/Kconfig"
1089 source "arch/arm/mach-orion5x/Kconfig"
1091 source "arch/arm/mach-pxa/Kconfig"
1092 source "arch/arm/plat-pxa/Kconfig"
1094 source "arch/arm/mach-mmp/Kconfig"
1096 source "arch/arm/mach-realview/Kconfig"
1098 source "arch/arm/mach-sa1100/Kconfig"
1100 source "arch/arm/plat-samsung/Kconfig"
1101 source "arch/arm/plat-s3c24xx/Kconfig"
1103 source "arch/arm/plat-spear/Kconfig"
1105 source "arch/arm/mach-s3c24xx/Kconfig"
1107 source "arch/arm/mach-s3c2412/Kconfig"
1108 source "arch/arm/mach-s3c2440/Kconfig"
1112 source "arch/arm/mach-s3c64xx/Kconfig"
1115 source "arch/arm/mach-s5p64x0/Kconfig"
1117 source "arch/arm/mach-s5pc100/Kconfig"
1119 source "arch/arm/mach-s5pv210/Kconfig"
1121 source "arch/arm/mach-exynos/Kconfig"
1123 source "arch/arm/mach-shmobile/Kconfig"
1125 source "arch/arm/mach-tegra/Kconfig"
1127 source "arch/arm/mach-u300/Kconfig"
1129 source "arch/arm/mach-ux500/Kconfig"
1131 source "arch/arm/mach-versatile/Kconfig"
1133 source "arch/arm/mach-vexpress/Kconfig"
1134 source "arch/arm/plat-versatile/Kconfig"
1136 source "arch/arm/mach-vt8500/Kconfig"
1138 source "arch/arm/mach-w90x900/Kconfig"
1140 # Definitions to make life easier
1146 select GENERIC_CLOCKEVENTS
1151 select GENERIC_IRQ_CHIP
1157 config PLAT_VERSATILE
1160 config ARM_TIMER_SP804
1163 select HAVE_SCHED_CLOCK
1165 source arch/arm/mm/Kconfig
1169 default 16 if ARCH_EP93XX
1173 bool "Enable iWMMXt support"
1174 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1175 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1177 Enable support for iWMMXt context switching at run time if
1178 running on a CPU that supports it.
1182 depends on CPU_XSCALE
1186 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1187 (!ARCH_OMAP3 || OMAP3_EMU)
1191 config MULTI_IRQ_HANDLER
1194 Allow each machine to specify it's own IRQ handler at run time.
1197 source "arch/arm/Kconfig-nommu"
1200 config ARM_ERRATA_326103
1201 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1204 Executing a SWP instruction to read-only memory does not set bit 11
1205 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1206 treat the access as a read, preventing a COW from occurring and
1207 causing the faulting task to livelock.
1209 config ARM_ERRATA_411920
1210 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1211 depends on CPU_V6 || CPU_V6K
1213 Invalidation of the Instruction Cache operation can
1214 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1215 It does not affect the MPCore. This option enables the ARM Ltd.
1216 recommended workaround.
1218 config ARM_ERRATA_430973
1219 bool "ARM errata: Stale prediction on replaced interworking branch"
1222 This option enables the workaround for the 430973 Cortex-A8
1223 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1224 interworking branch is replaced with another code sequence at the
1225 same virtual address, whether due to self-modifying code or virtual
1226 to physical address re-mapping, Cortex-A8 does not recover from the
1227 stale interworking branch prediction. This results in Cortex-A8
1228 executing the new code sequence in the incorrect ARM or Thumb state.
1229 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1230 and also flushes the branch target cache at every context switch.
1231 Note that setting specific bits in the ACTLR register may not be
1232 available in non-secure mode.
1234 config ARM_ERRATA_458693
1235 bool "ARM errata: Processor deadlock when a false hazard is created"
1238 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1239 erratum. For very specific sequences of memory operations, it is
1240 possible for a hazard condition intended for a cache line to instead
1241 be incorrectly associated with a different cache line. This false
1242 hazard might then cause a processor deadlock. The workaround enables
1243 the L1 caching of the NEON accesses and disables the PLD instruction
1244 in the ACTLR register. Note that setting specific bits in the ACTLR
1245 register may not be available in non-secure mode.
1247 config ARM_ERRATA_460075
1248 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1251 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1252 erratum. Any asynchronous access to the L2 cache may encounter a
1253 situation in which recent store transactions to the L2 cache are lost
1254 and overwritten with stale memory contents from external memory. The
1255 workaround disables the write-allocate mode for the L2 cache via the
1256 ACTLR register. Note that setting specific bits in the ACTLR register
1257 may not be available in non-secure mode.
1259 config ARM_ERRATA_742230
1260 bool "ARM errata: DMB operation may be faulty"
1261 depends on CPU_V7 && SMP
1263 This option enables the workaround for the 742230 Cortex-A9
1264 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1265 between two write operations may not ensure the correct visibility
1266 ordering of the two writes. This workaround sets a specific bit in
1267 the diagnostic register of the Cortex-A9 which causes the DMB
1268 instruction to behave as a DSB, ensuring the correct behaviour of
1271 config ARM_ERRATA_742231
1272 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1273 depends on CPU_V7 && SMP
1275 This option enables the workaround for the 742231 Cortex-A9
1276 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1277 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1278 accessing some data located in the same cache line, may get corrupted
1279 data due to bad handling of the address hazard when the line gets
1280 replaced from one of the CPUs at the same time as another CPU is
1281 accessing it. This workaround sets specific bits in the diagnostic
1282 register of the Cortex-A9 which reduces the linefill issuing
1283 capabilities of the processor.
1285 config PL310_ERRATA_588369
1286 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1287 depends on CACHE_L2X0
1289 The PL310 L2 cache controller implements three types of Clean &
1290 Invalidate maintenance operations: by Physical Address
1291 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1292 They are architecturally defined to behave as the execution of a
1293 clean operation followed immediately by an invalidate operation,
1294 both performing to the same memory location. This functionality
1295 is not correctly implemented in PL310 as clean lines are not
1296 invalidated as a result of these operations.
1298 config ARM_ERRATA_720789
1299 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1302 This option enables the workaround for the 720789 Cortex-A9 (prior to
1303 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1304 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1305 As a consequence of this erratum, some TLB entries which should be
1306 invalidated are not, resulting in an incoherency in the system page
1307 tables. The workaround changes the TLB flushing routines to invalidate
1308 entries regardless of the ASID.
1310 config PL310_ERRATA_727915
1311 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1312 depends on CACHE_L2X0
1314 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1315 operation (offset 0x7FC). This operation runs in background so that
1316 PL310 can handle normal accesses while it is in progress. Under very
1317 rare circumstances, due to this erratum, write data can be lost when
1318 PL310 treats a cacheable write transaction during a Clean &
1319 Invalidate by Way operation.
1321 config ARM_ERRATA_743622
1322 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1325 This option enables the workaround for the 743622 Cortex-A9
1326 (r2p*) erratum. Under very rare conditions, a faulty
1327 optimisation in the Cortex-A9 Store Buffer may lead to data
1328 corruption. This workaround sets a specific bit in the diagnostic
1329 register of the Cortex-A9 which disables the Store Buffer
1330 optimisation, preventing the defect from occurring. This has no
1331 visible impact on the overall performance or power consumption of the
1334 config ARM_ERRATA_751472
1335 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1338 This option enables the workaround for the 751472 Cortex-A9 (prior
1339 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1340 completion of a following broadcasted operation if the second
1341 operation is received by a CPU before the ICIALLUIS has completed,
1342 potentially leading to corrupted entries in the cache or TLB.
1344 config PL310_ERRATA_753970
1345 bool "PL310 errata: cache sync operation may be faulty"
1346 depends on CACHE_PL310
1348 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1350 Under some condition the effect of cache sync operation on
1351 the store buffer still remains when the operation completes.
1352 This means that the store buffer is always asked to drain and
1353 this prevents it from merging any further writes. The workaround
1354 is to replace the normal offset of cache sync operation (0x730)
1355 by another offset targeting an unmapped PL310 register 0x740.
1356 This has the same effect as the cache sync operation: store buffer
1357 drain and waiting for all buffers empty.
1359 config ARM_ERRATA_754322
1360 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1363 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1364 r3p*) erratum. A speculative memory access may cause a page table walk
1365 which starts prior to an ASID switch but completes afterwards. This
1366 can populate the micro-TLB with a stale entry which may be hit with
1367 the new ASID. This workaround places two dsb instructions in the mm
1368 switching code so that no page table walks can cross the ASID switch.
1370 config ARM_ERRATA_754327
1371 bool "ARM errata: no automatic Store Buffer drain"
1372 depends on CPU_V7 && SMP
1374 This option enables the workaround for the 754327 Cortex-A9 (prior to
1375 r2p0) erratum. The Store Buffer does not have any automatic draining
1376 mechanism and therefore a livelock may occur if an external agent
1377 continuously polls a memory location waiting to observe an update.
1378 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1379 written polling loops from denying visibility of updates to memory.
1381 config ARM_ERRATA_364296
1382 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1383 depends on CPU_V6 && !SMP
1385 This options enables the workaround for the 364296 ARM1136
1386 r0p2 erratum (possible cache data corruption with
1387 hit-under-miss enabled). It sets the undocumented bit 31 in
1388 the auxiliary control register and the FI bit in the control
1389 register, thus disabling hit-under-miss without putting the
1390 processor into full low interrupt latency mode. ARM11MPCore
1393 config ARM_ERRATA_764369
1394 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1395 depends on CPU_V7 && SMP
1397 This option enables the workaround for erratum 764369
1398 affecting Cortex-A9 MPCore with two or more processors (all
1399 current revisions). Under certain timing circumstances, a data
1400 cache line maintenance operation by MVA targeting an Inner
1401 Shareable memory region may fail to proceed up to either the
1402 Point of Coherency or to the Point of Unification of the
1403 system. This workaround adds a DSB instruction before the
1404 relevant cache maintenance functions and sets a specific bit
1405 in the diagnostic control register of the SCU.
1407 config PL310_ERRATA_769419
1408 bool "PL310 errata: no automatic Store Buffer drain"
1409 depends on CACHE_L2X0
1411 On revisions of the PL310 prior to r3p2, the Store Buffer does
1412 not automatically drain. This can cause normal, non-cacheable
1413 writes to be retained when the memory system is idle, leading
1414 to suboptimal I/O performance for drivers using coherent DMA.
1415 This option adds a write barrier to the cpu_idle loop so that,
1416 on systems with an outer cache, the store buffer is drained
1421 source "arch/arm/common/Kconfig"
1431 Find out whether you have ISA slots on your motherboard. ISA is the
1432 name of a bus system, i.e. the way the CPU talks to the other stuff
1433 inside your box. Other bus systems are PCI, EISA, MicroChannel
1434 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1435 newer boards don't support it. If you have ISA, say Y, otherwise N.
1437 # Select ISA DMA controller support
1442 # Select ISA DMA interface
1447 bool "PCI support" if MIGHT_HAVE_PCI
1449 Find out whether you have a PCI motherboard. PCI is the name of a
1450 bus system, i.e. the way the CPU talks to the other stuff inside
1451 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1452 VESA. If you have PCI, say Y, otherwise N.
1458 config PCI_NANOENGINE
1459 bool "BSE nanoEngine PCI support"
1460 depends on SA1100_NANOENGINE
1462 Enable PCI on the BSE nanoEngine board.
1467 # Select the host bridge type
1468 config PCI_HOST_VIA82C505
1470 depends on PCI && ARCH_SHARK
1473 config PCI_HOST_ITE8152
1475 depends on PCI && MACH_ARMCORE
1479 source "drivers/pci/Kconfig"
1481 source "drivers/pcmcia/Kconfig"
1485 menu "Kernel Features"
1490 This option should be selected by machines which have an SMP-
1493 The only effect of this option is to make the SMP-related
1494 options available to the user for configuration.
1497 bool "Symmetric Multi-Processing"
1498 depends on CPU_V6K || CPU_V7
1499 depends on GENERIC_CLOCKEVENTS
1502 select USE_GENERIC_SMP_HELPERS
1503 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1505 This enables support for systems with more than one CPU. If you have
1506 a system with only one CPU, like most personal computers, say N. If
1507 you have a system with more than one CPU, say Y.
1509 If you say N here, the kernel will run on single and multiprocessor
1510 machines, but will use only one CPU of a multiprocessor machine. If
1511 you say Y here, the kernel will run on many, but not all, single
1512 processor machines. On a single processor machine, the kernel will
1513 run faster if you say N here.
1515 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1516 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1517 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1519 If you don't know what to do here, say N.
1522 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1523 depends on EXPERIMENTAL
1524 depends on SMP && !XIP_KERNEL
1527 SMP kernels contain instructions which fail on non-SMP processors.
1528 Enabling this option allows the kernel to modify itself to make
1529 these instructions safe. Disabling it allows about 1K of space
1532 If you don't know what to do here, say Y.
1534 config ARM_CPU_TOPOLOGY
1535 bool "Support cpu topology definition"
1536 depends on SMP && CPU_V7
1539 Support ARM cpu topology definition. The MPIDR register defines
1540 affinity between processors which is then used to describe the cpu
1541 topology of an ARM System.
1544 bool "Multi-core scheduler support"
1545 depends on ARM_CPU_TOPOLOGY
1547 Multi-core scheduler support improves the CPU scheduler's decision
1548 making when dealing with multi-core CPU chips at a cost of slightly
1549 increased overhead in some places. If unsure say N here.
1552 bool "SMT scheduler support"
1553 depends on ARM_CPU_TOPOLOGY
1555 Improves the CPU scheduler's decision making when dealing with
1556 MultiThreading at a cost of slightly increased overhead in some
1557 places. If unsure say N here.
1562 This option enables support for the ARM system coherency unit
1564 config ARM_ARCH_TIMER
1565 bool "Architected timer support"
1568 This option enables support for the ARM architected timer
1574 This options enables support for the ARM timer and watchdog unit
1577 prompt "Memory split"
1580 Select the desired split between kernel and user memory.
1582 If you are not absolutely sure what you are doing, leave this
1586 bool "3G/1G user/kernel split"
1588 bool "2G/2G user/kernel split"
1590 bool "1G/3G user/kernel split"
1595 default 0x40000000 if VMSPLIT_1G
1596 default 0x80000000 if VMSPLIT_2G
1600 int "Maximum number of CPUs (2-32)"
1606 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1607 depends on SMP && HOTPLUG && EXPERIMENTAL
1609 Say Y here to experiment with turning CPUs off and on. CPUs
1610 can be controlled through /sys/devices/system/cpu.
1613 bool "Use local timer interrupts"
1616 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1618 Enable support for local timers on SMP platforms, rather then the
1619 legacy IPI broadcast method. Local timers allows the system
1620 accounting to be spread across the timer interval, preventing a
1621 "thundering herd" at every timer tick.
1625 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1626 default 355 if ARCH_U8500
1627 default 264 if MACH_H4700
1628 default 512 if SOC_OMAP5
1631 Maximum number of GPIOs in the system.
1633 If unsure, leave the default value.
1635 source kernel/Kconfig.preempt
1639 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1640 ARCH_S5PV210 || ARCH_EXYNOS4
1641 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1642 default AT91_TIMER_HZ if ARCH_AT91
1643 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1646 config THUMB2_KERNEL
1647 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1648 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1650 select ARM_ASM_UNIFIED
1653 By enabling this option, the kernel will be compiled in
1654 Thumb-2 mode. A compiler/assembler that understand the unified
1655 ARM-Thumb syntax is needed.
1659 config THUMB2_AVOID_R_ARM_THM_JUMP11
1660 bool "Work around buggy Thumb-2 short branch relocations in gas"
1661 depends on THUMB2_KERNEL && MODULES
1664 Various binutils versions can resolve Thumb-2 branches to
1665 locally-defined, preemptible global symbols as short-range "b.n"
1666 branch instructions.
1668 This is a problem, because there's no guarantee the final
1669 destination of the symbol, or any candidate locations for a
1670 trampoline, are within range of the branch. For this reason, the
1671 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1672 relocation in modules at all, and it makes little sense to add
1675 The symptom is that the kernel fails with an "unsupported
1676 relocation" error when loading some modules.
1678 Until fixed tools are available, passing
1679 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1680 code which hits this problem, at the cost of a bit of extra runtime
1681 stack usage in some cases.
1683 The problem is described in more detail at:
1684 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1686 Only Thumb-2 kernels are affected.
1688 Unless you are sure your tools don't have this problem, say Y.
1690 config ARM_ASM_UNIFIED
1694 bool "Use the ARM EABI to compile the kernel"
1696 This option allows for the kernel to be compiled using the latest
1697 ARM ABI (aka EABI). This is only useful if you are using a user
1698 space environment that is also compiled with EABI.
1700 Since there are major incompatibilities between the legacy ABI and
1701 EABI, especially with regard to structure member alignment, this
1702 option also changes the kernel syscall calling convention to
1703 disambiguate both ABIs and allow for backward compatibility support
1704 (selected with CONFIG_OABI_COMPAT).
1706 To use this you need GCC version 4.0.0 or later.
1709 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1710 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1713 This option preserves the old syscall interface along with the
1714 new (ARM EABI) one. It also provides a compatibility layer to
1715 intercept syscalls that have structure arguments which layout
1716 in memory differs between the legacy ABI and the new ARM EABI
1717 (only for non "thumb" binaries). This option adds a tiny
1718 overhead to all syscalls and produces a slightly larger kernel.
1719 If you know you'll be using only pure EABI user space then you
1720 can say N here. If this option is not selected and you attempt
1721 to execute a legacy ABI binary then the result will be
1722 UNPREDICTABLE (in fact it can be predicted that it won't work
1723 at all). If in doubt say Y.
1725 config ARCH_HAS_HOLES_MEMORYMODEL
1728 config ARCH_SPARSEMEM_ENABLE
1731 config ARCH_SPARSEMEM_DEFAULT
1732 def_bool ARCH_SPARSEMEM_ENABLE
1734 config ARCH_SELECT_MEMORY_MODEL
1735 def_bool ARCH_SPARSEMEM_ENABLE
1737 config HAVE_ARCH_PFN_VALID
1738 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1741 bool "High Memory Support"
1744 The address space of ARM processors is only 4 Gigabytes large
1745 and it has to accommodate user address space, kernel address
1746 space as well as some memory mapped IO. That means that, if you
1747 have a large amount of physical memory and/or IO, not all of the
1748 memory can be "permanently mapped" by the kernel. The physical
1749 memory that is not permanently mapped is called "high memory".
1751 Depending on the selected kernel/user memory split, minimum
1752 vmalloc space and actual amount of RAM, you may not need this
1753 option which should result in a slightly faster kernel.
1758 bool "Allocate 2nd-level pagetables from highmem"
1761 config HW_PERF_EVENTS
1762 bool "Enable hardware performance counter support for perf events"
1763 depends on PERF_EVENTS && CPU_HAS_PMU
1766 Enable hardware performance counter support for perf events. If
1767 disabled, perf events will use software events only.
1771 config FORCE_MAX_ZONEORDER
1772 int "Maximum zone order" if ARCH_SHMOBILE
1773 range 11 64 if ARCH_SHMOBILE
1774 default "9" if SA1111
1777 The kernel memory allocator divides physically contiguous memory
1778 blocks into "zones", where each zone is a power of two number of
1779 pages. This option selects the largest power of two that the kernel
1780 keeps in the memory allocator. If you need to allocate very large
1781 blocks of physically contiguous memory, then you may need to
1782 increase this value.
1784 This config option is actually maximum order plus one. For example,
1785 a value of 11 means that the largest free memory block is 2^10 pages.
1788 bool "Timer and CPU usage LEDs"
1789 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1790 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1791 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1792 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1793 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1794 ARCH_AT91 || ARCH_DAVINCI || \
1795 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1797 If you say Y here, the LEDs on your machine will be used
1798 to provide useful information about your current system status.
1800 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1801 be able to select which LEDs are active using the options below. If
1802 you are compiling a kernel for the EBSA-110 or the LART however, the
1803 red LED will simply flash regularly to indicate that the system is
1804 still functional. It is safe to say Y here if you have a CATS
1805 system, but the driver will do nothing.
1808 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1809 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1810 || MACH_OMAP_PERSEUS2
1812 depends on !GENERIC_CLOCKEVENTS
1813 default y if ARCH_EBSA110
1815 If you say Y here, one of the system LEDs (the green one on the
1816 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1817 will flash regularly to indicate that the system is still
1818 operational. This is mainly useful to kernel hackers who are
1819 debugging unstable kernels.
1821 The LART uses the same LED for both Timer LED and CPU usage LED
1822 functions. You may choose to use both, but the Timer LED function
1823 will overrule the CPU usage LED.
1826 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1828 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1829 || MACH_OMAP_PERSEUS2
1832 If you say Y here, the red LED will be used to give a good real
1833 time indication of CPU usage, by lighting whenever the idle task
1834 is not currently executing.
1836 The LART uses the same LED for both Timer LED and CPU usage LED
1837 functions. You may choose to use both, but the Timer LED function
1838 will overrule the CPU usage LED.
1840 config ALIGNMENT_TRAP
1842 depends on CPU_CP15_MMU
1843 default y if !ARCH_EBSA110
1844 select HAVE_PROC_CPU if PROC_FS
1846 ARM processors cannot fetch/store information which is not
1847 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1848 address divisible by 4. On 32-bit ARM processors, these non-aligned
1849 fetch/store instructions will be emulated in software if you say
1850 here, which has a severe performance impact. This is necessary for
1851 correct operation of some network protocols. With an IP-only
1852 configuration it is safe to say N, otherwise say Y.
1854 config UACCESS_WITH_MEMCPY
1855 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1856 depends on MMU && EXPERIMENTAL
1857 default y if CPU_FEROCEON
1859 Implement faster copy_to_user and clear_user methods for CPU
1860 cores where a 8-word STM instruction give significantly higher
1861 memory write throughput than a sequence of individual 32bit stores.
1863 A possible side effect is a slight increase in scheduling latency
1864 between threads sharing the same address space if they invoke
1865 such copy operations with large buffers.
1867 However, if the CPU data cache is using a write-allocate mode,
1868 this option is unlikely to provide any performance gain.
1872 prompt "Enable seccomp to safely compute untrusted bytecode"
1874 This kernel feature is useful for number crunching applications
1875 that may need to compute untrusted bytecode during their
1876 execution. By using pipes or other transports made available to
1877 the process as file descriptors supporting the read/write
1878 syscalls, it's possible to isolate those applications in
1879 their own address space using seccomp. Once seccomp is
1880 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1881 and the task is only allowed to execute a few safe syscalls
1882 defined by each seccomp mode.
1884 config CC_STACKPROTECTOR
1885 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1886 depends on EXPERIMENTAL
1888 This option turns on the -fstack-protector GCC feature. This
1889 feature puts, at the beginning of functions, a canary value on
1890 the stack just before the return address, and validates
1891 the value just before actually returning. Stack based buffer
1892 overflows (that need to overwrite this return address) now also
1893 overwrite the canary, which gets detected and the attack is then
1894 neutralized via a kernel panic.
1895 This feature requires gcc version 4.2 or above.
1897 config DEPRECATED_PARAM_STRUCT
1898 bool "Provide old way to pass kernel parameters"
1900 This was deprecated in 2001 and announced to live on for 5 years.
1901 Some old boot loaders still use this way.
1908 bool "Flattened Device Tree support"
1910 select OF_EARLY_FLATTREE
1913 Include support for flattened device tree machine descriptions.
1915 # Compressed boot loader in ROM. Yes, we really want to ask about
1916 # TEXT and BSS so we preserve their values in the config files.
1917 config ZBOOT_ROM_TEXT
1918 hex "Compressed ROM boot loader base address"
1921 The physical address at which the ROM-able zImage is to be
1922 placed in the target. Platforms which normally make use of
1923 ROM-able zImage formats normally set this to a suitable
1924 value in their defconfig file.
1926 If ZBOOT_ROM is not enabled, this has no effect.
1928 config ZBOOT_ROM_BSS
1929 hex "Compressed ROM boot loader BSS address"
1932 The base address of an area of read/write memory in the target
1933 for the ROM-able zImage which must be available while the
1934 decompressor is running. It must be large enough to hold the
1935 entire decompressed kernel plus an additional 128 KiB.
1936 Platforms which normally make use of ROM-able zImage formats
1937 normally set this to a suitable value in their defconfig file.
1939 If ZBOOT_ROM is not enabled, this has no effect.
1942 bool "Compressed boot loader in ROM/flash"
1943 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1945 Say Y here if you intend to execute your compressed kernel image
1946 (zImage) directly from ROM or flash. If unsure, say N.
1949 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1950 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1951 default ZBOOT_ROM_NONE
1953 Include experimental SD/MMC loading code in the ROM-able zImage.
1954 With this enabled it is possible to write the ROM-able zImage
1955 kernel image to an MMC or SD card and boot the kernel straight
1956 from the reset vector. At reset the processor Mask ROM will load
1957 the first part of the ROM-able zImage which in turn loads the
1958 rest the kernel image to RAM.
1960 config ZBOOT_ROM_NONE
1961 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1963 Do not load image from SD or MMC
1965 config ZBOOT_ROM_MMCIF
1966 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1968 Load image from MMCIF hardware block.
1970 config ZBOOT_ROM_SH_MOBILE_SDHI
1971 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1973 Load image from SDHI hardware block
1977 config ARM_APPENDED_DTB
1978 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1979 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1981 With this option, the boot code will look for a device tree binary
1982 (DTB) appended to zImage
1983 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1985 This is meant as a backward compatibility convenience for those
1986 systems with a bootloader that can't be upgraded to accommodate
1987 the documented boot protocol using a device tree.
1989 Beware that there is very little in terms of protection against
1990 this option being confused by leftover garbage in memory that might
1991 look like a DTB header after a reboot if no actual DTB is appended
1992 to zImage. Do not leave this option active in a production kernel
1993 if you don't intend to always append a DTB. Proper passing of the
1994 location into r2 of a bootloader provided DTB is always preferable
1997 config ARM_ATAG_DTB_COMPAT
1998 bool "Supplement the appended DTB with traditional ATAG information"
1999 depends on ARM_APPENDED_DTB
2001 Some old bootloaders can't be updated to a DTB capable one, yet
2002 they provide ATAGs with memory configuration, the ramdisk address,
2003 the kernel cmdline string, etc. Such information is dynamically
2004 provided by the bootloader and can't always be stored in a static
2005 DTB. To allow a device tree enabled kernel to be used with such
2006 bootloaders, this option allows zImage to extract the information
2007 from the ATAG list and store it at run time into the appended DTB.
2010 string "Default kernel command string"
2013 On some architectures (EBSA110 and CATS), there is currently no way
2014 for the boot loader to pass arguments to the kernel. For these
2015 architectures, you should supply some command-line options at build
2016 time by entering them here. As a minimum, you should specify the
2017 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2020 prompt "Kernel command line type" if CMDLINE != ""
2021 default CMDLINE_FROM_BOOTLOADER
2023 config CMDLINE_FROM_BOOTLOADER
2024 bool "Use bootloader kernel arguments if available"
2026 Uses the command-line options passed by the boot loader. If
2027 the boot loader doesn't provide any, the default kernel command
2028 string provided in CMDLINE will be used.
2030 config CMDLINE_EXTEND
2031 bool "Extend bootloader kernel arguments"
2033 The command-line arguments provided by the boot loader will be
2034 appended to the default kernel command string.
2036 config CMDLINE_FORCE
2037 bool "Always use the default kernel command string"
2039 Always use the default kernel command string, even if the boot
2040 loader passes other arguments to the kernel.
2041 This is useful if you cannot or don't want to change the
2042 command-line options your boot loader passes to the kernel.
2046 bool "Kernel Execute-In-Place from ROM"
2047 depends on !ZBOOT_ROM && !ARM_LPAE
2049 Execute-In-Place allows the kernel to run from non-volatile storage
2050 directly addressable by the CPU, such as NOR flash. This saves RAM
2051 space since the text section of the kernel is not loaded from flash
2052 to RAM. Read-write sections, such as the data section and stack,
2053 are still copied to RAM. The XIP kernel is not compressed since
2054 it has to run directly from flash, so it will take more space to
2055 store it. The flash address used to link the kernel object files,
2056 and for storing it, is configuration dependent. Therefore, if you
2057 say Y here, you must know the proper physical address where to
2058 store the kernel image depending on your own flash memory usage.
2060 Also note that the make target becomes "make xipImage" rather than
2061 "make zImage" or "make Image". The final kernel binary to put in
2062 ROM memory will be arch/arm/boot/xipImage.
2066 config XIP_PHYS_ADDR
2067 hex "XIP Kernel Physical Location"
2068 depends on XIP_KERNEL
2069 default "0x00080000"
2071 This is the physical address in your flash memory the kernel will
2072 be linked for and stored to. This address is dependent on your
2076 bool "Kexec system call (EXPERIMENTAL)"
2077 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2079 kexec is a system call that implements the ability to shutdown your
2080 current kernel, and to start another kernel. It is like a reboot
2081 but it is independent of the system firmware. And like a reboot
2082 you can start any kernel with it, not just Linux.
2084 It is an ongoing process to be certain the hardware in a machine
2085 is properly shutdown, so do not be surprised if this code does not
2086 initially work for you. It may help to enable device hotplugging
2090 bool "Export atags in procfs"
2094 Should the atags used to boot the kernel be exported in an "atags"
2095 file in procfs. Useful with kexec.
2098 bool "Build kdump crash kernel (EXPERIMENTAL)"
2099 depends on EXPERIMENTAL
2101 Generate crash dump after being started by kexec. This should
2102 be normally only set in special crash dump kernels which are
2103 loaded in the main kernel with kexec-tools into a specially
2104 reserved region and then later executed after a crash by
2105 kdump/kexec. The crash dump kernel must be compiled to a
2106 memory address not used by the main kernel
2108 For more details see Documentation/kdump/kdump.txt
2110 config AUTO_ZRELADDR
2111 bool "Auto calculation of the decompressed kernel image address"
2112 depends on !ZBOOT_ROM && !ARCH_U300
2114 ZRELADDR is the physical address where the decompressed kernel
2115 image will be placed. If AUTO_ZRELADDR is selected, the address
2116 will be determined at run-time by masking the current IP with
2117 0xf8000000. This assumes the zImage being placed in the first 128MB
2118 from start of memory.
2122 menu "CPU Power Management"
2126 source "drivers/cpufreq/Kconfig"
2129 tristate "CPUfreq driver for i.MX CPUs"
2130 depends on ARCH_MXC && CPU_FREQ
2132 This enables the CPUfreq driver for i.MX CPUs.
2134 config CPU_FREQ_SA1100
2137 config CPU_FREQ_SA1110
2140 config CPU_FREQ_INTEGRATOR
2141 tristate "CPUfreq driver for ARM Integrator CPUs"
2142 depends on ARCH_INTEGRATOR && CPU_FREQ
2145 This enables the CPUfreq driver for ARM Integrator CPUs.
2147 For details, take a look at <file:Documentation/cpu-freq>.
2153 depends on CPU_FREQ && ARCH_PXA && PXA25x
2155 select CPU_FREQ_TABLE
2156 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2161 Internal configuration node for common cpufreq on Samsung SoC
2163 config CPU_FREQ_S3C24XX
2164 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2165 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2168 This enables the CPUfreq driver for the Samsung S3C24XX family
2171 For details, take a look at <file:Documentation/cpu-freq>.
2175 config CPU_FREQ_S3C24XX_PLL
2176 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2177 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2179 Compile in support for changing the PLL frequency from the
2180 S3C24XX series CPUfreq driver. The PLL takes time to settle
2181 after a frequency change, so by default it is not enabled.
2183 This also means that the PLL tables for the selected CPU(s) will
2184 be built which may increase the size of the kernel image.
2186 config CPU_FREQ_S3C24XX_DEBUG
2187 bool "Debug CPUfreq Samsung driver core"
2188 depends on CPU_FREQ_S3C24XX
2190 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2192 config CPU_FREQ_S3C24XX_IODEBUG
2193 bool "Debug CPUfreq Samsung driver IO timing"
2194 depends on CPU_FREQ_S3C24XX
2196 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2198 config CPU_FREQ_S3C24XX_DEBUGFS
2199 bool "Export debugfs for CPUFreq"
2200 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2202 Export status information via debugfs.
2206 source "drivers/cpuidle/Kconfig"
2210 menu "Floating point emulation"
2212 comment "At least one emulation must be selected"
2215 bool "NWFPE math emulation"
2216 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2218 Say Y to include the NWFPE floating point emulator in the kernel.
2219 This is necessary to run most binaries. Linux does not currently
2220 support floating point hardware so you need to say Y here even if
2221 your machine has an FPA or floating point co-processor podule.
2223 You may say N here if you are going to load the Acorn FPEmulator
2224 early in the bootup.
2227 bool "Support extended precision"
2228 depends on FPE_NWFPE
2230 Say Y to include 80-bit support in the kernel floating-point
2231 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2232 Note that gcc does not generate 80-bit operations by default,
2233 so in most cases this option only enlarges the size of the
2234 floating point emulator without any good reason.
2236 You almost surely want to say N here.
2239 bool "FastFPE math emulation (EXPERIMENTAL)"
2240 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2242 Say Y here to include the FAST floating point emulator in the kernel.
2243 This is an experimental much faster emulator which now also has full
2244 precision for the mantissa. It does not support any exceptions.
2245 It is very simple, and approximately 3-6 times faster than NWFPE.
2247 It should be sufficient for most programs. It may be not suitable
2248 for scientific calculations, but you have to check this for yourself.
2249 If you do not feel you need a faster FP emulation you should better
2253 bool "VFP-format floating point maths"
2254 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2256 Say Y to include VFP support code in the kernel. This is needed
2257 if your hardware includes a VFP unit.
2259 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2260 release notes and additional status information.
2262 Say N if your target does not have VFP hardware.
2270 bool "Advanced SIMD (NEON) Extension support"
2271 depends on VFPv3 && CPU_V7
2273 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2278 menu "Userspace binary formats"
2280 source "fs/Kconfig.binfmt"
2283 tristate "RISC OS personality"
2286 Say Y here to include the kernel code necessary if you want to run
2287 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2288 experimental; if this sounds frightening, say N and sleep in peace.
2289 You can also say M here to compile this support as a module (which
2290 will be called arthur).
2294 menu "Power management options"
2296 source "kernel/power/Kconfig"
2298 config ARCH_SUSPEND_POSSIBLE
2299 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2300 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2301 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2304 config ARM_CPU_SUSPEND
2309 source "net/Kconfig"
2311 source "drivers/Kconfig"
2315 source "arch/arm/Kconfig.debug"
2317 source "security/Kconfig"
2319 source "crypto/Kconfig"
2321 source "lib/Kconfig"