5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
14 select HAVE_KPROBES if !XIP_KERNEL
15 select HAVE_KRETPROBES if (HAVE_KPROBES)
16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
21 select HAVE_GENERIC_DMA_COHERENT
22 select HAVE_KERNEL_GZIP
23 select HAVE_KERNEL_LZO
24 select HAVE_KERNEL_LZMA
27 select HAVE_PERF_EVENTS
28 select PERF_USE_VMALLOC
29 select HAVE_REGS_AND_STACK_ACCESS_API
30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_GENERIC_HARDIRQS
33 select GENERIC_IRQ_SHOW
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select GENERIC_PCI_IOMAP
36 select HAVE_BPF_JIT if NET
38 The ARM series is a line of low-power-consumption RISC chip designs
39 licensed by ARM Ltd and targeted at embedded applications and
40 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
41 manufactured, but legacy ARM-based PC hardware remains popular in
42 Europe. There is an ARM Linux project with a web page at
43 <http://www.arm.linux.org.uk/>.
45 config ARM_HAS_SG_CHAIN
54 config SYS_SUPPORTS_APM_EMULATION
60 config ARCH_USES_GETTIMEOFFSET
64 config GENERIC_CLOCKEVENTS
67 config GENERIC_CLOCKEVENTS_BROADCAST
69 depends on GENERIC_CLOCKEVENTS
78 select GENERIC_ALLOCATOR
89 The Extended Industry Standard Architecture (EISA) bus was
90 developed as an open alternative to the IBM MicroChannel bus.
92 The EISA bus provided some of the features of the IBM MicroChannel
93 bus while maintaining backward compatibility with cards made for
94 the older ISA bus. The EISA bus saw limited use between 1988 and
95 1995 when it was made obsolete by the PCI bus.
97 Say Y here if you are building a kernel for an EISA-based machine.
107 MicroChannel Architecture is found in some IBM PS/2 machines and
108 laptops. It is a bus system similar to PCI or ISA. See
109 <file:Documentation/mca.txt> (and especially the web page given
110 there) before attempting to build an MCA bus kernel.
112 config STACKTRACE_SUPPORT
116 config HAVE_LATENCYTOP_SUPPORT
121 config LOCKDEP_SUPPORT
125 config TRACE_IRQFLAGS_SUPPORT
129 config HARDIRQS_SW_RESEND
133 config GENERIC_IRQ_PROBE
137 config GENERIC_LOCKBREAK
140 depends on SMP && PREEMPT
142 config RWSEM_GENERIC_SPINLOCK
146 config RWSEM_XCHGADD_ALGORITHM
149 config ARCH_HAS_ILOG2_U32
152 config ARCH_HAS_ILOG2_U64
155 config ARCH_HAS_CPUFREQ
158 Internal node to signify that the ARCH has CPUFREQ support
159 and that the relevant menu configurations are displayed for
162 config ARCH_HAS_CPU_IDLE_WAIT
165 config GENERIC_HWEIGHT
169 config GENERIC_CALIBRATE_DELAY
173 config ARCH_MAY_HAVE_PC_FDC
179 config NEED_DMA_MAP_STATE
182 config ARCH_HAS_DMA_SET_COHERENT_MASK
185 config GENERIC_ISA_DMA
191 config NEED_RET_TO_USER
199 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
200 default DRAM_BASE if REMAP_VECTORS_TO_RAM
203 The base address of exception vectors.
205 config ARM_PATCH_PHYS_VIRT
206 bool "Patch physical to virtual translations at runtime" if EMBEDDED
208 depends on !XIP_KERNEL && MMU
209 depends on !ARCH_REALVIEW || !SPARSEMEM
211 Patch phys-to-virt and virt-to-phys translation functions at
212 boot and module load time according to the position of the
213 kernel in system memory.
215 This can only be used with non-XIP MMU kernels where the base
216 of physical memory is at a 16MB boundary.
218 Only disable this option if you know that you do not require
219 this feature (eg, building a kernel for a single machine) and
220 you need to shrink the kernel to the minimal size.
222 config NEED_MACH_IO_H
225 Select this when mach/io.h is required to provide special
226 definitions for this platform. The need for mach/io.h should
227 be avoided when possible.
229 config NEED_MACH_MEMORY_H
232 Select this when mach/memory.h is required to provide special
233 definitions for this platform. The need for mach/memory.h should
234 be avoided when possible.
237 hex "Physical address of main memory" if MMU
238 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
239 default DRAM_BASE if !MMU
241 Please provide the physical address corresponding to the
242 location of main memory in your system.
248 source "init/Kconfig"
250 source "kernel/Kconfig.freezer"
255 bool "MMU-based Paged Memory Management Support"
258 Select if you want MMU-based virtualised addressing space
259 support by paged memory management. If unsure, say 'Y'.
262 # The "ARM system type" choice list is ordered alphabetically by option
263 # text. Please add new entries in the option alphabetic order.
266 prompt "ARM system type"
267 default ARCH_VERSATILE
269 config ARCH_INTEGRATOR
270 bool "ARM Ltd. Integrator family"
272 select ARCH_HAS_CPUFREQ
274 select HAVE_MACH_CLKDEV
277 select GENERIC_CLOCKEVENTS
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_FPGA_IRQ
280 select NEED_MACH_IO_H
281 select NEED_MACH_MEMORY_H
284 Support for ARM's Integrator platform.
287 bool "ARM Ltd. RealView family"
290 select HAVE_MACH_CLKDEV
292 select GENERIC_CLOCKEVENTS
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 select ARM_TIMER_SP804
297 select GPIO_PL061 if GPIOLIB
298 select NEED_MACH_MEMORY_H
300 This enables support for ARM Ltd RealView boards.
302 config ARCH_VERSATILE
303 bool "ARM Ltd. Versatile family"
307 select HAVE_MACH_CLKDEV
309 select GENERIC_CLOCKEVENTS
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLCD
313 select PLAT_VERSATILE_FPGA_IRQ
314 select ARM_TIMER_SP804
316 This enables support for ARM Ltd Versatile board.
319 bool "ARM Ltd. Versatile Express family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select HAVE_MACH_CLKDEV
325 select GENERIC_CLOCKEVENTS
327 select HAVE_PATA_PLATFORM
330 select PLAT_VERSATILE
331 select PLAT_VERSATILE_CLCD
333 This enables support for the ARM Ltd Versatile Express boards.
337 select ARCH_REQUIRE_GPIOLIB
341 select NEED_MACH_IO_H if PCCARD
343 This enables support for systems based on the Atmel AT91RM9200,
347 bool "Broadcom BCMRING"
351 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
354 select ARCH_WANT_OPTIONAL_GPIOLIB
356 Support for Broadcom's BCMRing platform.
359 bool "Calxeda Highbank-based"
360 select ARCH_WANT_OPTIONAL_GPIOLIB
363 select ARM_TIMER_SP804
367 select GENERIC_CLOCKEVENTS
373 Support for the Calxeda Highbank SoC based boards.
376 bool "Cirrus Logic CLPS711x/EP721x-based"
378 select ARCH_USES_GETTIMEOFFSET
379 select NEED_MACH_MEMORY_H
381 Support for Cirrus Logic 711x/721x based boards.
384 bool "Cavium Networks CNS3XXX family"
386 select GENERIC_CLOCKEVENTS
388 select MIGHT_HAVE_CACHE_L2X0
389 select MIGHT_HAVE_PCI
390 select PCI_DOMAINS if PCI
392 Support for Cavium Networks CNS3XXX platform.
395 bool "Cortina Systems Gemini"
397 select ARCH_REQUIRE_GPIOLIB
398 select ARCH_USES_GETTIMEOFFSET
400 Support for the Cortina Systems Gemini family SoCs
403 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
406 select GENERIC_CLOCKEVENTS
408 select GENERIC_IRQ_CHIP
409 select MIGHT_HAVE_CACHE_L2X0
413 Support for CSR SiRFSoC ARM Cortex A9 Platform
420 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_IO_H
422 select NEED_MACH_MEMORY_H
424 This is an evaluation board for the StrongARM processor available
425 from Digital. It has limited hardware on-board, including an
426 Ethernet interface, two PCMCIA sockets, two serial ports and a
435 select ARCH_REQUIRE_GPIOLIB
436 select ARCH_HAS_HOLES_MEMORYMODEL
437 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_MEMORY_H
440 This enables support for the Cirrus EP93xx series of CPUs.
442 config ARCH_FOOTBRIDGE
446 select GENERIC_CLOCKEVENTS
448 select NEED_MACH_IO_H
449 select NEED_MACH_MEMORY_H
451 Support for systems based on the DC21285 companion chip
452 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
455 bool "Freescale MXC/iMX-based"
456 select GENERIC_CLOCKEVENTS
457 select ARCH_REQUIRE_GPIOLIB
460 select GENERIC_IRQ_CHIP
461 select MULTI_IRQ_HANDLER
463 Support for Freescale MXC/iMX-based family of processors
466 bool "Freescale MXS-based"
467 select GENERIC_CLOCKEVENTS
468 select ARCH_REQUIRE_GPIOLIB
471 select HAVE_CLK_PREPARE
473 Support for Freescale MXS-based family of processors
476 bool "Hilscher NetX based"
480 select GENERIC_CLOCKEVENTS
482 This enables support for systems based on the Hilscher NetX Soc
485 bool "Hynix HMS720x-based"
488 select ARCH_USES_GETTIMEOFFSET
490 This enables support for systems based on the Hynix HMS720x
498 select ARCH_SUPPORTS_MSI
500 select NEED_MACH_IO_H
501 select NEED_MACH_MEMORY_H
502 select NEED_RET_TO_USER
504 Support for Intel's IOP13XX (XScale) family of processors.
510 select NEED_MACH_IO_H
511 select NEED_RET_TO_USER
514 select ARCH_REQUIRE_GPIOLIB
516 Support for Intel's 80219 and IOP32X (XScale) family of
523 select NEED_MACH_IO_H
524 select NEED_RET_TO_USER
527 select ARCH_REQUIRE_GPIOLIB
529 Support for Intel's IOP33X (XScale) family of processors.
536 select ARCH_USES_GETTIMEOFFSET
537 select NEED_MACH_IO_H
538 select NEED_MACH_MEMORY_H
540 Support for Intel's IXP23xx (XScale) family of processors.
543 bool "IXP2400/2800-based"
547 select ARCH_USES_GETTIMEOFFSET
548 select NEED_MACH_IO_H
549 select NEED_MACH_MEMORY_H
551 Support for Intel's IXP2400/2800 (XScale) family of processors.
556 select ARCH_HAS_DMA_SET_COHERENT_MASK
560 select GENERIC_CLOCKEVENTS
561 select MIGHT_HAVE_PCI
562 select NEED_MACH_IO_H
563 select DMABOUNCE if PCI
565 Support for Intel's IXP4XX (XScale) family of processors.
571 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
573 select NEED_MACH_IO_H
576 Support for the Marvell Dove SoC 88AP510
579 bool "Marvell Kirkwood"
582 select ARCH_REQUIRE_GPIOLIB
583 select GENERIC_CLOCKEVENTS
584 select NEED_MACH_IO_H
587 Support for the following Marvell Kirkwood series SoCs:
588 88F6180, 88F6192 and 88F6281.
594 select ARCH_REQUIRE_GPIOLIB
597 select USB_ARCH_HAS_OHCI
599 select GENERIC_CLOCKEVENTS
601 Support for the NXP LPC32XX family of processors
604 bool "Marvell MV78xx0"
607 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
609 select NEED_MACH_IO_H
612 Support for the following Marvell MV78xx0 series SoCs:
620 select ARCH_REQUIRE_GPIOLIB
621 select GENERIC_CLOCKEVENTS
624 Support for the following Marvell Orion 5x series SoCs:
625 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
626 Orion-2 (5281), Orion-1-90 (6183).
629 bool "Marvell PXA168/910/MMP2"
631 select ARCH_REQUIRE_GPIOLIB
633 select GENERIC_CLOCKEVENTS
638 select GENERIC_ALLOCATOR
640 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
643 bool "Micrel/Kendin KS8695"
645 select ARCH_REQUIRE_GPIOLIB
646 select ARCH_USES_GETTIMEOFFSET
647 select NEED_MACH_MEMORY_H
649 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
650 System-on-Chip devices.
653 bool "Nuvoton W90X900 CPU"
655 select ARCH_REQUIRE_GPIOLIB
658 select GENERIC_CLOCKEVENTS
660 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
661 At present, the w90x900 has been renamed nuc900, regarding
662 the ARM series product line, you can login the following
663 link address to know more.
665 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
666 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
672 select GENERIC_CLOCKEVENTS
676 select MIGHT_HAVE_CACHE_L2X0
677 select NEED_MACH_IO_H if PCI
678 select ARCH_HAS_CPUFREQ
680 This enables support for NVIDIA Tegra based systems (Tegra APX,
681 Tegra 6xx and Tegra 2 series).
683 config ARCH_PICOXCELL
684 bool "Picochip picoXcell"
685 select ARCH_REQUIRE_GPIOLIB
686 select ARM_PATCH_PHYS_VIRT
690 select GENERIC_CLOCKEVENTS
697 This enables support for systems based on the Picochip picoXcell
698 family of Femtocell devices. The picoxcell support requires device tree
702 bool "Philips Nexperia PNX4008 Mobile"
705 select ARCH_USES_GETTIMEOFFSET
707 This enables support for Philips PNX4008 mobile platform.
710 bool "PXA2xx/PXA3xx-based"
713 select ARCH_HAS_CPUFREQ
716 select ARCH_REQUIRE_GPIOLIB
717 select GENERIC_CLOCKEVENTS
723 select MULTI_IRQ_HANDLER
724 select ARM_CPU_SUSPEND if PM
727 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
732 select GENERIC_CLOCKEVENTS
733 select ARCH_REQUIRE_GPIOLIB
736 Support for Qualcomm MSM/QSD based systems. This runs on the
737 apps processor of the MSM/QSD and depends on a shared memory
738 interface to the modem processor which runs the baseband
739 stack and controls some vital subsystems
740 (clock and power control, etc).
743 bool "Renesas SH-Mobile / R-Mobile"
746 select HAVE_MACH_CLKDEV
748 select GENERIC_CLOCKEVENTS
749 select MIGHT_HAVE_CACHE_L2X0
752 select MULTI_IRQ_HANDLER
753 select PM_GENERIC_DOMAINS if PM
754 select NEED_MACH_MEMORY_H
756 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
762 select ARCH_MAY_HAVE_PC_FDC
763 select HAVE_PATA_PLATFORM
766 select ARCH_SPARSEMEM_ENABLE
767 select ARCH_USES_GETTIMEOFFSET
769 select NEED_MACH_IO_H
770 select NEED_MACH_MEMORY_H
772 On the Acorn Risc-PC, Linux can support the internal IDE disk and
773 CD-ROM interface, serial and parallel port, and the floppy drive.
780 select ARCH_SPARSEMEM_ENABLE
782 select ARCH_HAS_CPUFREQ
784 select GENERIC_CLOCKEVENTS
787 select ARCH_REQUIRE_GPIOLIB
789 select NEED_MACH_MEMORY_H
792 Support for StrongARM 11x0 based boards.
795 bool "Samsung S3C24XX SoCs"
797 select ARCH_HAS_CPUFREQ
800 select ARCH_USES_GETTIMEOFFSET
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C_RTC if RTC_CLASS
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 select NEED_MACH_IO_H
806 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
807 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
808 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
809 Samsung SMDK2410 development board (and derivatives).
812 bool "Samsung S3C64XX"
820 select ARCH_USES_GETTIMEOFFSET
821 select ARCH_HAS_CPUFREQ
822 select ARCH_REQUIRE_GPIOLIB
823 select SAMSUNG_CLKSRC
824 select SAMSUNG_IRQ_VIC_TIMER
825 select S3C_GPIO_TRACK
827 select USB_ARCH_HAS_OHCI
828 select SAMSUNG_GPIOLIB_4BIT
829 select HAVE_S3C2410_I2C if I2C
830 select HAVE_S3C2410_WATCHDOG if WATCHDOG
832 Samsung S3C64XX series based systems
835 bool "Samsung S5P6440 S5P6450"
841 select HAVE_S3C2410_WATCHDOG if WATCHDOG
842 select GENERIC_CLOCKEVENTS
843 select HAVE_S3C2410_I2C if I2C
844 select HAVE_S3C_RTC if RTC_CLASS
846 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
850 bool "Samsung S5PC100"
855 select ARCH_USES_GETTIMEOFFSET
856 select HAVE_S3C2410_I2C if I2C
857 select HAVE_S3C_RTC if RTC_CLASS
858 select HAVE_S3C2410_WATCHDOG if WATCHDOG
860 Samsung S5PC100 series based systems
863 bool "Samsung S5PV210/S5PC110"
865 select ARCH_SPARSEMEM_ENABLE
866 select ARCH_HAS_HOLES_MEMORYMODEL
871 select ARCH_HAS_CPUFREQ
872 select GENERIC_CLOCKEVENTS
873 select HAVE_S3C2410_I2C if I2C
874 select HAVE_S3C_RTC if RTC_CLASS
875 select HAVE_S3C2410_WATCHDOG if WATCHDOG
876 select NEED_MACH_MEMORY_H
878 Samsung S5PV210/S5PC110 series based systems
881 bool "SAMSUNG EXYNOS"
883 select ARCH_SPARSEMEM_ENABLE
884 select ARCH_HAS_HOLES_MEMORYMODEL
888 select ARCH_HAS_CPUFREQ
889 select GENERIC_CLOCKEVENTS
890 select HAVE_S3C_RTC if RTC_CLASS
891 select HAVE_S3C2410_I2C if I2C
892 select HAVE_S3C2410_WATCHDOG if WATCHDOG
893 select NEED_MACH_MEMORY_H
895 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
904 select ARCH_USES_GETTIMEOFFSET
905 select NEED_MACH_MEMORY_H
906 select NEED_MACH_IO_H
908 Support for the StrongARM based Digital DNARD machine, also known
909 as "Shark" (<http://www.shark-linux.de/shark.html>).
912 bool "ST-Ericsson U300 Series"
918 select ARM_PATCH_PHYS_VIRT
920 select GENERIC_CLOCKEVENTS
922 select HAVE_MACH_CLKDEV
924 select ARCH_REQUIRE_GPIOLIB
926 Support for ST-Ericsson U300 series mobile platforms.
929 bool "ST-Ericsson U8500 Series"
933 select GENERIC_CLOCKEVENTS
935 select ARCH_REQUIRE_GPIOLIB
936 select ARCH_HAS_CPUFREQ
938 select MIGHT_HAVE_CACHE_L2X0
940 Support for ST-Ericsson's Ux500 architecture
943 bool "STMicroelectronics Nomadik"
948 select GENERIC_CLOCKEVENTS
949 select MIGHT_HAVE_CACHE_L2X0
950 select ARCH_REQUIRE_GPIOLIB
952 Support for the Nomadik platform by ST-Ericsson
956 select GENERIC_CLOCKEVENTS
957 select ARCH_REQUIRE_GPIOLIB
961 select GENERIC_ALLOCATOR
962 select GENERIC_IRQ_CHIP
963 select ARCH_HAS_HOLES_MEMORYMODEL
965 Support for TI's DaVinci platform.
970 select ARCH_REQUIRE_GPIOLIB
971 select ARCH_HAS_CPUFREQ
973 select GENERIC_CLOCKEVENTS
974 select ARCH_HAS_HOLES_MEMORYMODEL
976 Support for TI's OMAP platform (OMAP1/2/3/4).
981 select ARCH_REQUIRE_GPIOLIB
984 select GENERIC_CLOCKEVENTS
987 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
990 bool "VIA/WonderMedia 85xx"
993 select ARCH_HAS_CPUFREQ
994 select GENERIC_CLOCKEVENTS
995 select ARCH_REQUIRE_GPIOLIB
998 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1001 bool "Xilinx Zynq ARM Cortex A9 Platform"
1003 select GENERIC_CLOCKEVENTS
1004 select CLKDEV_LOOKUP
1008 select MIGHT_HAVE_CACHE_L2X0
1011 Support for Xilinx Zynq ARM Cortex A9 Platform
1015 # This is sorted alphabetically by mach-* pathname. However, plat-*
1016 # Kconfigs may be included either alphabetically (according to the
1017 # plat- suffix) or along side the corresponding mach-* source.
1019 source "arch/arm/mach-at91/Kconfig"
1021 source "arch/arm/mach-bcmring/Kconfig"
1023 source "arch/arm/mach-clps711x/Kconfig"
1025 source "arch/arm/mach-cns3xxx/Kconfig"
1027 source "arch/arm/mach-davinci/Kconfig"
1029 source "arch/arm/mach-dove/Kconfig"
1031 source "arch/arm/mach-ep93xx/Kconfig"
1033 source "arch/arm/mach-footbridge/Kconfig"
1035 source "arch/arm/mach-gemini/Kconfig"
1037 source "arch/arm/mach-h720x/Kconfig"
1039 source "arch/arm/mach-integrator/Kconfig"
1041 source "arch/arm/mach-iop32x/Kconfig"
1043 source "arch/arm/mach-iop33x/Kconfig"
1045 source "arch/arm/mach-iop13xx/Kconfig"
1047 source "arch/arm/mach-ixp4xx/Kconfig"
1049 source "arch/arm/mach-ixp2000/Kconfig"
1051 source "arch/arm/mach-ixp23xx/Kconfig"
1053 source "arch/arm/mach-kirkwood/Kconfig"
1055 source "arch/arm/mach-ks8695/Kconfig"
1057 source "arch/arm/mach-lpc32xx/Kconfig"
1059 source "arch/arm/mach-msm/Kconfig"
1061 source "arch/arm/mach-mv78xx0/Kconfig"
1063 source "arch/arm/plat-mxc/Kconfig"
1065 source "arch/arm/mach-mxs/Kconfig"
1067 source "arch/arm/mach-netx/Kconfig"
1069 source "arch/arm/mach-nomadik/Kconfig"
1070 source "arch/arm/plat-nomadik/Kconfig"
1072 source "arch/arm/plat-omap/Kconfig"
1074 source "arch/arm/mach-omap1/Kconfig"
1076 source "arch/arm/mach-omap2/Kconfig"
1078 source "arch/arm/mach-orion5x/Kconfig"
1080 source "arch/arm/mach-pxa/Kconfig"
1081 source "arch/arm/plat-pxa/Kconfig"
1083 source "arch/arm/mach-mmp/Kconfig"
1085 source "arch/arm/mach-realview/Kconfig"
1087 source "arch/arm/mach-sa1100/Kconfig"
1089 source "arch/arm/plat-samsung/Kconfig"
1090 source "arch/arm/plat-s3c24xx/Kconfig"
1091 source "arch/arm/plat-s5p/Kconfig"
1093 source "arch/arm/plat-spear/Kconfig"
1095 source "arch/arm/mach-s3c24xx/Kconfig"
1097 source "arch/arm/mach-s3c2412/Kconfig"
1098 source "arch/arm/mach-s3c2440/Kconfig"
1102 source "arch/arm/mach-s3c64xx/Kconfig"
1105 source "arch/arm/mach-s5p64x0/Kconfig"
1107 source "arch/arm/mach-s5pc100/Kconfig"
1109 source "arch/arm/mach-s5pv210/Kconfig"
1111 source "arch/arm/mach-exynos/Kconfig"
1113 source "arch/arm/mach-shmobile/Kconfig"
1115 source "arch/arm/mach-tegra/Kconfig"
1117 source "arch/arm/mach-u300/Kconfig"
1119 source "arch/arm/mach-ux500/Kconfig"
1121 source "arch/arm/mach-versatile/Kconfig"
1123 source "arch/arm/mach-vexpress/Kconfig"
1124 source "arch/arm/plat-versatile/Kconfig"
1126 source "arch/arm/mach-vt8500/Kconfig"
1128 source "arch/arm/mach-w90x900/Kconfig"
1130 # Definitions to make life easier
1136 select GENERIC_CLOCKEVENTS
1141 select GENERIC_IRQ_CHIP
1146 config PLAT_VERSATILE
1149 config ARM_TIMER_SP804
1152 select HAVE_SCHED_CLOCK
1154 source arch/arm/mm/Kconfig
1158 default 16 if ARCH_EP93XX
1162 bool "Enable iWMMXt support"
1163 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1164 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1166 Enable support for iWMMXt context switching at run time if
1167 running on a CPU that supports it.
1171 depends on CPU_XSCALE
1175 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1176 (!ARCH_OMAP3 || OMAP3_EMU)
1180 config MULTI_IRQ_HANDLER
1183 Allow each machine to specify it's own IRQ handler at run time.
1186 source "arch/arm/Kconfig-nommu"
1189 config ARM_ERRATA_411920
1190 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1191 depends on CPU_V6 || CPU_V6K
1193 Invalidation of the Instruction Cache operation can
1194 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1195 It does not affect the MPCore. This option enables the ARM Ltd.
1196 recommended workaround.
1198 config ARM_ERRATA_430973
1199 bool "ARM errata: Stale prediction on replaced interworking branch"
1202 This option enables the workaround for the 430973 Cortex-A8
1203 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1204 interworking branch is replaced with another code sequence at the
1205 same virtual address, whether due to self-modifying code or virtual
1206 to physical address re-mapping, Cortex-A8 does not recover from the
1207 stale interworking branch prediction. This results in Cortex-A8
1208 executing the new code sequence in the incorrect ARM or Thumb state.
1209 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1210 and also flushes the branch target cache at every context switch.
1211 Note that setting specific bits in the ACTLR register may not be
1212 available in non-secure mode.
1214 config ARM_ERRATA_458693
1215 bool "ARM errata: Processor deadlock when a false hazard is created"
1218 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1219 erratum. For very specific sequences of memory operations, it is
1220 possible for a hazard condition intended for a cache line to instead
1221 be incorrectly associated with a different cache line. This false
1222 hazard might then cause a processor deadlock. The workaround enables
1223 the L1 caching of the NEON accesses and disables the PLD instruction
1224 in the ACTLR register. Note that setting specific bits in the ACTLR
1225 register may not be available in non-secure mode.
1227 config ARM_ERRATA_460075
1228 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1231 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1232 erratum. Any asynchronous access to the L2 cache may encounter a
1233 situation in which recent store transactions to the L2 cache are lost
1234 and overwritten with stale memory contents from external memory. The
1235 workaround disables the write-allocate mode for the L2 cache via the
1236 ACTLR register. Note that setting specific bits in the ACTLR register
1237 may not be available in non-secure mode.
1239 config ARM_ERRATA_742230
1240 bool "ARM errata: DMB operation may be faulty"
1241 depends on CPU_V7 && SMP
1243 This option enables the workaround for the 742230 Cortex-A9
1244 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1245 between two write operations may not ensure the correct visibility
1246 ordering of the two writes. This workaround sets a specific bit in
1247 the diagnostic register of the Cortex-A9 which causes the DMB
1248 instruction to behave as a DSB, ensuring the correct behaviour of
1251 config ARM_ERRATA_742231
1252 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1253 depends on CPU_V7 && SMP
1255 This option enables the workaround for the 742231 Cortex-A9
1256 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1257 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1258 accessing some data located in the same cache line, may get corrupted
1259 data due to bad handling of the address hazard when the line gets
1260 replaced from one of the CPUs at the same time as another CPU is
1261 accessing it. This workaround sets specific bits in the diagnostic
1262 register of the Cortex-A9 which reduces the linefill issuing
1263 capabilities of the processor.
1265 config PL310_ERRATA_588369
1266 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1267 depends on CACHE_L2X0
1269 The PL310 L2 cache controller implements three types of Clean &
1270 Invalidate maintenance operations: by Physical Address
1271 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1272 They are architecturally defined to behave as the execution of a
1273 clean operation followed immediately by an invalidate operation,
1274 both performing to the same memory location. This functionality
1275 is not correctly implemented in PL310 as clean lines are not
1276 invalidated as a result of these operations.
1278 config ARM_ERRATA_720789
1279 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1282 This option enables the workaround for the 720789 Cortex-A9 (prior to
1283 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1284 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1285 As a consequence of this erratum, some TLB entries which should be
1286 invalidated are not, resulting in an incoherency in the system page
1287 tables. The workaround changes the TLB flushing routines to invalidate
1288 entries regardless of the ASID.
1290 config PL310_ERRATA_727915
1291 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1292 depends on CACHE_L2X0
1294 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1295 operation (offset 0x7FC). This operation runs in background so that
1296 PL310 can handle normal accesses while it is in progress. Under very
1297 rare circumstances, due to this erratum, write data can be lost when
1298 PL310 treats a cacheable write transaction during a Clean &
1299 Invalidate by Way operation.
1301 config ARM_ERRATA_743622
1302 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1305 This option enables the workaround for the 743622 Cortex-A9
1306 (r2p*) erratum. Under very rare conditions, a faulty
1307 optimisation in the Cortex-A9 Store Buffer may lead to data
1308 corruption. This workaround sets a specific bit in the diagnostic
1309 register of the Cortex-A9 which disables the Store Buffer
1310 optimisation, preventing the defect from occurring. This has no
1311 visible impact on the overall performance or power consumption of the
1314 config ARM_ERRATA_751472
1315 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1318 This option enables the workaround for the 751472 Cortex-A9 (prior
1319 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1320 completion of a following broadcasted operation if the second
1321 operation is received by a CPU before the ICIALLUIS has completed,
1322 potentially leading to corrupted entries in the cache or TLB.
1324 config PL310_ERRATA_753970
1325 bool "PL310 errata: cache sync operation may be faulty"
1326 depends on CACHE_PL310
1328 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1330 Under some condition the effect of cache sync operation on
1331 the store buffer still remains when the operation completes.
1332 This means that the store buffer is always asked to drain and
1333 this prevents it from merging any further writes. The workaround
1334 is to replace the normal offset of cache sync operation (0x730)
1335 by another offset targeting an unmapped PL310 register 0x740.
1336 This has the same effect as the cache sync operation: store buffer
1337 drain and waiting for all buffers empty.
1339 config ARM_ERRATA_754322
1340 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1343 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1344 r3p*) erratum. A speculative memory access may cause a page table walk
1345 which starts prior to an ASID switch but completes afterwards. This
1346 can populate the micro-TLB with a stale entry which may be hit with
1347 the new ASID. This workaround places two dsb instructions in the mm
1348 switching code so that no page table walks can cross the ASID switch.
1350 config ARM_ERRATA_754327
1351 bool "ARM errata: no automatic Store Buffer drain"
1352 depends on CPU_V7 && SMP
1354 This option enables the workaround for the 754327 Cortex-A9 (prior to
1355 r2p0) erratum. The Store Buffer does not have any automatic draining
1356 mechanism and therefore a livelock may occur if an external agent
1357 continuously polls a memory location waiting to observe an update.
1358 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1359 written polling loops from denying visibility of updates to memory.
1361 config ARM_ERRATA_364296
1362 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1363 depends on CPU_V6 && !SMP
1365 This options enables the workaround for the 364296 ARM1136
1366 r0p2 erratum (possible cache data corruption with
1367 hit-under-miss enabled). It sets the undocumented bit 31 in
1368 the auxiliary control register and the FI bit in the control
1369 register, thus disabling hit-under-miss without putting the
1370 processor into full low interrupt latency mode. ARM11MPCore
1373 config ARM_ERRATA_764369
1374 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1375 depends on CPU_V7 && SMP
1377 This option enables the workaround for erratum 764369
1378 affecting Cortex-A9 MPCore with two or more processors (all
1379 current revisions). Under certain timing circumstances, a data
1380 cache line maintenance operation by MVA targeting an Inner
1381 Shareable memory region may fail to proceed up to either the
1382 Point of Coherency or to the Point of Unification of the
1383 system. This workaround adds a DSB instruction before the
1384 relevant cache maintenance functions and sets a specific bit
1385 in the diagnostic control register of the SCU.
1387 config PL310_ERRATA_769419
1388 bool "PL310 errata: no automatic Store Buffer drain"
1389 depends on CACHE_L2X0
1391 On revisions of the PL310 prior to r3p2, the Store Buffer does
1392 not automatically drain. This can cause normal, non-cacheable
1393 writes to be retained when the memory system is idle, leading
1394 to suboptimal I/O performance for drivers using coherent DMA.
1395 This option adds a write barrier to the cpu_idle loop so that,
1396 on systems with an outer cache, the store buffer is drained
1401 source "arch/arm/common/Kconfig"
1411 Find out whether you have ISA slots on your motherboard. ISA is the
1412 name of a bus system, i.e. the way the CPU talks to the other stuff
1413 inside your box. Other bus systems are PCI, EISA, MicroChannel
1414 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1415 newer boards don't support it. If you have ISA, say Y, otherwise N.
1417 # Select ISA DMA controller support
1422 # Select ISA DMA interface
1427 bool "PCI support" if MIGHT_HAVE_PCI
1429 Find out whether you have a PCI motherboard. PCI is the name of a
1430 bus system, i.e. the way the CPU talks to the other stuff inside
1431 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1432 VESA. If you have PCI, say Y, otherwise N.
1438 config PCI_NANOENGINE
1439 bool "BSE nanoEngine PCI support"
1440 depends on SA1100_NANOENGINE
1442 Enable PCI on the BSE nanoEngine board.
1447 # Select the host bridge type
1448 config PCI_HOST_VIA82C505
1450 depends on PCI && ARCH_SHARK
1453 config PCI_HOST_ITE8152
1455 depends on PCI && MACH_ARMCORE
1459 source "drivers/pci/Kconfig"
1461 source "drivers/pcmcia/Kconfig"
1465 menu "Kernel Features"
1467 source "kernel/time/Kconfig"
1472 This option should be selected by machines which have an SMP-
1475 The only effect of this option is to make the SMP-related
1476 options available to the user for configuration.
1479 bool "Symmetric Multi-Processing"
1480 depends on CPU_V6K || CPU_V7
1481 depends on GENERIC_CLOCKEVENTS
1484 select USE_GENERIC_SMP_HELPERS
1485 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1487 This enables support for systems with more than one CPU. If you have
1488 a system with only one CPU, like most personal computers, say N. If
1489 you have a system with more than one CPU, say Y.
1491 If you say N here, the kernel will run on single and multiprocessor
1492 machines, but will use only one CPU of a multiprocessor machine. If
1493 you say Y here, the kernel will run on many, but not all, single
1494 processor machines. On a single processor machine, the kernel will
1495 run faster if you say N here.
1497 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1498 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1499 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1501 If you don't know what to do here, say N.
1504 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1505 depends on EXPERIMENTAL
1506 depends on SMP && !XIP_KERNEL
1509 SMP kernels contain instructions which fail on non-SMP processors.
1510 Enabling this option allows the kernel to modify itself to make
1511 these instructions safe. Disabling it allows about 1K of space
1514 If you don't know what to do here, say Y.
1516 config ARM_CPU_TOPOLOGY
1517 bool "Support cpu topology definition"
1518 depends on SMP && CPU_V7
1521 Support ARM cpu topology definition. The MPIDR register defines
1522 affinity between processors which is then used to describe the cpu
1523 topology of an ARM System.
1526 bool "Multi-core scheduler support"
1527 depends on ARM_CPU_TOPOLOGY
1529 Multi-core scheduler support improves the CPU scheduler's decision
1530 making when dealing with multi-core CPU chips at a cost of slightly
1531 increased overhead in some places. If unsure say N here.
1534 bool "SMT scheduler support"
1535 depends on ARM_CPU_TOPOLOGY
1537 Improves the CPU scheduler's decision making when dealing with
1538 MultiThreading at a cost of slightly increased overhead in some
1539 places. If unsure say N here.
1544 This option enables support for the ARM system coherency unit
1551 This options enables support for the ARM timer and watchdog unit
1554 prompt "Memory split"
1557 Select the desired split between kernel and user memory.
1559 If you are not absolutely sure what you are doing, leave this
1563 bool "3G/1G user/kernel split"
1565 bool "2G/2G user/kernel split"
1567 bool "1G/3G user/kernel split"
1572 default 0x40000000 if VMSPLIT_1G
1573 default 0x80000000 if VMSPLIT_2G
1577 int "Maximum number of CPUs (2-32)"
1583 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1584 depends on SMP && HOTPLUG && EXPERIMENTAL
1586 Say Y here to experiment with turning CPUs off and on. CPUs
1587 can be controlled through /sys/devices/system/cpu.
1590 bool "Use local timer interrupts"
1593 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1595 Enable support for local timers on SMP platforms, rather then the
1596 legacy IPI broadcast method. Local timers allows the system
1597 accounting to be spread across the timer interval, preventing a
1598 "thundering herd" at every timer tick.
1602 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1603 default 355 if ARCH_U8500
1604 default 264 if MACH_H4700
1607 Maximum number of GPIOs in the system.
1609 If unsure, leave the default value.
1611 source kernel/Kconfig.preempt
1615 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1616 ARCH_S5PV210 || ARCH_EXYNOS4
1617 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1618 default AT91_TIMER_HZ if ARCH_AT91
1619 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1622 config THUMB2_KERNEL
1623 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1624 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1626 select ARM_ASM_UNIFIED
1629 By enabling this option, the kernel will be compiled in
1630 Thumb-2 mode. A compiler/assembler that understand the unified
1631 ARM-Thumb syntax is needed.
1635 config THUMB2_AVOID_R_ARM_THM_JUMP11
1636 bool "Work around buggy Thumb-2 short branch relocations in gas"
1637 depends on THUMB2_KERNEL && MODULES
1640 Various binutils versions can resolve Thumb-2 branches to
1641 locally-defined, preemptible global symbols as short-range "b.n"
1642 branch instructions.
1644 This is a problem, because there's no guarantee the final
1645 destination of the symbol, or any candidate locations for a
1646 trampoline, are within range of the branch. For this reason, the
1647 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1648 relocation in modules at all, and it makes little sense to add
1651 The symptom is that the kernel fails with an "unsupported
1652 relocation" error when loading some modules.
1654 Until fixed tools are available, passing
1655 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1656 code which hits this problem, at the cost of a bit of extra runtime
1657 stack usage in some cases.
1659 The problem is described in more detail at:
1660 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1662 Only Thumb-2 kernels are affected.
1664 Unless you are sure your tools don't have this problem, say Y.
1666 config ARM_ASM_UNIFIED
1670 bool "Use the ARM EABI to compile the kernel"
1672 This option allows for the kernel to be compiled using the latest
1673 ARM ABI (aka EABI). This is only useful if you are using a user
1674 space environment that is also compiled with EABI.
1676 Since there are major incompatibilities between the legacy ABI and
1677 EABI, especially with regard to structure member alignment, this
1678 option also changes the kernel syscall calling convention to
1679 disambiguate both ABIs and allow for backward compatibility support
1680 (selected with CONFIG_OABI_COMPAT).
1682 To use this you need GCC version 4.0.0 or later.
1685 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1686 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1689 This option preserves the old syscall interface along with the
1690 new (ARM EABI) one. It also provides a compatibility layer to
1691 intercept syscalls that have structure arguments which layout
1692 in memory differs between the legacy ABI and the new ARM EABI
1693 (only for non "thumb" binaries). This option adds a tiny
1694 overhead to all syscalls and produces a slightly larger kernel.
1695 If you know you'll be using only pure EABI user space then you
1696 can say N here. If this option is not selected and you attempt
1697 to execute a legacy ABI binary then the result will be
1698 UNPREDICTABLE (in fact it can be predicted that it won't work
1699 at all). If in doubt say Y.
1701 config ARCH_HAS_HOLES_MEMORYMODEL
1704 config ARCH_SPARSEMEM_ENABLE
1707 config ARCH_SPARSEMEM_DEFAULT
1708 def_bool ARCH_SPARSEMEM_ENABLE
1710 config ARCH_SELECT_MEMORY_MODEL
1711 def_bool ARCH_SPARSEMEM_ENABLE
1713 config HAVE_ARCH_PFN_VALID
1714 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1717 bool "High Memory Support"
1720 The address space of ARM processors is only 4 Gigabytes large
1721 and it has to accommodate user address space, kernel address
1722 space as well as some memory mapped IO. That means that, if you
1723 have a large amount of physical memory and/or IO, not all of the
1724 memory can be "permanently mapped" by the kernel. The physical
1725 memory that is not permanently mapped is called "high memory".
1727 Depending on the selected kernel/user memory split, minimum
1728 vmalloc space and actual amount of RAM, you may not need this
1729 option which should result in a slightly faster kernel.
1734 bool "Allocate 2nd-level pagetables from highmem"
1737 config HW_PERF_EVENTS
1738 bool "Enable hardware performance counter support for perf events"
1739 depends on PERF_EVENTS && CPU_HAS_PMU
1742 Enable hardware performance counter support for perf events. If
1743 disabled, perf events will use software events only.
1747 config FORCE_MAX_ZONEORDER
1748 int "Maximum zone order" if ARCH_SHMOBILE
1749 range 11 64 if ARCH_SHMOBILE
1750 default "9" if SA1111
1753 The kernel memory allocator divides physically contiguous memory
1754 blocks into "zones", where each zone is a power of two number of
1755 pages. This option selects the largest power of two that the kernel
1756 keeps in the memory allocator. If you need to allocate very large
1757 blocks of physically contiguous memory, then you may need to
1758 increase this value.
1760 This config option is actually maximum order plus one. For example,
1761 a value of 11 means that the largest free memory block is 2^10 pages.
1764 bool "Timer and CPU usage LEDs"
1765 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1766 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1767 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1768 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1769 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1770 ARCH_AT91 || ARCH_DAVINCI || \
1771 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1773 If you say Y here, the LEDs on your machine will be used
1774 to provide useful information about your current system status.
1776 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1777 be able to select which LEDs are active using the options below. If
1778 you are compiling a kernel for the EBSA-110 or the LART however, the
1779 red LED will simply flash regularly to indicate that the system is
1780 still functional. It is safe to say Y here if you have a CATS
1781 system, but the driver will do nothing.
1784 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1785 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1786 || MACH_OMAP_PERSEUS2
1788 depends on !GENERIC_CLOCKEVENTS
1789 default y if ARCH_EBSA110
1791 If you say Y here, one of the system LEDs (the green one on the
1792 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1793 will flash regularly to indicate that the system is still
1794 operational. This is mainly useful to kernel hackers who are
1795 debugging unstable kernels.
1797 The LART uses the same LED for both Timer LED and CPU usage LED
1798 functions. You may choose to use both, but the Timer LED function
1799 will overrule the CPU usage LED.
1802 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1804 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1805 || MACH_OMAP_PERSEUS2
1808 If you say Y here, the red LED will be used to give a good real
1809 time indication of CPU usage, by lighting whenever the idle task
1810 is not currently executing.
1812 The LART uses the same LED for both Timer LED and CPU usage LED
1813 functions. You may choose to use both, but the Timer LED function
1814 will overrule the CPU usage LED.
1816 config ALIGNMENT_TRAP
1818 depends on CPU_CP15_MMU
1819 default y if !ARCH_EBSA110
1820 select HAVE_PROC_CPU if PROC_FS
1822 ARM processors cannot fetch/store information which is not
1823 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1824 address divisible by 4. On 32-bit ARM processors, these non-aligned
1825 fetch/store instructions will be emulated in software if you say
1826 here, which has a severe performance impact. This is necessary for
1827 correct operation of some network protocols. With an IP-only
1828 configuration it is safe to say N, otherwise say Y.
1830 config UACCESS_WITH_MEMCPY
1831 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1832 depends on MMU && EXPERIMENTAL
1833 default y if CPU_FEROCEON
1835 Implement faster copy_to_user and clear_user methods for CPU
1836 cores where a 8-word STM instruction give significantly higher
1837 memory write throughput than a sequence of individual 32bit stores.
1839 A possible side effect is a slight increase in scheduling latency
1840 between threads sharing the same address space if they invoke
1841 such copy operations with large buffers.
1843 However, if the CPU data cache is using a write-allocate mode,
1844 this option is unlikely to provide any performance gain.
1848 prompt "Enable seccomp to safely compute untrusted bytecode"
1850 This kernel feature is useful for number crunching applications
1851 that may need to compute untrusted bytecode during their
1852 execution. By using pipes or other transports made available to
1853 the process as file descriptors supporting the read/write
1854 syscalls, it's possible to isolate those applications in
1855 their own address space using seccomp. Once seccomp is
1856 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1857 and the task is only allowed to execute a few safe syscalls
1858 defined by each seccomp mode.
1860 config CC_STACKPROTECTOR
1861 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1862 depends on EXPERIMENTAL
1864 This option turns on the -fstack-protector GCC feature. This
1865 feature puts, at the beginning of functions, a canary value on
1866 the stack just before the return address, and validates
1867 the value just before actually returning. Stack based buffer
1868 overflows (that need to overwrite this return address) now also
1869 overwrite the canary, which gets detected and the attack is then
1870 neutralized via a kernel panic.
1871 This feature requires gcc version 4.2 or above.
1873 config DEPRECATED_PARAM_STRUCT
1874 bool "Provide old way to pass kernel parameters"
1876 This was deprecated in 2001 and announced to live on for 5 years.
1877 Some old boot loaders still use this way.
1884 bool "Flattened Device Tree support"
1886 select OF_EARLY_FLATTREE
1889 Include support for flattened device tree machine descriptions.
1891 # Compressed boot loader in ROM. Yes, we really want to ask about
1892 # TEXT and BSS so we preserve their values in the config files.
1893 config ZBOOT_ROM_TEXT
1894 hex "Compressed ROM boot loader base address"
1897 The physical address at which the ROM-able zImage is to be
1898 placed in the target. Platforms which normally make use of
1899 ROM-able zImage formats normally set this to a suitable
1900 value in their defconfig file.
1902 If ZBOOT_ROM is not enabled, this has no effect.
1904 config ZBOOT_ROM_BSS
1905 hex "Compressed ROM boot loader BSS address"
1908 The base address of an area of read/write memory in the target
1909 for the ROM-able zImage which must be available while the
1910 decompressor is running. It must be large enough to hold the
1911 entire decompressed kernel plus an additional 128 KiB.
1912 Platforms which normally make use of ROM-able zImage formats
1913 normally set this to a suitable value in their defconfig file.
1915 If ZBOOT_ROM is not enabled, this has no effect.
1918 bool "Compressed boot loader in ROM/flash"
1919 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1921 Say Y here if you intend to execute your compressed kernel image
1922 (zImage) directly from ROM or flash. If unsure, say N.
1925 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1926 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1927 default ZBOOT_ROM_NONE
1929 Include experimental SD/MMC loading code in the ROM-able zImage.
1930 With this enabled it is possible to write the the ROM-able zImage
1931 kernel image to an MMC or SD card and boot the kernel straight
1932 from the reset vector. At reset the processor Mask ROM will load
1933 the first part of the the ROM-able zImage which in turn loads the
1934 rest the kernel image to RAM.
1936 config ZBOOT_ROM_NONE
1937 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1939 Do not load image from SD or MMC
1941 config ZBOOT_ROM_MMCIF
1942 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1944 Load image from MMCIF hardware block.
1946 config ZBOOT_ROM_SH_MOBILE_SDHI
1947 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1949 Load image from SDHI hardware block
1953 config ARM_APPENDED_DTB
1954 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1955 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1957 With this option, the boot code will look for a device tree binary
1958 (DTB) appended to zImage
1959 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1961 This is meant as a backward compatibility convenience for those
1962 systems with a bootloader that can't be upgraded to accommodate
1963 the documented boot protocol using a device tree.
1965 Beware that there is very little in terms of protection against
1966 this option being confused by leftover garbage in memory that might
1967 look like a DTB header after a reboot if no actual DTB is appended
1968 to zImage. Do not leave this option active in a production kernel
1969 if you don't intend to always append a DTB. Proper passing of the
1970 location into r2 of a bootloader provided DTB is always preferable
1973 config ARM_ATAG_DTB_COMPAT
1974 bool "Supplement the appended DTB with traditional ATAG information"
1975 depends on ARM_APPENDED_DTB
1977 Some old bootloaders can't be updated to a DTB capable one, yet
1978 they provide ATAGs with memory configuration, the ramdisk address,
1979 the kernel cmdline string, etc. Such information is dynamically
1980 provided by the bootloader and can't always be stored in a static
1981 DTB. To allow a device tree enabled kernel to be used with such
1982 bootloaders, this option allows zImage to extract the information
1983 from the ATAG list and store it at run time into the appended DTB.
1986 string "Default kernel command string"
1989 On some architectures (EBSA110 and CATS), there is currently no way
1990 for the boot loader to pass arguments to the kernel. For these
1991 architectures, you should supply some command-line options at build
1992 time by entering them here. As a minimum, you should specify the
1993 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1996 prompt "Kernel command line type" if CMDLINE != ""
1997 default CMDLINE_FROM_BOOTLOADER
1999 config CMDLINE_FROM_BOOTLOADER
2000 bool "Use bootloader kernel arguments if available"
2002 Uses the command-line options passed by the boot loader. If
2003 the boot loader doesn't provide any, the default kernel command
2004 string provided in CMDLINE will be used.
2006 config CMDLINE_EXTEND
2007 bool "Extend bootloader kernel arguments"
2009 The command-line arguments provided by the boot loader will be
2010 appended to the default kernel command string.
2012 config CMDLINE_FORCE
2013 bool "Always use the default kernel command string"
2015 Always use the default kernel command string, even if the boot
2016 loader passes other arguments to the kernel.
2017 This is useful if you cannot or don't want to change the
2018 command-line options your boot loader passes to the kernel.
2022 bool "Kernel Execute-In-Place from ROM"
2023 depends on !ZBOOT_ROM && !ARM_LPAE
2025 Execute-In-Place allows the kernel to run from non-volatile storage
2026 directly addressable by the CPU, such as NOR flash. This saves RAM
2027 space since the text section of the kernel is not loaded from flash
2028 to RAM. Read-write sections, such as the data section and stack,
2029 are still copied to RAM. The XIP kernel is not compressed since
2030 it has to run directly from flash, so it will take more space to
2031 store it. The flash address used to link the kernel object files,
2032 and for storing it, is configuration dependent. Therefore, if you
2033 say Y here, you must know the proper physical address where to
2034 store the kernel image depending on your own flash memory usage.
2036 Also note that the make target becomes "make xipImage" rather than
2037 "make zImage" or "make Image". The final kernel binary to put in
2038 ROM memory will be arch/arm/boot/xipImage.
2042 config XIP_PHYS_ADDR
2043 hex "XIP Kernel Physical Location"
2044 depends on XIP_KERNEL
2045 default "0x00080000"
2047 This is the physical address in your flash memory the kernel will
2048 be linked for and stored to. This address is dependent on your
2052 bool "Kexec system call (EXPERIMENTAL)"
2053 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2055 kexec is a system call that implements the ability to shutdown your
2056 current kernel, and to start another kernel. It is like a reboot
2057 but it is independent of the system firmware. And like a reboot
2058 you can start any kernel with it, not just Linux.
2060 It is an ongoing process to be certain the hardware in a machine
2061 is properly shutdown, so do not be surprised if this code does not
2062 initially work for you. It may help to enable device hotplugging
2066 bool "Export atags in procfs"
2070 Should the atags used to boot the kernel be exported in an "atags"
2071 file in procfs. Useful with kexec.
2074 bool "Build kdump crash kernel (EXPERIMENTAL)"
2075 depends on EXPERIMENTAL
2077 Generate crash dump after being started by kexec. This should
2078 be normally only set in special crash dump kernels which are
2079 loaded in the main kernel with kexec-tools into a specially
2080 reserved region and then later executed after a crash by
2081 kdump/kexec. The crash dump kernel must be compiled to a
2082 memory address not used by the main kernel
2084 For more details see Documentation/kdump/kdump.txt
2086 config AUTO_ZRELADDR
2087 bool "Auto calculation of the decompressed kernel image address"
2088 depends on !ZBOOT_ROM && !ARCH_U300
2090 ZRELADDR is the physical address where the decompressed kernel
2091 image will be placed. If AUTO_ZRELADDR is selected, the address
2092 will be determined at run-time by masking the current IP with
2093 0xf8000000. This assumes the zImage being placed in the first 128MB
2094 from start of memory.
2098 menu "CPU Power Management"
2102 source "drivers/cpufreq/Kconfig"
2105 tristate "CPUfreq driver for i.MX CPUs"
2106 depends on ARCH_MXC && CPU_FREQ
2108 This enables the CPUfreq driver for i.MX CPUs.
2110 config CPU_FREQ_SA1100
2113 config CPU_FREQ_SA1110
2116 config CPU_FREQ_INTEGRATOR
2117 tristate "CPUfreq driver for ARM Integrator CPUs"
2118 depends on ARCH_INTEGRATOR && CPU_FREQ
2121 This enables the CPUfreq driver for ARM Integrator CPUs.
2123 For details, take a look at <file:Documentation/cpu-freq>.
2129 depends on CPU_FREQ && ARCH_PXA && PXA25x
2131 select CPU_FREQ_TABLE
2132 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2137 Internal configuration node for common cpufreq on Samsung SoC
2139 config CPU_FREQ_S3C24XX
2140 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2141 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2144 This enables the CPUfreq driver for the Samsung S3C24XX family
2147 For details, take a look at <file:Documentation/cpu-freq>.
2151 config CPU_FREQ_S3C24XX_PLL
2152 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2153 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2155 Compile in support for changing the PLL frequency from the
2156 S3C24XX series CPUfreq driver. The PLL takes time to settle
2157 after a frequency change, so by default it is not enabled.
2159 This also means that the PLL tables for the selected CPU(s) will
2160 be built which may increase the size of the kernel image.
2162 config CPU_FREQ_S3C24XX_DEBUG
2163 bool "Debug CPUfreq Samsung driver core"
2164 depends on CPU_FREQ_S3C24XX
2166 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2168 config CPU_FREQ_S3C24XX_IODEBUG
2169 bool "Debug CPUfreq Samsung driver IO timing"
2170 depends on CPU_FREQ_S3C24XX
2172 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2174 config CPU_FREQ_S3C24XX_DEBUGFS
2175 bool "Export debugfs for CPUFreq"
2176 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2178 Export status information via debugfs.
2182 source "drivers/cpuidle/Kconfig"
2186 menu "Floating point emulation"
2188 comment "At least one emulation must be selected"
2191 bool "NWFPE math emulation"
2192 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2194 Say Y to include the NWFPE floating point emulator in the kernel.
2195 This is necessary to run most binaries. Linux does not currently
2196 support floating point hardware so you need to say Y here even if
2197 your machine has an FPA or floating point co-processor podule.
2199 You may say N here if you are going to load the Acorn FPEmulator
2200 early in the bootup.
2203 bool "Support extended precision"
2204 depends on FPE_NWFPE
2206 Say Y to include 80-bit support in the kernel floating-point
2207 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2208 Note that gcc does not generate 80-bit operations by default,
2209 so in most cases this option only enlarges the size of the
2210 floating point emulator without any good reason.
2212 You almost surely want to say N here.
2215 bool "FastFPE math emulation (EXPERIMENTAL)"
2216 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2218 Say Y here to include the FAST floating point emulator in the kernel.
2219 This is an experimental much faster emulator which now also has full
2220 precision for the mantissa. It does not support any exceptions.
2221 It is very simple, and approximately 3-6 times faster than NWFPE.
2223 It should be sufficient for most programs. It may be not suitable
2224 for scientific calculations, but you have to check this for yourself.
2225 If you do not feel you need a faster FP emulation you should better
2229 bool "VFP-format floating point maths"
2230 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2232 Say Y to include VFP support code in the kernel. This is needed
2233 if your hardware includes a VFP unit.
2235 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2236 release notes and additional status information.
2238 Say N if your target does not have VFP hardware.
2246 bool "Advanced SIMD (NEON) Extension support"
2247 depends on VFPv3 && CPU_V7
2249 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2254 menu "Userspace binary formats"
2256 source "fs/Kconfig.binfmt"
2259 tristate "RISC OS personality"
2262 Say Y here to include the kernel code necessary if you want to run
2263 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2264 experimental; if this sounds frightening, say N and sleep in peace.
2265 You can also say M here to compile this support as a module (which
2266 will be called arthur).
2270 menu "Power management options"
2272 source "kernel/power/Kconfig"
2274 config ARCH_SUSPEND_POSSIBLE
2275 depends on !ARCH_S5PC100
2276 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2277 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2280 config ARM_CPU_SUSPEND
2285 source "net/Kconfig"
2287 source "drivers/Kconfig"
2291 source "arch/arm/Kconfig.debug"
2293 source "security/Kconfig"
2295 source "crypto/Kconfig"
2297 source "lib/Kconfig"