4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
59 select OLD_SIGSUSPEND3
62 The ARM series is a line of low-power-consumption RISC chip designs
63 licensed by ARM Ltd and targeted at embedded applications and
64 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
65 manufactured, but legacy ARM-based PC hardware remains popular in
66 Europe. There is an ARM Linux project with a web page at
67 <http://www.arm.linux.org.uk/>.
69 config ARM_HAS_SG_CHAIN
72 config NEED_SG_DMA_LENGTH
75 config ARM_DMA_USE_IOMMU
77 select ARM_HAS_SG_CHAIN
78 select NEED_SG_DMA_LENGTH
82 config ARM_DMA_IOMMU_ALIGNMENT
83 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
87 DMA mapping framework by default aligns all buffers to the smallest
88 PAGE_SIZE order which is greater than or equal to the requested buffer
89 size. This works well for buffers up to a few hundreds kilobytes, but
90 for larger buffers it just a waste of address space. Drivers which has
91 relatively small addressing window (like 64Mib) might run out of
92 virtual space with just a few allocations.
94 With this parameter you can specify the maximum PAGE_SIZE order for
95 DMA IOMMU buffers. Larger buffers will be aligned only to this
96 specified order. The order is expressed as a power of two multiplied
104 config MIGHT_HAVE_PCI
107 config SYS_SUPPORTS_APM_EMULATION
115 select GENERIC_ALLOCATOR
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
141 config STACKTRACE_SUPPORT
145 config HAVE_LATENCYTOP_SUPPORT
150 config LOCKDEP_SUPPORT
154 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_GENERIC_SPINLOCK
162 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_CPUFREQ
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
178 config GENERIC_HWEIGHT
182 config GENERIC_CALIBRATE_DELAY
186 config ARCH_MAY_HAVE_PC_FDC
192 config NEED_DMA_MAP_STATE
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
198 config GENERIC_ISA_DMA
204 config NEED_RET_TO_USER
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
216 The base address of exception vectors.
218 config ARM_PATCH_PHYS_VIRT
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
221 depends on !XIP_KERNEL && MMU
222 depends on !ARCH_REALVIEW || !SPARSEMEM
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
228 This can only be used with non-XIP MMU kernels where the base
229 of physical memory is at a 16MB boundary.
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
235 config NEED_MACH_GPIO_H
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
242 config NEED_MACH_IO_H
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
275 bool "MMU-based Paged Memory Management Support"
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
293 select ARM_PATCH_PHYS_VIRT
296 select MULTI_IRQ_HANDLER
300 config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
302 select ARCH_HAS_CPUFREQ
305 select COMMON_CLK_VERSATILE
306 select GENERIC_CLOCKEVENTS
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
311 select PLAT_VERSATILE
313 select VERSATILE_FPGA_IRQ
315 Support for ARM's Integrator platform.
318 bool "ARM Ltd. RealView family"
319 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_TIMER_SP804
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
325 select GPIO_PL061 if GPIOLIB
327 select NEED_MACH_MEMORY_H
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
331 This enables support for ARM Ltd RealView boards.
333 config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 select ARM_TIMER_SP804
340 select GENERIC_CLOCKEVENTS
341 select HAVE_MACH_CLKDEV
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
345 select PLAT_VERSATILE_CLOCK
346 select VERSATILE_FPGA_IRQ
348 This enables support for ARM Ltd Versatile board.
352 select ARCH_REQUIRE_GPIOLIB
356 select NEED_MACH_GPIO_H
357 select NEED_MACH_IO_H if PCCARD
359 select PINCTRL_AT91 if USE_OF
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
365 bool "Broadcom BCM2835 family"
366 select ARCH_REQUIRE_GPIOLIB
368 select ARM_ERRATA_411920
369 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
375 select MULTI_IRQ_HANDLER
377 select PINCTRL_BCM2835
381 This enables support for the Broadcom BCM2835 SoC. This SoC is
382 use in the Raspberry Pi, and Roku 2 devices.
385 bool "Cavium Networks CNS3XXX family"
388 select GENERIC_CLOCKEVENTS
389 select MIGHT_HAVE_CACHE_L2X0
390 select MIGHT_HAVE_PCI
391 select PCI_DOMAINS if PCI
393 Support for Cavium Networks CNS3XXX platform.
396 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
397 select ARCH_REQUIRE_GPIOLIB
402 select GENERIC_CLOCKEVENTS
403 select MULTI_IRQ_HANDLER
404 select NEED_MACH_MEMORY_H
407 Support for Cirrus Logic 711x/721x/731x based boards.
410 bool "Cortina Systems Gemini"
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_USES_GETTIMEOFFSET
415 Support for the Cortina Systems Gemini family SoCs
419 select ARCH_REQUIRE_GPIOLIB
422 select GENERIC_CLOCKEVENTS
423 select GENERIC_IRQ_CHIP
424 select MIGHT_HAVE_CACHE_L2X0
430 Support for CSR SiRFprimaII/Marco/Polo platforms
434 select ARCH_USES_GETTIMEOFFSET
437 select NEED_MACH_IO_H
438 select NEED_MACH_MEMORY_H
441 This is an evaluation board for the StrongARM processor available
442 from Digital. It has limited hardware on-board, including an
443 Ethernet interface, two PCMCIA sockets, two serial ports and a
448 select ARCH_HAS_HOLES_MEMORYMODEL
449 select ARCH_REQUIRE_GPIOLIB
450 select ARCH_USES_GETTIMEOFFSET
455 select NEED_MACH_MEMORY_H
457 This enables support for the Cirrus EP93xx series of CPUs.
459 config ARCH_FOOTBRIDGE
463 select GENERIC_CLOCKEVENTS
465 select NEED_MACH_IO_H if !MMU
466 select NEED_MACH_MEMORY_H
468 Support for systems based on the DC21285 companion chip
469 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
472 bool "Freescale MXS-based"
473 select ARCH_REQUIRE_GPIOLIB
477 select GENERIC_CLOCKEVENTS
478 select HAVE_CLK_PREPARE
479 select MULTI_IRQ_HANDLER
484 Support for Freescale MXS-based family of processors
487 bool "Hilscher NetX based"
491 select GENERIC_CLOCKEVENTS
493 This enables support for systems based on the Hilscher NetX Soc
496 bool "Hynix HMS720x-based"
497 select ARCH_USES_GETTIMEOFFSET
501 This enables support for systems based on the Hynix HMS720x
506 select ARCH_SUPPORTS_MSI
508 select NEED_MACH_MEMORY_H
509 select NEED_RET_TO_USER
514 Support for Intel's IOP13XX (XScale) family of processors.
519 select ARCH_REQUIRE_GPIOLIB
521 select NEED_MACH_GPIO_H
522 select NEED_RET_TO_USER
526 Support for Intel's 80219 and IOP32X (XScale) family of
532 select ARCH_REQUIRE_GPIOLIB
534 select NEED_MACH_GPIO_H
535 select NEED_RET_TO_USER
539 Support for Intel's IOP33X (XScale) family of processors.
544 select ARCH_HAS_DMA_SET_COHERENT_MASK
545 select ARCH_REQUIRE_GPIOLIB
548 select DMABOUNCE if PCI
549 select GENERIC_CLOCKEVENTS
550 select MIGHT_HAVE_PCI
551 select NEED_MACH_IO_H
553 Support for Intel's IXP4XX (XScale) family of processors.
557 select ARCH_REQUIRE_GPIOLIB
558 select COMMON_CLK_DOVE
560 select GENERIC_CLOCKEVENTS
561 select MIGHT_HAVE_PCI
564 select PLAT_ORION_LEGACY
565 select USB_ARCH_HAS_EHCI
567 Support for the Marvell Dove SoC 88AP510
570 bool "Marvell Kirkwood"
571 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
577 select PINCTRL_KIRKWOOD
578 select PLAT_ORION_LEGACY
580 Support for the following Marvell Kirkwood series SoCs:
581 88F6180, 88F6192 and 88F6281.
584 bool "Marvell MV78xx0"
585 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
589 select PLAT_ORION_LEGACY
591 Support for the following Marvell MV78xx0 series SoCs:
597 select ARCH_REQUIRE_GPIOLIB
599 select GENERIC_CLOCKEVENTS
601 select PLAT_ORION_LEGACY
603 Support for the following Marvell Orion 5x series SoCs:
604 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
605 Orion-2 (5281), Orion-1-90 (6183).
608 bool "Marvell PXA168/910/MMP2"
610 select ARCH_REQUIRE_GPIOLIB
612 select GENERIC_ALLOCATOR
613 select GENERIC_CLOCKEVENTS
616 select NEED_MACH_GPIO_H
621 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
624 bool "Micrel/Kendin KS8695"
625 select ARCH_REQUIRE_GPIOLIB
628 select GENERIC_CLOCKEVENTS
629 select NEED_MACH_MEMORY_H
631 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
632 System-on-Chip devices.
635 bool "Nuvoton W90X900 CPU"
636 select ARCH_REQUIRE_GPIOLIB
640 select GENERIC_CLOCKEVENTS
642 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
643 At present, the w90x900 has been renamed nuc900, regarding
644 the ARM series product line, you can login the following
645 link address to know more.
647 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
648 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
652 select ARCH_REQUIRE_GPIOLIB
657 select GENERIC_CLOCKEVENTS
660 select USB_ARCH_HAS_OHCI
663 Support for the NXP LPC32XX family of processors
667 select ARCH_HAS_CPUFREQ
668 select ARCH_REQUIRE_GPIOLIB
673 select GENERIC_CLOCKEVENTS
676 select MIGHT_HAVE_CACHE_L2X0
680 This enables support for NVIDIA Tegra based systems (Tegra APX,
681 Tegra 6xx and Tegra 2 series).
684 bool "PXA2xx/PXA3xx-based"
686 select ARCH_HAS_CPUFREQ
688 select ARCH_REQUIRE_GPIOLIB
689 select ARM_CPU_SUSPEND if PM
693 select GENERIC_CLOCKEVENTS
696 select MULTI_IRQ_HANDLER
697 select NEED_MACH_GPIO_H
701 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
705 select ARCH_REQUIRE_GPIOLIB
707 select GENERIC_CLOCKEVENTS
710 Support for Qualcomm MSM/QSD based systems. This runs on the
711 apps processor of the MSM/QSD and depends on a shared memory
712 interface to the modem processor which runs the baseband
713 stack and controls some vital subsystems
714 (clock and power control, etc).
717 bool "Renesas SH-Mobile / R-Mobile"
719 select GENERIC_CLOCKEVENTS
721 select HAVE_MACH_CLKDEV
723 select MIGHT_HAVE_CACHE_L2X0
724 select MULTI_IRQ_HANDLER
725 select NEED_MACH_MEMORY_H
728 select PM_GENERIC_DOMAINS if PM
731 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
736 select ARCH_MAY_HAVE_PC_FDC
737 select ARCH_SPARSEMEM_ENABLE
738 select ARCH_USES_GETTIMEOFFSET
741 select HAVE_PATA_PLATFORM
743 select NEED_MACH_IO_H
744 select NEED_MACH_MEMORY_H
747 On the Acorn Risc-PC, Linux can support the internal IDE disk and
748 CD-ROM interface, serial and parallel port, and the floppy drive.
752 select ARCH_HAS_CPUFREQ
754 select ARCH_REQUIRE_GPIOLIB
755 select ARCH_SPARSEMEM_ENABLE
760 select GENERIC_CLOCKEVENTS
763 select NEED_MACH_GPIO_H
764 select NEED_MACH_MEMORY_H
767 Support for StrongARM 11x0 based boards.
770 bool "Samsung S3C24XX SoCs"
771 select ARCH_HAS_CPUFREQ
772 select ARCH_USES_GETTIMEOFFSET
775 select HAVE_S3C2410_I2C if I2C
776 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 select HAVE_S3C_RTC if RTC_CLASS
778 select NEED_MACH_GPIO_H
779 select NEED_MACH_IO_H
781 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
782 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
783 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
784 Samsung SMDK2410 development board (and derivatives).
787 bool "Samsung S3C64XX"
788 select ARCH_HAS_CPUFREQ
789 select ARCH_REQUIRE_GPIOLIB
790 select ARCH_USES_GETTIMEOFFSET
795 select HAVE_S3C2410_I2C if I2C
796 select HAVE_S3C2410_WATCHDOG if WATCHDOG
798 select NEED_MACH_GPIO_H
802 select S3C_GPIO_TRACK
803 select SAMSUNG_CLKSRC
804 select SAMSUNG_GPIOLIB_4BIT
805 select SAMSUNG_IRQ_VIC_TIMER
806 select USB_ARCH_HAS_OHCI
808 Samsung S3C64XX series based systems
811 bool "Samsung S5P6440 S5P6450"
815 select GENERIC_CLOCKEVENTS
817 select HAVE_S3C2410_I2C if I2C
818 select HAVE_S3C2410_WATCHDOG if WATCHDOG
819 select HAVE_S3C_RTC if RTC_CLASS
820 select NEED_MACH_GPIO_H
822 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
826 bool "Samsung S5PC100"
827 select ARCH_USES_GETTIMEOFFSET
831 select HAVE_S3C2410_I2C if I2C
832 select HAVE_S3C2410_WATCHDOG if WATCHDOG
833 select HAVE_S3C_RTC if RTC_CLASS
834 select NEED_MACH_GPIO_H
836 Samsung S5PC100 series based systems
839 bool "Samsung S5PV210/S5PC110"
840 select ARCH_HAS_CPUFREQ
841 select ARCH_HAS_HOLES_MEMORYMODEL
842 select ARCH_SPARSEMEM_ENABLE
846 select GENERIC_CLOCKEVENTS
848 select HAVE_S3C2410_I2C if I2C
849 select HAVE_S3C2410_WATCHDOG if WATCHDOG
850 select HAVE_S3C_RTC if RTC_CLASS
851 select NEED_MACH_GPIO_H
852 select NEED_MACH_MEMORY_H
854 Samsung S5PV210/S5PC110 series based systems
857 bool "Samsung EXYNOS"
858 select ARCH_HAS_CPUFREQ
859 select ARCH_HAS_HOLES_MEMORYMODEL
860 select ARCH_SPARSEMEM_ENABLE
863 select GENERIC_CLOCKEVENTS
865 select HAVE_S3C2410_I2C if I2C
866 select HAVE_S3C2410_WATCHDOG if WATCHDOG
867 select HAVE_S3C_RTC if RTC_CLASS
868 select NEED_MACH_GPIO_H
869 select NEED_MACH_MEMORY_H
871 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
875 select ARCH_USES_GETTIMEOFFSET
879 select NEED_MACH_MEMORY_H
883 Support for the StrongARM based Digital DNARD machine, also known
884 as "Shark" (<http://www.shark-linux.de/shark.html>).
887 bool "ST-Ericsson U300 Series"
889 select ARCH_REQUIRE_GPIOLIB
891 select ARM_PATCH_PHYS_VIRT
897 select GENERIC_CLOCKEVENTS
901 Support for ST-Ericsson U300 series mobile platforms.
904 bool "ST-Ericsson U8500 Series"
906 select ARCH_HAS_CPUFREQ
907 select ARCH_REQUIRE_GPIOLIB
911 select GENERIC_CLOCKEVENTS
913 select MIGHT_HAVE_CACHE_L2X0
916 Support for ST-Ericsson's Ux500 architecture
919 bool "STMicroelectronics Nomadik"
920 select ARCH_REQUIRE_GPIOLIB
923 select CLKSRC_NOMADIK_MTU
926 select GENERIC_CLOCKEVENTS
927 select MIGHT_HAVE_CACHE_L2X0
930 select PINCTRL_STN8815
933 Support for the Nomadik platform by ST-Ericsson
937 select ARCH_HAS_CPUFREQ
938 select ARCH_REQUIRE_GPIOLIB
943 select GENERIC_CLOCKEVENTS
946 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
950 select ARCH_HAS_HOLES_MEMORYMODEL
951 select ARCH_REQUIRE_GPIOLIB
953 select GENERIC_ALLOCATOR
954 select GENERIC_CLOCKEVENTS
955 select GENERIC_IRQ_CHIP
957 select NEED_MACH_GPIO_H
961 Support for TI's DaVinci platform.
966 select ARCH_HAS_CPUFREQ
967 select ARCH_HAS_HOLES_MEMORYMODEL
969 select ARCH_REQUIRE_GPIOLIB
972 select GENERIC_CLOCKEVENTS
973 select GENERIC_IRQ_CHIP
977 select NEED_MACH_IO_H if PCCARD
978 select NEED_MACH_MEMORY_H
980 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
984 menu "Multiple platform selection"
985 depends on ARCH_MULTIPLATFORM
987 comment "CPU Core family selection"
990 bool "ARMv4 based platforms (FA526, StrongARM)"
991 depends on !ARCH_MULTI_V6_V7
992 select ARCH_MULTI_V4_V5
994 config ARCH_MULTI_V4T
995 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
996 depends on !ARCH_MULTI_V6_V7
997 select ARCH_MULTI_V4_V5
1000 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1001 depends on !ARCH_MULTI_V6_V7
1002 select ARCH_MULTI_V4_V5
1004 config ARCH_MULTI_V4_V5
1007 config ARCH_MULTI_V6
1008 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
1009 select ARCH_MULTI_V6_V7
1012 config ARCH_MULTI_V7
1013 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1015 select ARCH_MULTI_V6_V7
1016 select ARCH_VEXPRESS
1019 config ARCH_MULTI_V6_V7
1022 config ARCH_MULTI_CPU_AUTO
1023 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1024 select ARCH_MULTI_V5
1029 # This is sorted alphabetically by mach-* pathname. However, plat-*
1030 # Kconfigs may be included either alphabetically (according to the
1031 # plat- suffix) or along side the corresponding mach-* source.
1033 source "arch/arm/mach-mvebu/Kconfig"
1035 source "arch/arm/mach-at91/Kconfig"
1037 source "arch/arm/mach-bcm/Kconfig"
1039 source "arch/arm/mach-clps711x/Kconfig"
1041 source "arch/arm/mach-cns3xxx/Kconfig"
1043 source "arch/arm/mach-davinci/Kconfig"
1045 source "arch/arm/mach-dove/Kconfig"
1047 source "arch/arm/mach-ep93xx/Kconfig"
1049 source "arch/arm/mach-footbridge/Kconfig"
1051 source "arch/arm/mach-gemini/Kconfig"
1053 source "arch/arm/mach-h720x/Kconfig"
1055 source "arch/arm/mach-highbank/Kconfig"
1057 source "arch/arm/mach-integrator/Kconfig"
1059 source "arch/arm/mach-iop32x/Kconfig"
1061 source "arch/arm/mach-iop33x/Kconfig"
1063 source "arch/arm/mach-iop13xx/Kconfig"
1065 source "arch/arm/mach-ixp4xx/Kconfig"
1067 source "arch/arm/mach-kirkwood/Kconfig"
1069 source "arch/arm/mach-ks8695/Kconfig"
1071 source "arch/arm/mach-msm/Kconfig"
1073 source "arch/arm/mach-mv78xx0/Kconfig"
1075 source "arch/arm/mach-imx/Kconfig"
1077 source "arch/arm/mach-mxs/Kconfig"
1079 source "arch/arm/mach-netx/Kconfig"
1081 source "arch/arm/mach-nomadik/Kconfig"
1083 source "arch/arm/plat-omap/Kconfig"
1085 source "arch/arm/mach-omap1/Kconfig"
1087 source "arch/arm/mach-omap2/Kconfig"
1089 source "arch/arm/mach-orion5x/Kconfig"
1091 source "arch/arm/mach-picoxcell/Kconfig"
1093 source "arch/arm/mach-pxa/Kconfig"
1094 source "arch/arm/plat-pxa/Kconfig"
1096 source "arch/arm/mach-mmp/Kconfig"
1098 source "arch/arm/mach-realview/Kconfig"
1100 source "arch/arm/mach-sa1100/Kconfig"
1102 source "arch/arm/plat-samsung/Kconfig"
1104 source "arch/arm/mach-socfpga/Kconfig"
1106 source "arch/arm/plat-spear/Kconfig"
1108 source "arch/arm/mach-s3c24xx/Kconfig"
1111 source "arch/arm/mach-s3c64xx/Kconfig"
1114 source "arch/arm/mach-s5p64x0/Kconfig"
1116 source "arch/arm/mach-s5pc100/Kconfig"
1118 source "arch/arm/mach-s5pv210/Kconfig"
1120 source "arch/arm/mach-exynos/Kconfig"
1122 source "arch/arm/mach-shmobile/Kconfig"
1124 source "arch/arm/mach-sunxi/Kconfig"
1126 source "arch/arm/mach-prima2/Kconfig"
1128 source "arch/arm/mach-tegra/Kconfig"
1130 source "arch/arm/mach-u300/Kconfig"
1132 source "arch/arm/mach-ux500/Kconfig"
1134 source "arch/arm/mach-versatile/Kconfig"
1136 source "arch/arm/mach-vexpress/Kconfig"
1137 source "arch/arm/plat-versatile/Kconfig"
1139 source "arch/arm/mach-virt/Kconfig"
1141 source "arch/arm/mach-vt8500/Kconfig"
1143 source "arch/arm/mach-w90x900/Kconfig"
1145 source "arch/arm/mach-zynq/Kconfig"
1147 # Definitions to make life easier
1153 select GENERIC_CLOCKEVENTS
1159 select GENERIC_IRQ_CHIP
1162 config PLAT_ORION_LEGACY
1169 config PLAT_VERSATILE
1172 config ARM_TIMER_SP804
1175 select HAVE_SCHED_CLOCK
1177 source arch/arm/mm/Kconfig
1181 default 16 if ARCH_EP93XX
1185 bool "Enable iWMMXt support"
1186 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1187 default y if PXA27x || PXA3xx || ARCH_MMP
1189 Enable support for iWMMXt context switching at run time if
1190 running on a CPU that supports it.
1194 depends on CPU_XSCALE
1197 config MULTI_IRQ_HANDLER
1200 Allow each machine to specify it's own IRQ handler at run time.
1203 source "arch/arm/Kconfig-nommu"
1206 config ARM_ERRATA_326103
1207 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1210 Executing a SWP instruction to read-only memory does not set bit 11
1211 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1212 treat the access as a read, preventing a COW from occurring and
1213 causing the faulting task to livelock.
1215 config ARM_ERRATA_411920
1216 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1217 depends on CPU_V6 || CPU_V6K
1219 Invalidation of the Instruction Cache operation can
1220 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1221 It does not affect the MPCore. This option enables the ARM Ltd.
1222 recommended workaround.
1224 config ARM_ERRATA_430973
1225 bool "ARM errata: Stale prediction on replaced interworking branch"
1228 This option enables the workaround for the 430973 Cortex-A8
1229 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1230 interworking branch is replaced with another code sequence at the
1231 same virtual address, whether due to self-modifying code or virtual
1232 to physical address re-mapping, Cortex-A8 does not recover from the
1233 stale interworking branch prediction. This results in Cortex-A8
1234 executing the new code sequence in the incorrect ARM or Thumb state.
1235 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1236 and also flushes the branch target cache at every context switch.
1237 Note that setting specific bits in the ACTLR register may not be
1238 available in non-secure mode.
1240 config ARM_ERRATA_458693
1241 bool "ARM errata: Processor deadlock when a false hazard is created"
1243 depends on !ARCH_MULTIPLATFORM
1245 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1246 erratum. For very specific sequences of memory operations, it is
1247 possible for a hazard condition intended for a cache line to instead
1248 be incorrectly associated with a different cache line. This false
1249 hazard might then cause a processor deadlock. The workaround enables
1250 the L1 caching of the NEON accesses and disables the PLD instruction
1251 in the ACTLR register. Note that setting specific bits in the ACTLR
1252 register may not be available in non-secure mode.
1254 config ARM_ERRATA_460075
1255 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1257 depends on !ARCH_MULTIPLATFORM
1259 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1260 erratum. Any asynchronous access to the L2 cache may encounter a
1261 situation in which recent store transactions to the L2 cache are lost
1262 and overwritten with stale memory contents from external memory. The
1263 workaround disables the write-allocate mode for the L2 cache via the
1264 ACTLR register. Note that setting specific bits in the ACTLR register
1265 may not be available in non-secure mode.
1267 config ARM_ERRATA_742230
1268 bool "ARM errata: DMB operation may be faulty"
1269 depends on CPU_V7 && SMP
1270 depends on !ARCH_MULTIPLATFORM
1272 This option enables the workaround for the 742230 Cortex-A9
1273 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1274 between two write operations may not ensure the correct visibility
1275 ordering of the two writes. This workaround sets a specific bit in
1276 the diagnostic register of the Cortex-A9 which causes the DMB
1277 instruction to behave as a DSB, ensuring the correct behaviour of
1280 config ARM_ERRATA_742231
1281 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1282 depends on CPU_V7 && SMP
1283 depends on !ARCH_MULTIPLATFORM
1285 This option enables the workaround for the 742231 Cortex-A9
1286 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1287 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1288 accessing some data located in the same cache line, may get corrupted
1289 data due to bad handling of the address hazard when the line gets
1290 replaced from one of the CPUs at the same time as another CPU is
1291 accessing it. This workaround sets specific bits in the diagnostic
1292 register of the Cortex-A9 which reduces the linefill issuing
1293 capabilities of the processor.
1295 config PL310_ERRATA_588369
1296 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1297 depends on CACHE_L2X0
1299 The PL310 L2 cache controller implements three types of Clean &
1300 Invalidate maintenance operations: by Physical Address
1301 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1302 They are architecturally defined to behave as the execution of a
1303 clean operation followed immediately by an invalidate operation,
1304 both performing to the same memory location. This functionality
1305 is not correctly implemented in PL310 as clean lines are not
1306 invalidated as a result of these operations.
1308 config ARM_ERRATA_720789
1309 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1312 This option enables the workaround for the 720789 Cortex-A9 (prior to
1313 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1314 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1315 As a consequence of this erratum, some TLB entries which should be
1316 invalidated are not, resulting in an incoherency in the system page
1317 tables. The workaround changes the TLB flushing routines to invalidate
1318 entries regardless of the ASID.
1320 config PL310_ERRATA_727915
1321 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1322 depends on CACHE_L2X0
1324 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1325 operation (offset 0x7FC). This operation runs in background so that
1326 PL310 can handle normal accesses while it is in progress. Under very
1327 rare circumstances, due to this erratum, write data can be lost when
1328 PL310 treats a cacheable write transaction during a Clean &
1329 Invalidate by Way operation.
1331 config ARM_ERRATA_743622
1332 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1334 depends on !ARCH_MULTIPLATFORM
1336 This option enables the workaround for the 743622 Cortex-A9
1337 (r2p*) erratum. Under very rare conditions, a faulty
1338 optimisation in the Cortex-A9 Store Buffer may lead to data
1339 corruption. This workaround sets a specific bit in the diagnostic
1340 register of the Cortex-A9 which disables the Store Buffer
1341 optimisation, preventing the defect from occurring. This has no
1342 visible impact on the overall performance or power consumption of the
1345 config ARM_ERRATA_751472
1346 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1348 depends on !ARCH_MULTIPLATFORM
1350 This option enables the workaround for the 751472 Cortex-A9 (prior
1351 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1352 completion of a following broadcasted operation if the second
1353 operation is received by a CPU before the ICIALLUIS has completed,
1354 potentially leading to corrupted entries in the cache or TLB.
1356 config PL310_ERRATA_753970
1357 bool "PL310 errata: cache sync operation may be faulty"
1358 depends on CACHE_PL310
1360 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1362 Under some condition the effect of cache sync operation on
1363 the store buffer still remains when the operation completes.
1364 This means that the store buffer is always asked to drain and
1365 this prevents it from merging any further writes. The workaround
1366 is to replace the normal offset of cache sync operation (0x730)
1367 by another offset targeting an unmapped PL310 register 0x740.
1368 This has the same effect as the cache sync operation: store buffer
1369 drain and waiting for all buffers empty.
1371 config ARM_ERRATA_754322
1372 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1375 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1376 r3p*) erratum. A speculative memory access may cause a page table walk
1377 which starts prior to an ASID switch but completes afterwards. This
1378 can populate the micro-TLB with a stale entry which may be hit with
1379 the new ASID. This workaround places two dsb instructions in the mm
1380 switching code so that no page table walks can cross the ASID switch.
1382 config ARM_ERRATA_754327
1383 bool "ARM errata: no automatic Store Buffer drain"
1384 depends on CPU_V7 && SMP
1386 This option enables the workaround for the 754327 Cortex-A9 (prior to
1387 r2p0) erratum. The Store Buffer does not have any automatic draining
1388 mechanism and therefore a livelock may occur if an external agent
1389 continuously polls a memory location waiting to observe an update.
1390 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1391 written polling loops from denying visibility of updates to memory.
1393 config ARM_ERRATA_364296
1394 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1395 depends on CPU_V6 && !SMP
1397 This options enables the workaround for the 364296 ARM1136
1398 r0p2 erratum (possible cache data corruption with
1399 hit-under-miss enabled). It sets the undocumented bit 31 in
1400 the auxiliary control register and the FI bit in the control
1401 register, thus disabling hit-under-miss without putting the
1402 processor into full low interrupt latency mode. ARM11MPCore
1405 config ARM_ERRATA_764369
1406 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1407 depends on CPU_V7 && SMP
1409 This option enables the workaround for erratum 764369
1410 affecting Cortex-A9 MPCore with two or more processors (all
1411 current revisions). Under certain timing circumstances, a data
1412 cache line maintenance operation by MVA targeting an Inner
1413 Shareable memory region may fail to proceed up to either the
1414 Point of Coherency or to the Point of Unification of the
1415 system. This workaround adds a DSB instruction before the
1416 relevant cache maintenance functions and sets a specific bit
1417 in the diagnostic control register of the SCU.
1419 config PL310_ERRATA_769419
1420 bool "PL310 errata: no automatic Store Buffer drain"
1421 depends on CACHE_L2X0
1423 On revisions of the PL310 prior to r3p2, the Store Buffer does
1424 not automatically drain. This can cause normal, non-cacheable
1425 writes to be retained when the memory system is idle, leading
1426 to suboptimal I/O performance for drivers using coherent DMA.
1427 This option adds a write barrier to the cpu_idle loop so that,
1428 on systems with an outer cache, the store buffer is drained
1431 config ARM_ERRATA_775420
1432 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1435 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1436 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1437 operation aborts with MMU exception, it might cause the processor
1438 to deadlock. This workaround puts DSB before executing ISB if
1439 an abort may occur on cache maintenance.
1443 source "arch/arm/common/Kconfig"
1453 Find out whether you have ISA slots on your motherboard. ISA is the
1454 name of a bus system, i.e. the way the CPU talks to the other stuff
1455 inside your box. Other bus systems are PCI, EISA, MicroChannel
1456 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1457 newer boards don't support it. If you have ISA, say Y, otherwise N.
1459 # Select ISA DMA controller support
1464 config ARCH_NO_VIRT_TO_BUS
1466 depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
1468 # Select ISA DMA interface
1473 bool "PCI support" if MIGHT_HAVE_PCI
1475 Find out whether you have a PCI motherboard. PCI is the name of a
1476 bus system, i.e. the way the CPU talks to the other stuff inside
1477 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1478 VESA. If you have PCI, say Y, otherwise N.
1484 config PCI_NANOENGINE
1485 bool "BSE nanoEngine PCI support"
1486 depends on SA1100_NANOENGINE
1488 Enable PCI on the BSE nanoEngine board.
1493 # Select the host bridge type
1494 config PCI_HOST_VIA82C505
1496 depends on PCI && ARCH_SHARK
1499 config PCI_HOST_ITE8152
1501 depends on PCI && MACH_ARMCORE
1505 source "drivers/pci/Kconfig"
1507 source "drivers/pcmcia/Kconfig"
1511 menu "Kernel Features"
1516 This option should be selected by machines which have an SMP-
1519 The only effect of this option is to make the SMP-related
1520 options available to the user for configuration.
1523 bool "Symmetric Multi-Processing"
1524 depends on CPU_V6K || CPU_V7
1525 depends on GENERIC_CLOCKEVENTS
1528 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1529 select USE_GENERIC_SMP_HELPERS
1531 This enables support for systems with more than one CPU. If you have
1532 a system with only one CPU, like most personal computers, say N. If
1533 you have a system with more than one CPU, say Y.
1535 If you say N here, the kernel will run on single and multiprocessor
1536 machines, but will use only one CPU of a multiprocessor machine. If
1537 you say Y here, the kernel will run on many, but not all, single
1538 processor machines. On a single processor machine, the kernel will
1539 run faster if you say N here.
1541 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1542 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1543 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1545 If you don't know what to do here, say N.
1548 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1549 depends on SMP && !XIP_KERNEL
1552 SMP kernels contain instructions which fail on non-SMP processors.
1553 Enabling this option allows the kernel to modify itself to make
1554 these instructions safe. Disabling it allows about 1K of space
1557 If you don't know what to do here, say Y.
1559 config ARM_CPU_TOPOLOGY
1560 bool "Support cpu topology definition"
1561 depends on SMP && CPU_V7
1564 Support ARM cpu topology definition. The MPIDR register defines
1565 affinity between processors which is then used to describe the cpu
1566 topology of an ARM System.
1569 bool "Multi-core scheduler support"
1570 depends on ARM_CPU_TOPOLOGY
1572 Multi-core scheduler support improves the CPU scheduler's decision
1573 making when dealing with multi-core CPU chips at a cost of slightly
1574 increased overhead in some places. If unsure say N here.
1577 bool "SMT scheduler support"
1578 depends on ARM_CPU_TOPOLOGY
1580 Improves the CPU scheduler's decision making when dealing with
1581 MultiThreading at a cost of slightly increased overhead in some
1582 places. If unsure say N here.
1587 This option enables support for the ARM system coherency unit
1589 config HAVE_ARM_ARCH_TIMER
1590 bool "Architected timer support"
1592 select ARM_ARCH_TIMER
1594 This option enables support for the ARM architected timer
1600 This options enables support for the ARM timer and watchdog unit
1603 prompt "Memory split"
1606 Select the desired split between kernel and user memory.
1608 If you are not absolutely sure what you are doing, leave this
1612 bool "3G/1G user/kernel split"
1614 bool "2G/2G user/kernel split"
1616 bool "1G/3G user/kernel split"
1621 default 0x40000000 if VMSPLIT_1G
1622 default 0x80000000 if VMSPLIT_2G
1626 int "Maximum number of CPUs (2-32)"
1632 bool "Support for hot-pluggable CPUs"
1633 depends on SMP && HOTPLUG
1635 Say Y here to experiment with turning CPUs off and on. CPUs
1636 can be controlled through /sys/devices/system/cpu.
1639 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1642 Say Y here if you want Linux to communicate with system firmware
1643 implementing the PSCI specification for CPU-centric power
1644 management operations described in ARM document number ARM DEN
1645 0022A ("Power State Coordination Interface System Software on
1649 bool "Use local timer interrupts"
1652 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1654 Enable support for local timers on SMP platforms, rather then the
1655 legacy IPI broadcast method. Local timers allows the system
1656 accounting to be spread across the timer interval, preventing a
1657 "thundering herd" at every timer tick.
1661 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1662 default 355 if ARCH_U8500
1663 default 264 if MACH_H4700
1664 default 512 if SOC_OMAP5
1665 default 288 if ARCH_VT8500 || ARCH_SUNXI
1668 Maximum number of GPIOs in the system.
1670 If unsure, leave the default value.
1672 source kernel/Kconfig.preempt
1676 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1677 ARCH_S5PV210 || ARCH_EXYNOS4
1678 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1679 default AT91_TIMER_HZ if ARCH_AT91
1680 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1684 def_bool HIGH_RES_TIMERS
1686 config THUMB2_KERNEL
1687 bool "Compile the kernel in Thumb-2 mode"
1688 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1690 select ARM_ASM_UNIFIED
1693 By enabling this option, the kernel will be compiled in
1694 Thumb-2 mode. A compiler/assembler that understand the unified
1695 ARM-Thumb syntax is needed.
1699 config THUMB2_AVOID_R_ARM_THM_JUMP11
1700 bool "Work around buggy Thumb-2 short branch relocations in gas"
1701 depends on THUMB2_KERNEL && MODULES
1704 Various binutils versions can resolve Thumb-2 branches to
1705 locally-defined, preemptible global symbols as short-range "b.n"
1706 branch instructions.
1708 This is a problem, because there's no guarantee the final
1709 destination of the symbol, or any candidate locations for a
1710 trampoline, are within range of the branch. For this reason, the
1711 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1712 relocation in modules at all, and it makes little sense to add
1715 The symptom is that the kernel fails with an "unsupported
1716 relocation" error when loading some modules.
1718 Until fixed tools are available, passing
1719 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1720 code which hits this problem, at the cost of a bit of extra runtime
1721 stack usage in some cases.
1723 The problem is described in more detail at:
1724 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1726 Only Thumb-2 kernels are affected.
1728 Unless you are sure your tools don't have this problem, say Y.
1730 config ARM_ASM_UNIFIED
1734 bool "Use the ARM EABI to compile the kernel"
1736 This option allows for the kernel to be compiled using the latest
1737 ARM ABI (aka EABI). This is only useful if you are using a user
1738 space environment that is also compiled with EABI.
1740 Since there are major incompatibilities between the legacy ABI and
1741 EABI, especially with regard to structure member alignment, this
1742 option also changes the kernel syscall calling convention to
1743 disambiguate both ABIs and allow for backward compatibility support
1744 (selected with CONFIG_OABI_COMPAT).
1746 To use this you need GCC version 4.0.0 or later.
1749 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1750 depends on AEABI && !THUMB2_KERNEL
1753 This option preserves the old syscall interface along with the
1754 new (ARM EABI) one. It also provides a compatibility layer to
1755 intercept syscalls that have structure arguments which layout
1756 in memory differs between the legacy ABI and the new ARM EABI
1757 (only for non "thumb" binaries). This option adds a tiny
1758 overhead to all syscalls and produces a slightly larger kernel.
1759 If you know you'll be using only pure EABI user space then you
1760 can say N here. If this option is not selected and you attempt
1761 to execute a legacy ABI binary then the result will be
1762 UNPREDICTABLE (in fact it can be predicted that it won't work
1763 at all). If in doubt say Y.
1765 config ARCH_HAS_HOLES_MEMORYMODEL
1768 config ARCH_SPARSEMEM_ENABLE
1771 config ARCH_SPARSEMEM_DEFAULT
1772 def_bool ARCH_SPARSEMEM_ENABLE
1774 config ARCH_SELECT_MEMORY_MODEL
1775 def_bool ARCH_SPARSEMEM_ENABLE
1777 config HAVE_ARCH_PFN_VALID
1778 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1781 bool "High Memory Support"
1784 The address space of ARM processors is only 4 Gigabytes large
1785 and it has to accommodate user address space, kernel address
1786 space as well as some memory mapped IO. That means that, if you
1787 have a large amount of physical memory and/or IO, not all of the
1788 memory can be "permanently mapped" by the kernel. The physical
1789 memory that is not permanently mapped is called "high memory".
1791 Depending on the selected kernel/user memory split, minimum
1792 vmalloc space and actual amount of RAM, you may not need this
1793 option which should result in a slightly faster kernel.
1798 bool "Allocate 2nd-level pagetables from highmem"
1801 config HW_PERF_EVENTS
1802 bool "Enable hardware performance counter support for perf events"
1803 depends on PERF_EVENTS
1806 Enable hardware performance counter support for perf events. If
1807 disabled, perf events will use software events only.
1811 config FORCE_MAX_ZONEORDER
1812 int "Maximum zone order" if ARCH_SHMOBILE
1813 range 11 64 if ARCH_SHMOBILE
1814 default "12" if SOC_AM33XX
1815 default "9" if SA1111
1818 The kernel memory allocator divides physically contiguous memory
1819 blocks into "zones", where each zone is a power of two number of
1820 pages. This option selects the largest power of two that the kernel
1821 keeps in the memory allocator. If you need to allocate very large
1822 blocks of physically contiguous memory, then you may need to
1823 increase this value.
1825 This config option is actually maximum order plus one. For example,
1826 a value of 11 means that the largest free memory block is 2^10 pages.
1828 config ALIGNMENT_TRAP
1830 depends on CPU_CP15_MMU
1831 default y if !ARCH_EBSA110
1832 select HAVE_PROC_CPU if PROC_FS
1834 ARM processors cannot fetch/store information which is not
1835 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1836 address divisible by 4. On 32-bit ARM processors, these non-aligned
1837 fetch/store instructions will be emulated in software if you say
1838 here, which has a severe performance impact. This is necessary for
1839 correct operation of some network protocols. With an IP-only
1840 configuration it is safe to say N, otherwise say Y.
1842 config UACCESS_WITH_MEMCPY
1843 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1845 default y if CPU_FEROCEON
1847 Implement faster copy_to_user and clear_user methods for CPU
1848 cores where a 8-word STM instruction give significantly higher
1849 memory write throughput than a sequence of individual 32bit stores.
1851 A possible side effect is a slight increase in scheduling latency
1852 between threads sharing the same address space if they invoke
1853 such copy operations with large buffers.
1855 However, if the CPU data cache is using a write-allocate mode,
1856 this option is unlikely to provide any performance gain.
1860 prompt "Enable seccomp to safely compute untrusted bytecode"
1862 This kernel feature is useful for number crunching applications
1863 that may need to compute untrusted bytecode during their
1864 execution. By using pipes or other transports made available to
1865 the process as file descriptors supporting the read/write
1866 syscalls, it's possible to isolate those applications in
1867 their own address space using seccomp. Once seccomp is
1868 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1869 and the task is only allowed to execute a few safe syscalls
1870 defined by each seccomp mode.
1872 config CC_STACKPROTECTOR
1873 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1875 This option turns on the -fstack-protector GCC feature. This
1876 feature puts, at the beginning of functions, a canary value on
1877 the stack just before the return address, and validates
1878 the value just before actually returning. Stack based buffer
1879 overflows (that need to overwrite this return address) now also
1880 overwrite the canary, which gets detected and the attack is then
1881 neutralized via a kernel panic.
1882 This feature requires gcc version 4.2 or above.
1889 bool "Xen guest support on ARM (EXPERIMENTAL)"
1890 depends on ARM && OF
1891 depends on CPU_V7 && !CPU_V6
1893 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1900 bool "Flattened Device Tree support"
1903 select OF_EARLY_FLATTREE
1905 Include support for flattened device tree machine descriptions.
1908 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1911 This is the traditional way of passing data to the kernel at boot
1912 time. If you are solely relying on the flattened device tree (or
1913 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1914 to remove ATAGS support from your kernel binary. If unsure,
1917 config DEPRECATED_PARAM_STRUCT
1918 bool "Provide old way to pass kernel parameters"
1921 This was deprecated in 2001 and announced to live on for 5 years.
1922 Some old boot loaders still use this way.
1924 # Compressed boot loader in ROM. Yes, we really want to ask about
1925 # TEXT and BSS so we preserve their values in the config files.
1926 config ZBOOT_ROM_TEXT
1927 hex "Compressed ROM boot loader base address"
1930 The physical address at which the ROM-able zImage is to be
1931 placed in the target. Platforms which normally make use of
1932 ROM-able zImage formats normally set this to a suitable
1933 value in their defconfig file.
1935 If ZBOOT_ROM is not enabled, this has no effect.
1937 config ZBOOT_ROM_BSS
1938 hex "Compressed ROM boot loader BSS address"
1941 The base address of an area of read/write memory in the target
1942 for the ROM-able zImage which must be available while the
1943 decompressor is running. It must be large enough to hold the
1944 entire decompressed kernel plus an additional 128 KiB.
1945 Platforms which normally make use of ROM-able zImage formats
1946 normally set this to a suitable value in their defconfig file.
1948 If ZBOOT_ROM is not enabled, this has no effect.
1951 bool "Compressed boot loader in ROM/flash"
1952 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1954 Say Y here if you intend to execute your compressed kernel image
1955 (zImage) directly from ROM or flash. If unsure, say N.
1958 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1959 depends on ZBOOT_ROM && ARCH_SH7372
1960 default ZBOOT_ROM_NONE
1962 Include experimental SD/MMC loading code in the ROM-able zImage.
1963 With this enabled it is possible to write the ROM-able zImage
1964 kernel image to an MMC or SD card and boot the kernel straight
1965 from the reset vector. At reset the processor Mask ROM will load
1966 the first part of the ROM-able zImage which in turn loads the
1967 rest the kernel image to RAM.
1969 config ZBOOT_ROM_NONE
1970 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1972 Do not load image from SD or MMC
1974 config ZBOOT_ROM_MMCIF
1975 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1977 Load image from MMCIF hardware block.
1979 config ZBOOT_ROM_SH_MOBILE_SDHI
1980 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1982 Load image from SDHI hardware block
1986 config ARM_APPENDED_DTB
1987 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1988 depends on OF && !ZBOOT_ROM
1990 With this option, the boot code will look for a device tree binary
1991 (DTB) appended to zImage
1992 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1994 This is meant as a backward compatibility convenience for those
1995 systems with a bootloader that can't be upgraded to accommodate
1996 the documented boot protocol using a device tree.
1998 Beware that there is very little in terms of protection against
1999 this option being confused by leftover garbage in memory that might
2000 look like a DTB header after a reboot if no actual DTB is appended
2001 to zImage. Do not leave this option active in a production kernel
2002 if you don't intend to always append a DTB. Proper passing of the
2003 location into r2 of a bootloader provided DTB is always preferable
2006 config ARM_ATAG_DTB_COMPAT
2007 bool "Supplement the appended DTB with traditional ATAG information"
2008 depends on ARM_APPENDED_DTB
2010 Some old bootloaders can't be updated to a DTB capable one, yet
2011 they provide ATAGs with memory configuration, the ramdisk address,
2012 the kernel cmdline string, etc. Such information is dynamically
2013 provided by the bootloader and can't always be stored in a static
2014 DTB. To allow a device tree enabled kernel to be used with such
2015 bootloaders, this option allows zImage to extract the information
2016 from the ATAG list and store it at run time into the appended DTB.
2019 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2020 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2022 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2023 bool "Use bootloader kernel arguments if available"
2025 Uses the command-line options passed by the boot loader instead of
2026 the device tree bootargs property. If the boot loader doesn't provide
2027 any, the device tree bootargs property will be used.
2029 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2030 bool "Extend with bootloader kernel arguments"
2032 The command-line arguments provided by the boot loader will be
2033 appended to the the device tree bootargs property.
2038 string "Default kernel command string"
2041 On some architectures (EBSA110 and CATS), there is currently no way
2042 for the boot loader to pass arguments to the kernel. For these
2043 architectures, you should supply some command-line options at build
2044 time by entering them here. As a minimum, you should specify the
2045 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2048 prompt "Kernel command line type" if CMDLINE != ""
2049 default CMDLINE_FROM_BOOTLOADER
2052 config CMDLINE_FROM_BOOTLOADER
2053 bool "Use bootloader kernel arguments if available"
2055 Uses the command-line options passed by the boot loader. If
2056 the boot loader doesn't provide any, the default kernel command
2057 string provided in CMDLINE will be used.
2059 config CMDLINE_EXTEND
2060 bool "Extend bootloader kernel arguments"
2062 The command-line arguments provided by the boot loader will be
2063 appended to the default kernel command string.
2065 config CMDLINE_FORCE
2066 bool "Always use the default kernel command string"
2068 Always use the default kernel command string, even if the boot
2069 loader passes other arguments to the kernel.
2070 This is useful if you cannot or don't want to change the
2071 command-line options your boot loader passes to the kernel.
2075 bool "Kernel Execute-In-Place from ROM"
2076 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2078 Execute-In-Place allows the kernel to run from non-volatile storage
2079 directly addressable by the CPU, such as NOR flash. This saves RAM
2080 space since the text section of the kernel is not loaded from flash
2081 to RAM. Read-write sections, such as the data section and stack,
2082 are still copied to RAM. The XIP kernel is not compressed since
2083 it has to run directly from flash, so it will take more space to
2084 store it. The flash address used to link the kernel object files,
2085 and for storing it, is configuration dependent. Therefore, if you
2086 say Y here, you must know the proper physical address where to
2087 store the kernel image depending on your own flash memory usage.
2089 Also note that the make target becomes "make xipImage" rather than
2090 "make zImage" or "make Image". The final kernel binary to put in
2091 ROM memory will be arch/arm/boot/xipImage.
2095 config XIP_PHYS_ADDR
2096 hex "XIP Kernel Physical Location"
2097 depends on XIP_KERNEL
2098 default "0x00080000"
2100 This is the physical address in your flash memory the kernel will
2101 be linked for and stored to. This address is dependent on your
2105 bool "Kexec system call (EXPERIMENTAL)"
2106 depends on (!SMP || HOTPLUG_CPU)
2108 kexec is a system call that implements the ability to shutdown your
2109 current kernel, and to start another kernel. It is like a reboot
2110 but it is independent of the system firmware. And like a reboot
2111 you can start any kernel with it, not just Linux.
2113 It is an ongoing process to be certain the hardware in a machine
2114 is properly shutdown, so do not be surprised if this code does not
2115 initially work for you. It may help to enable device hotplugging
2119 bool "Export atags in procfs"
2120 depends on ATAGS && KEXEC
2123 Should the atags used to boot the kernel be exported in an "atags"
2124 file in procfs. Useful with kexec.
2127 bool "Build kdump crash kernel (EXPERIMENTAL)"
2129 Generate crash dump after being started by kexec. This should
2130 be normally only set in special crash dump kernels which are
2131 loaded in the main kernel with kexec-tools into a specially
2132 reserved region and then later executed after a crash by
2133 kdump/kexec. The crash dump kernel must be compiled to a
2134 memory address not used by the main kernel
2136 For more details see Documentation/kdump/kdump.txt
2138 config AUTO_ZRELADDR
2139 bool "Auto calculation of the decompressed kernel image address"
2140 depends on !ZBOOT_ROM && !ARCH_U300
2142 ZRELADDR is the physical address where the decompressed kernel
2143 image will be placed. If AUTO_ZRELADDR is selected, the address
2144 will be determined at run-time by masking the current IP with
2145 0xf8000000. This assumes the zImage being placed in the first 128MB
2146 from start of memory.
2150 menu "CPU Power Management"
2154 source "drivers/cpufreq/Kconfig"
2157 tristate "CPUfreq driver for i.MX CPUs"
2158 depends on ARCH_MXC && CPU_FREQ
2159 select CPU_FREQ_TABLE
2161 This enables the CPUfreq driver for i.MX CPUs.
2163 config CPU_FREQ_SA1100
2166 config CPU_FREQ_SA1110
2169 config CPU_FREQ_INTEGRATOR
2170 tristate "CPUfreq driver for ARM Integrator CPUs"
2171 depends on ARCH_INTEGRATOR && CPU_FREQ
2174 This enables the CPUfreq driver for ARM Integrator CPUs.
2176 For details, take a look at <file:Documentation/cpu-freq>.
2182 depends on CPU_FREQ && ARCH_PXA && PXA25x
2184 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2185 select CPU_FREQ_TABLE
2190 Internal configuration node for common cpufreq on Samsung SoC
2192 config CPU_FREQ_S3C24XX
2193 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2194 depends on ARCH_S3C24XX && CPU_FREQ
2197 This enables the CPUfreq driver for the Samsung S3C24XX family
2200 For details, take a look at <file:Documentation/cpu-freq>.
2204 config CPU_FREQ_S3C24XX_PLL
2205 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2206 depends on CPU_FREQ_S3C24XX
2208 Compile in support for changing the PLL frequency from the
2209 S3C24XX series CPUfreq driver. The PLL takes time to settle
2210 after a frequency change, so by default it is not enabled.
2212 This also means that the PLL tables for the selected CPU(s) will
2213 be built which may increase the size of the kernel image.
2215 config CPU_FREQ_S3C24XX_DEBUG
2216 bool "Debug CPUfreq Samsung driver core"
2217 depends on CPU_FREQ_S3C24XX
2219 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2221 config CPU_FREQ_S3C24XX_IODEBUG
2222 bool "Debug CPUfreq Samsung driver IO timing"
2223 depends on CPU_FREQ_S3C24XX
2225 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2227 config CPU_FREQ_S3C24XX_DEBUGFS
2228 bool "Export debugfs for CPUFreq"
2229 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2231 Export status information via debugfs.
2235 source "drivers/cpuidle/Kconfig"
2239 menu "Floating point emulation"
2241 comment "At least one emulation must be selected"
2244 bool "NWFPE math emulation"
2245 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2247 Say Y to include the NWFPE floating point emulator in the kernel.
2248 This is necessary to run most binaries. Linux does not currently
2249 support floating point hardware so you need to say Y here even if
2250 your machine has an FPA or floating point co-processor podule.
2252 You may say N here if you are going to load the Acorn FPEmulator
2253 early in the bootup.
2256 bool "Support extended precision"
2257 depends on FPE_NWFPE
2259 Say Y to include 80-bit support in the kernel floating-point
2260 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2261 Note that gcc does not generate 80-bit operations by default,
2262 so in most cases this option only enlarges the size of the
2263 floating point emulator without any good reason.
2265 You almost surely want to say N here.
2268 bool "FastFPE math emulation (EXPERIMENTAL)"
2269 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2271 Say Y here to include the FAST floating point emulator in the kernel.
2272 This is an experimental much faster emulator which now also has full
2273 precision for the mantissa. It does not support any exceptions.
2274 It is very simple, and approximately 3-6 times faster than NWFPE.
2276 It should be sufficient for most programs. It may be not suitable
2277 for scientific calculations, but you have to check this for yourself.
2278 If you do not feel you need a faster FP emulation you should better
2282 bool "VFP-format floating point maths"
2283 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2285 Say Y to include VFP support code in the kernel. This is needed
2286 if your hardware includes a VFP unit.
2288 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2289 release notes and additional status information.
2291 Say N if your target does not have VFP hardware.
2299 bool "Advanced SIMD (NEON) Extension support"
2300 depends on VFPv3 && CPU_V7
2302 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2307 menu "Userspace binary formats"
2309 source "fs/Kconfig.binfmt"
2312 tristate "RISC OS personality"
2315 Say Y here to include the kernel code necessary if you want to run
2316 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2317 experimental; if this sounds frightening, say N and sleep in peace.
2318 You can also say M here to compile this support as a module (which
2319 will be called arthur).
2323 menu "Power management options"
2325 source "kernel/power/Kconfig"
2327 config ARCH_SUSPEND_POSSIBLE
2328 depends on !ARCH_S5PC100
2329 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2330 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2333 config ARM_CPU_SUSPEND
2338 source "net/Kconfig"
2340 source "drivers/Kconfig"
2344 source "arch/arm/Kconfig.debug"
2346 source "security/Kconfig"
2348 source "crypto/Kconfig"
2350 source "lib/Kconfig"
2352 source "arch/arm/kvm/Kconfig"