5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
72 select GENERIC_ALLOCATOR
83 The Extended Industry Standard Architecture (EISA) bus was
84 developed as an open alternative to the IBM MicroChannel bus.
86 The EISA bus provided some of the features of the IBM MicroChannel
87 bus while maintaining backward compatibility with cards made for
88 the older ISA bus. The EISA bus saw limited use between 1988 and
89 1995 when it was made obsolete by the PCI bus.
91 Say Y here if you are building a kernel for an EISA-based machine.
101 MicroChannel Architecture is found in some IBM PS/2 machines and
102 laptops. It is a bus system similar to PCI or ISA. See
103 <file:Documentation/mca.txt> (and especially the web page given
104 there) before attempting to build an MCA bus kernel.
106 config STACKTRACE_SUPPORT
110 config HAVE_LATENCYTOP_SUPPORT
115 config LOCKDEP_SUPPORT
119 config TRACE_IRQFLAGS_SUPPORT
123 config HARDIRQS_SW_RESEND
127 config GENERIC_IRQ_PROBE
131 config GENERIC_LOCKBREAK
134 depends on SMP && PREEMPT
136 config RWSEM_GENERIC_SPINLOCK
140 config RWSEM_XCHGADD_ALGORITHM
143 config ARCH_HAS_ILOG2_U32
146 config ARCH_HAS_ILOG2_U64
149 config ARCH_HAS_CPUFREQ
152 Internal node to signify that the ARCH has CPUFREQ support
153 and that the relevant menu configurations are displayed for
156 config ARCH_HAS_CPU_IDLE_WAIT
159 config GENERIC_HWEIGHT
163 config GENERIC_CALIBRATE_DELAY
167 config ARCH_MAY_HAVE_PC_FDC
173 config NEED_DMA_MAP_STATE
176 config GENERIC_ISA_DMA
187 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
188 default DRAM_BASE if REMAP_VECTORS_TO_RAM
191 The base address of exception vectors.
193 config ARM_PATCH_PHYS_VIRT
194 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
195 depends on EXPERIMENTAL
196 depends on !XIP_KERNEL && MMU
197 depends on !ARCH_REALVIEW || !SPARSEMEM
199 Patch phys-to-virt translation functions at runtime according to
200 the position of the kernel in system memory.
202 This can only be used with non-XIP with MMU kernels where
203 the base of physical memory is at a 16MB boundary.
205 config ARM_PATCH_PHYS_VIRT_16BIT
207 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
209 source "init/Kconfig"
211 source "kernel/Kconfig.freezer"
216 bool "MMU-based Paged Memory Management Support"
219 Select if you want MMU-based virtualised addressing space
220 support by paged memory management. If unsure, say 'Y'.
223 # The "ARM system type" choice list is ordered alphabetically by option
224 # text. Please add new entries in the option alphabetic order.
227 prompt "ARM system type"
228 default ARCH_VERSATILE
230 config ARCH_INTEGRATOR
231 bool "ARM Ltd. Integrator family"
233 select ARCH_HAS_CPUFREQ
236 select GENERIC_CLOCKEVENTS
237 select PLAT_VERSATILE
238 select PLAT_VERSATILE_FPGA_IRQ
240 Support for ARM's Integrator platform.
243 bool "ARM Ltd. RealView family"
247 select GENERIC_CLOCKEVENTS
248 select ARCH_WANT_OPTIONAL_GPIOLIB
249 select PLAT_VERSATILE
250 select PLAT_VERSATILE_CLCD
251 select ARM_TIMER_SP804
252 select GPIO_PL061 if GPIOLIB
254 This enables support for ARM Ltd RealView boards.
256 config ARCH_VERSATILE
257 bool "ARM Ltd. Versatile family"
262 select GENERIC_CLOCKEVENTS
263 select ARCH_WANT_OPTIONAL_GPIOLIB
264 select PLAT_VERSATILE
265 select PLAT_VERSATILE_CLCD
266 select PLAT_VERSATILE_FPGA_IRQ
267 select ARM_TIMER_SP804
269 This enables support for ARM Ltd Versatile board.
272 bool "ARM Ltd. Versatile Express family"
273 select ARCH_WANT_OPTIONAL_GPIOLIB
275 select ARM_TIMER_SP804
277 select GENERIC_CLOCKEVENTS
279 select HAVE_PATA_PLATFORM
281 select PLAT_VERSATILE
282 select PLAT_VERSATILE_CLCD
284 This enables support for the ARM Ltd Versatile Express boards.
288 select ARCH_REQUIRE_GPIOLIB
291 This enables support for systems based on the Atmel AT91RM9200,
292 AT91SAM9 and AT91CAP9 processors.
295 bool "Broadcom BCMRING"
300 select GENERIC_CLOCKEVENTS
301 select ARCH_WANT_OPTIONAL_GPIOLIB
303 Support for Broadcom's BCMRing platform.
306 bool "Cirrus Logic CLPS711x/EP721x-based"
308 select ARCH_USES_GETTIMEOFFSET
310 Support for Cirrus Logic 711x/721x based boards.
313 bool "Cavium Networks CNS3XXX family"
315 select GENERIC_CLOCKEVENTS
317 select MIGHT_HAVE_PCI
318 select PCI_DOMAINS if PCI
320 Support for Cavium Networks CNS3XXX platform.
323 bool "Cortina Systems Gemini"
325 select ARCH_REQUIRE_GPIOLIB
326 select ARCH_USES_GETTIMEOFFSET
328 Support for the Cortina Systems Gemini family SoCs
335 select ARCH_USES_GETTIMEOFFSET
337 This is an evaluation board for the StrongARM processor available
338 from Digital. It has limited hardware on-board, including an
339 Ethernet interface, two PCMCIA sockets, two serial ports and a
348 select ARCH_REQUIRE_GPIOLIB
349 select ARCH_HAS_HOLES_MEMORYMODEL
350 select ARCH_USES_GETTIMEOFFSET
352 This enables support for the Cirrus EP93xx series of CPUs.
354 config ARCH_FOOTBRIDGE
358 select GENERIC_CLOCKEVENTS
360 Support for systems based on the DC21285 companion chip
361 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
364 bool "Freescale MXC/iMX-based"
365 select GENERIC_CLOCKEVENTS
366 select ARCH_REQUIRE_GPIOLIB
368 select HAVE_SCHED_CLOCK
370 Support for Freescale MXC/iMX-based family of processors
373 bool "Freescale MXS-based"
374 select GENERIC_CLOCKEVENTS
375 select ARCH_REQUIRE_GPIOLIB
378 Support for Freescale MXS-based family of processors
381 bool "Freescale STMP3xxx"
384 select ARCH_REQUIRE_GPIOLIB
385 select GENERIC_CLOCKEVENTS
386 select USB_ARCH_HAS_EHCI
388 Support for systems based on the Freescale 3xxx CPUs.
391 bool "Hilscher NetX based"
394 select GENERIC_CLOCKEVENTS
396 This enables support for systems based on the Hilscher NetX Soc
399 bool "Hynix HMS720x-based"
402 select ARCH_USES_GETTIMEOFFSET
404 This enables support for systems based on the Hynix HMS720x
412 select ARCH_SUPPORTS_MSI
415 Support for Intel's IOP13XX (XScale) family of processors.
423 select ARCH_REQUIRE_GPIOLIB
425 Support for Intel's 80219 and IOP32X (XScale) family of
434 select ARCH_REQUIRE_GPIOLIB
436 Support for Intel's IOP33X (XScale) family of processors.
443 select ARCH_USES_GETTIMEOFFSET
445 Support for Intel's IXP23xx (XScale) family of processors.
448 bool "IXP2400/2800-based"
452 select ARCH_USES_GETTIMEOFFSET
454 Support for Intel's IXP2400/2800 (XScale) family of processors.
461 select GENERIC_CLOCKEVENTS
462 select HAVE_SCHED_CLOCK
463 select MIGHT_HAVE_PCI
464 select DMABOUNCE if PCI
466 Support for Intel's IXP4XX (XScale) family of processors.
472 select ARCH_REQUIRE_GPIOLIB
473 select GENERIC_CLOCKEVENTS
476 Support for the Marvell Dove SoC 88AP510
479 bool "Marvell Kirkwood"
482 select ARCH_REQUIRE_GPIOLIB
483 select GENERIC_CLOCKEVENTS
486 Support for the following Marvell Kirkwood series SoCs:
487 88F6180, 88F6192 and 88F6281.
490 bool "Marvell Loki (88RC8480)"
492 select GENERIC_CLOCKEVENTS
495 Support for the Marvell Loki (88RC8480) SoC.
500 select ARCH_REQUIRE_GPIOLIB
503 select USB_ARCH_HAS_OHCI
506 select GENERIC_CLOCKEVENTS
508 Support for the NXP LPC32XX family of processors
511 bool "Marvell MV78xx0"
514 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
518 Support for the following Marvell MV78xx0 series SoCs:
526 select ARCH_REQUIRE_GPIOLIB
527 select GENERIC_CLOCKEVENTS
530 Support for the following Marvell Orion 5x series SoCs:
531 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
532 Orion-2 (5281), Orion-1-90 (6183).
535 bool "Marvell PXA168/910/MMP2"
537 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
540 select HAVE_SCHED_CLOCK
545 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
548 bool "Micrel/Kendin KS8695"
550 select ARCH_REQUIRE_GPIOLIB
551 select ARCH_USES_GETTIMEOFFSET
553 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
554 System-on-Chip devices.
557 bool "NetSilicon NS9xxx"
560 select GENERIC_CLOCKEVENTS
563 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
566 <http://www.digi.com/products/microprocessors/index.jsp>
569 bool "Nuvoton W90X900 CPU"
571 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
575 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
576 At present, the w90x900 has been renamed nuc900, regarding
577 the ARM series product line, you can login the following
578 link address to know more.
580 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
581 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
584 bool "Nuvoton NUC93X CPU"
588 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
589 low-power and high performance MPEG-4/JPEG multimedia controller chip.
595 select GENERIC_CLOCKEVENTS
598 select HAVE_SCHED_CLOCK
599 select ARCH_HAS_BARRIERS if CACHE_L2X0
600 select ARCH_HAS_CPUFREQ
602 This enables support for NVIDIA Tegra based systems (Tegra APX,
603 Tegra 6xx and Tegra 2 series).
606 bool "Philips Nexperia PNX4008 Mobile"
609 select ARCH_USES_GETTIMEOFFSET
611 This enables support for Philips PNX4008 mobile platform.
614 bool "PXA2xx/PXA3xx-based"
617 select ARCH_HAS_CPUFREQ
619 select ARCH_REQUIRE_GPIOLIB
620 select GENERIC_CLOCKEVENTS
621 select HAVE_SCHED_CLOCK
626 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
631 select GENERIC_CLOCKEVENTS
632 select ARCH_REQUIRE_GPIOLIB
635 Support for Qualcomm MSM/QSD based systems. This runs on the
636 apps processor of the MSM/QSD and depends on a shared memory
637 interface to the modem processor which runs the baseband
638 stack and controls some vital subsystems
639 (clock and power control, etc).
642 bool "Renesas SH-Mobile / R-Mobile"
645 select GENERIC_CLOCKEVENTS
648 select MULTI_IRQ_HANDLER
650 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
657 select ARCH_MAY_HAVE_PC_FDC
658 select HAVE_PATA_PLATFORM
661 select ARCH_SPARSEMEM_ENABLE
662 select ARCH_USES_GETTIMEOFFSET
664 On the Acorn Risc-PC, Linux can support the internal IDE disk and
665 CD-ROM interface, serial and parallel port, and the floppy drive.
671 select ARCH_SPARSEMEM_ENABLE
673 select ARCH_HAS_CPUFREQ
675 select GENERIC_CLOCKEVENTS
677 select HAVE_SCHED_CLOCK
679 select ARCH_REQUIRE_GPIOLIB
681 Support for StrongARM 11x0 based boards.
684 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
686 select ARCH_HAS_CPUFREQ
688 select ARCH_USES_GETTIMEOFFSET
689 select HAVE_S3C2410_I2C if I2C
691 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
692 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
693 the Samsung SMDK2410 development board (and derivatives).
695 Note, the S3C2416 and the S3C2450 are so close that they even share
696 the same SoC ID code. This means that there is no seperate machine
697 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
700 bool "Samsung S3C64XX"
706 select ARCH_USES_GETTIMEOFFSET
707 select ARCH_HAS_CPUFREQ
708 select ARCH_REQUIRE_GPIOLIB
709 select SAMSUNG_CLKSRC
710 select SAMSUNG_IRQ_VIC_TIMER
711 select SAMSUNG_IRQ_UART
712 select S3C_GPIO_TRACK
713 select S3C_GPIO_PULL_UPDOWN
714 select S3C_GPIO_CFG_S3C24XX
715 select S3C_GPIO_CFG_S3C64XX
717 select USB_ARCH_HAS_OHCI
718 select SAMSUNG_GPIOLIB_4BIT
719 select HAVE_S3C2410_I2C if I2C
720 select HAVE_S3C2410_WATCHDOG if WATCHDOG
722 Samsung S3C64XX series based systems
725 bool "Samsung S5P6440 S5P6450"
729 select HAVE_S3C2410_WATCHDOG if WATCHDOG
730 select GENERIC_CLOCKEVENTS
731 select HAVE_SCHED_CLOCK
732 select HAVE_S3C2410_I2C if I2C
733 select HAVE_S3C_RTC if RTC_CLASS
735 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
739 bool "Samsung S5P6442"
743 select ARCH_USES_GETTIMEOFFSET
744 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 Samsung S5P6442 CPU based systems
749 bool "Samsung S5PC100"
753 select ARM_L1_CACHE_SHIFT_6
754 select ARCH_USES_GETTIMEOFFSET
755 select HAVE_S3C2410_I2C if I2C
756 select HAVE_S3C_RTC if RTC_CLASS
757 select HAVE_S3C2410_WATCHDOG if WATCHDOG
759 Samsung S5PC100 series based systems
762 bool "Samsung S5PV210/S5PC110"
764 select ARCH_SPARSEMEM_ENABLE
767 select ARM_L1_CACHE_SHIFT_6
768 select ARCH_HAS_CPUFREQ
769 select GENERIC_CLOCKEVENTS
770 select HAVE_SCHED_CLOCK
771 select HAVE_S3C2410_I2C if I2C
772 select HAVE_S3C_RTC if RTC_CLASS
773 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 Samsung S5PV210/S5PC110 series based systems
778 bool "Samsung EXYNOS4"
780 select ARCH_SPARSEMEM_ENABLE
783 select ARCH_HAS_CPUFREQ
784 select GENERIC_CLOCKEVENTS
785 select HAVE_S3C_RTC if RTC_CLASS
786 select HAVE_S3C2410_I2C if I2C
787 select HAVE_S3C2410_WATCHDOG if WATCHDOG
789 Samsung EXYNOS4 series based systems
798 select ARCH_USES_GETTIMEOFFSET
800 Support for the StrongARM based Digital DNARD machine, also known
801 as "Shark" (<http://www.shark-linux.de/shark.html>).
804 bool "Telechips TCC ARM926-based systems"
808 select GENERIC_CLOCKEVENTS
810 Support for Telechips TCC ARM926-based systems.
813 bool "ST-Ericsson U300 Series"
816 select HAVE_SCHED_CLOCK
820 select GENERIC_CLOCKEVENTS
824 Support for ST-Ericsson U300 series mobile platforms.
827 bool "ST-Ericsson U8500 Series"
830 select GENERIC_CLOCKEVENTS
832 select ARCH_REQUIRE_GPIOLIB
833 select ARCH_HAS_CPUFREQ
835 Support for ST-Ericsson's Ux500 architecture
838 bool "STMicroelectronics Nomadik"
843 select GENERIC_CLOCKEVENTS
844 select ARCH_REQUIRE_GPIOLIB
846 Support for the Nomadik platform by ST-Ericsson
850 select GENERIC_CLOCKEVENTS
851 select ARCH_REQUIRE_GPIOLIB
855 select GENERIC_ALLOCATOR
856 select ARCH_HAS_HOLES_MEMORYMODEL
858 Support for TI's DaVinci platform.
863 select ARCH_REQUIRE_GPIOLIB
864 select ARCH_HAS_CPUFREQ
865 select GENERIC_CLOCKEVENTS
866 select HAVE_SCHED_CLOCK
867 select ARCH_HAS_HOLES_MEMORYMODEL
869 Support for TI's OMAP platform (OMAP1/2/3/4).
874 select ARCH_REQUIRE_GPIOLIB
876 select GENERIC_CLOCKEVENTS
879 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
882 bool "VIA/WonderMedia 85xx"
885 select ARCH_HAS_CPUFREQ
886 select GENERIC_CLOCKEVENTS
887 select ARCH_REQUIRE_GPIOLIB
890 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
894 # This is sorted alphabetically by mach-* pathname. However, plat-*
895 # Kconfigs may be included either alphabetically (according to the
896 # plat- suffix) or along side the corresponding mach-* source.
898 source "arch/arm/mach-at91/Kconfig"
900 source "arch/arm/mach-bcmring/Kconfig"
902 source "arch/arm/mach-clps711x/Kconfig"
904 source "arch/arm/mach-cns3xxx/Kconfig"
906 source "arch/arm/mach-davinci/Kconfig"
908 source "arch/arm/mach-dove/Kconfig"
910 source "arch/arm/mach-ep93xx/Kconfig"
912 source "arch/arm/mach-footbridge/Kconfig"
914 source "arch/arm/mach-gemini/Kconfig"
916 source "arch/arm/mach-h720x/Kconfig"
918 source "arch/arm/mach-integrator/Kconfig"
920 source "arch/arm/mach-iop32x/Kconfig"
922 source "arch/arm/mach-iop33x/Kconfig"
924 source "arch/arm/mach-iop13xx/Kconfig"
926 source "arch/arm/mach-ixp4xx/Kconfig"
928 source "arch/arm/mach-ixp2000/Kconfig"
930 source "arch/arm/mach-ixp23xx/Kconfig"
932 source "arch/arm/mach-kirkwood/Kconfig"
934 source "arch/arm/mach-ks8695/Kconfig"
936 source "arch/arm/mach-loki/Kconfig"
938 source "arch/arm/mach-lpc32xx/Kconfig"
940 source "arch/arm/mach-msm/Kconfig"
942 source "arch/arm/mach-mv78xx0/Kconfig"
944 source "arch/arm/plat-mxc/Kconfig"
946 source "arch/arm/mach-mxs/Kconfig"
948 source "arch/arm/mach-netx/Kconfig"
950 source "arch/arm/mach-nomadik/Kconfig"
951 source "arch/arm/plat-nomadik/Kconfig"
953 source "arch/arm/mach-ns9xxx/Kconfig"
955 source "arch/arm/mach-nuc93x/Kconfig"
957 source "arch/arm/plat-omap/Kconfig"
959 source "arch/arm/mach-omap1/Kconfig"
961 source "arch/arm/mach-omap2/Kconfig"
963 source "arch/arm/mach-orion5x/Kconfig"
965 source "arch/arm/mach-pxa/Kconfig"
966 source "arch/arm/plat-pxa/Kconfig"
968 source "arch/arm/mach-mmp/Kconfig"
970 source "arch/arm/mach-realview/Kconfig"
972 source "arch/arm/mach-sa1100/Kconfig"
974 source "arch/arm/plat-samsung/Kconfig"
975 source "arch/arm/plat-s3c24xx/Kconfig"
976 source "arch/arm/plat-s5p/Kconfig"
978 source "arch/arm/plat-spear/Kconfig"
980 source "arch/arm/plat-tcc/Kconfig"
983 source "arch/arm/mach-s3c2400/Kconfig"
984 source "arch/arm/mach-s3c2410/Kconfig"
985 source "arch/arm/mach-s3c2412/Kconfig"
986 source "arch/arm/mach-s3c2416/Kconfig"
987 source "arch/arm/mach-s3c2440/Kconfig"
988 source "arch/arm/mach-s3c2443/Kconfig"
992 source "arch/arm/mach-s3c64xx/Kconfig"
995 source "arch/arm/mach-s5p64x0/Kconfig"
997 source "arch/arm/mach-s5p6442/Kconfig"
999 source "arch/arm/mach-s5pc100/Kconfig"
1001 source "arch/arm/mach-s5pv210/Kconfig"
1003 source "arch/arm/mach-exynos4/Kconfig"
1005 source "arch/arm/mach-shmobile/Kconfig"
1007 source "arch/arm/plat-stmp3xxx/Kconfig"
1009 source "arch/arm/mach-tegra/Kconfig"
1011 source "arch/arm/mach-u300/Kconfig"
1013 source "arch/arm/mach-ux500/Kconfig"
1015 source "arch/arm/mach-versatile/Kconfig"
1017 source "arch/arm/mach-vexpress/Kconfig"
1018 source "arch/arm/plat-versatile/Kconfig"
1020 source "arch/arm/mach-vt8500/Kconfig"
1022 source "arch/arm/mach-w90x900/Kconfig"
1024 # Definitions to make life easier
1030 select GENERIC_CLOCKEVENTS
1031 select HAVE_SCHED_CLOCK
1035 select HAVE_SCHED_CLOCK
1040 config PLAT_VERSATILE
1043 config ARM_TIMER_SP804
1046 source arch/arm/mm/Kconfig
1049 bool "Enable iWMMXt support"
1050 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1051 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1053 Enable support for iWMMXt context switching at run time if
1054 running on a CPU that supports it.
1056 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1059 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1063 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1064 (!ARCH_OMAP3 || OMAP3_EMU)
1068 config MULTI_IRQ_HANDLER
1071 Allow each machine to specify it's own IRQ handler at run time.
1074 source "arch/arm/Kconfig-nommu"
1077 config ARM_ERRATA_411920
1078 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1079 depends on CPU_V6 || CPU_V6K
1081 Invalidation of the Instruction Cache operation can
1082 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1083 It does not affect the MPCore. This option enables the ARM Ltd.
1084 recommended workaround.
1086 config ARM_ERRATA_430973
1087 bool "ARM errata: Stale prediction on replaced interworking branch"
1090 This option enables the workaround for the 430973 Cortex-A8
1091 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1092 interworking branch is replaced with another code sequence at the
1093 same virtual address, whether due to self-modifying code or virtual
1094 to physical address re-mapping, Cortex-A8 does not recover from the
1095 stale interworking branch prediction. This results in Cortex-A8
1096 executing the new code sequence in the incorrect ARM or Thumb state.
1097 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1098 and also flushes the branch target cache at every context switch.
1099 Note that setting specific bits in the ACTLR register may not be
1100 available in non-secure mode.
1102 config ARM_ERRATA_458693
1103 bool "ARM errata: Processor deadlock when a false hazard is created"
1106 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1107 erratum. For very specific sequences of memory operations, it is
1108 possible for a hazard condition intended for a cache line to instead
1109 be incorrectly associated with a different cache line. This false
1110 hazard might then cause a processor deadlock. The workaround enables
1111 the L1 caching of the NEON accesses and disables the PLD instruction
1112 in the ACTLR register. Note that setting specific bits in the ACTLR
1113 register may not be available in non-secure mode.
1115 config ARM_ERRATA_460075
1116 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1119 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1120 erratum. Any asynchronous access to the L2 cache may encounter a
1121 situation in which recent store transactions to the L2 cache are lost
1122 and overwritten with stale memory contents from external memory. The
1123 workaround disables the write-allocate mode for the L2 cache via the
1124 ACTLR register. Note that setting specific bits in the ACTLR register
1125 may not be available in non-secure mode.
1127 config ARM_ERRATA_742230
1128 bool "ARM errata: DMB operation may be faulty"
1129 depends on CPU_V7 && SMP
1131 This option enables the workaround for the 742230 Cortex-A9
1132 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1133 between two write operations may not ensure the correct visibility
1134 ordering of the two writes. This workaround sets a specific bit in
1135 the diagnostic register of the Cortex-A9 which causes the DMB
1136 instruction to behave as a DSB, ensuring the correct behaviour of
1139 config ARM_ERRATA_742231
1140 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1141 depends on CPU_V7 && SMP
1143 This option enables the workaround for the 742231 Cortex-A9
1144 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1145 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1146 accessing some data located in the same cache line, may get corrupted
1147 data due to bad handling of the address hazard when the line gets
1148 replaced from one of the CPUs at the same time as another CPU is
1149 accessing it. This workaround sets specific bits in the diagnostic
1150 register of the Cortex-A9 which reduces the linefill issuing
1151 capabilities of the processor.
1153 config PL310_ERRATA_588369
1154 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1155 depends on CACHE_L2X0
1157 The PL310 L2 cache controller implements three types of Clean &
1158 Invalidate maintenance operations: by Physical Address
1159 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1160 They are architecturally defined to behave as the execution of a
1161 clean operation followed immediately by an invalidate operation,
1162 both performing to the same memory location. This functionality
1163 is not correctly implemented in PL310 as clean lines are not
1164 invalidated as a result of these operations.
1166 config ARM_ERRATA_720789
1167 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1168 depends on CPU_V7 && SMP
1170 This option enables the workaround for the 720789 Cortex-A9 (prior to
1171 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1172 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1173 As a consequence of this erratum, some TLB entries which should be
1174 invalidated are not, resulting in an incoherency in the system page
1175 tables. The workaround changes the TLB flushing routines to invalidate
1176 entries regardless of the ASID.
1178 config PL310_ERRATA_727915
1179 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1180 depends on CACHE_L2X0
1182 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1183 operation (offset 0x7FC). This operation runs in background so that
1184 PL310 can handle normal accesses while it is in progress. Under very
1185 rare circumstances, due to this erratum, write data can be lost when
1186 PL310 treats a cacheable write transaction during a Clean &
1187 Invalidate by Way operation.
1189 config ARM_ERRATA_743622
1190 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1193 This option enables the workaround for the 743622 Cortex-A9
1194 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1195 optimisation in the Cortex-A9 Store Buffer may lead to data
1196 corruption. This workaround sets a specific bit in the diagnostic
1197 register of the Cortex-A9 which disables the Store Buffer
1198 optimisation, preventing the defect from occurring. This has no
1199 visible impact on the overall performance or power consumption of the
1202 config ARM_ERRATA_751472
1203 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1204 depends on CPU_V7 && SMP
1206 This option enables the workaround for the 751472 Cortex-A9 (prior
1207 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1208 completion of a following broadcasted operation if the second
1209 operation is received by a CPU before the ICIALLUIS has completed,
1210 potentially leading to corrupted entries in the cache or TLB.
1212 config ARM_ERRATA_753970
1213 bool "ARM errata: cache sync operation may be faulty"
1214 depends on CACHE_PL310
1216 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1218 Under some condition the effect of cache sync operation on
1219 the store buffer still remains when the operation completes.
1220 This means that the store buffer is always asked to drain and
1221 this prevents it from merging any further writes. The workaround
1222 is to replace the normal offset of cache sync operation (0x730)
1223 by another offset targeting an unmapped PL310 register 0x740.
1224 This has the same effect as the cache sync operation: store buffer
1225 drain and waiting for all buffers empty.
1227 config ARM_ERRATA_754322
1228 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1231 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1232 r3p*) erratum. A speculative memory access may cause a page table walk
1233 which starts prior to an ASID switch but completes afterwards. This
1234 can populate the micro-TLB with a stale entry which may be hit with
1235 the new ASID. This workaround places two dsb instructions in the mm
1236 switching code so that no page table walks can cross the ASID switch.
1238 config ARM_ERRATA_754327
1239 bool "ARM errata: no automatic Store Buffer drain"
1240 depends on CPU_V7 && SMP
1242 This option enables the workaround for the 754327 Cortex-A9 (prior to
1243 r2p0) erratum. The Store Buffer does not have any automatic draining
1244 mechanism and therefore a livelock may occur if an external agent
1245 continuously polls a memory location waiting to observe an update.
1246 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1247 written polling loops from denying visibility of updates to memory.
1251 source "arch/arm/common/Kconfig"
1261 Find out whether you have ISA slots on your motherboard. ISA is the
1262 name of a bus system, i.e. the way the CPU talks to the other stuff
1263 inside your box. Other bus systems are PCI, EISA, MicroChannel
1264 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1265 newer boards don't support it. If you have ISA, say Y, otherwise N.
1267 # Select ISA DMA controller support
1272 # Select ISA DMA interface
1277 bool "PCI support" if MIGHT_HAVE_PCI
1279 Find out whether you have a PCI motherboard. PCI is the name of a
1280 bus system, i.e. the way the CPU talks to the other stuff inside
1281 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1282 VESA. If you have PCI, say Y, otherwise N.
1288 config PCI_NANOENGINE
1289 bool "BSE nanoEngine PCI support"
1290 depends on SA1100_NANOENGINE
1292 Enable PCI on the BSE nanoEngine board.
1297 # Select the host bridge type
1298 config PCI_HOST_VIA82C505
1300 depends on PCI && ARCH_SHARK
1303 config PCI_HOST_ITE8152
1305 depends on PCI && MACH_ARMCORE
1309 source "drivers/pci/Kconfig"
1311 source "drivers/pcmcia/Kconfig"
1315 menu "Kernel Features"
1317 source "kernel/time/Kconfig"
1320 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1321 depends on EXPERIMENTAL
1322 depends on CPU_V6K || CPU_V7
1323 depends on GENERIC_CLOCKEVENTS
1324 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1325 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1326 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1327 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1328 select USE_GENERIC_SMP_HELPERS
1329 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1331 This enables support for systems with more than one CPU. If you have
1332 a system with only one CPU, like most personal computers, say N. If
1333 you have a system with more than one CPU, say Y.
1335 If you say N here, the kernel will run on single and multiprocessor
1336 machines, but will use only one CPU of a multiprocessor machine. If
1337 you say Y here, the kernel will run on many, but not all, single
1338 processor machines. On a single processor machine, the kernel will
1339 run faster if you say N here.
1341 See also <file:Documentation/i386/IO-APIC.txt>,
1342 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1343 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1345 If you don't know what to do here, say N.
1348 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1349 depends on EXPERIMENTAL
1350 depends on SMP && !XIP_KERNEL
1353 SMP kernels contain instructions which fail on non-SMP processors.
1354 Enabling this option allows the kernel to modify itself to make
1355 these instructions safe. Disabling it allows about 1K of space
1358 If you don't know what to do here, say Y.
1364 This option enables support for the ARM system coherency unit
1371 This options enables support for the ARM timer and watchdog unit
1374 prompt "Memory split"
1377 Select the desired split between kernel and user memory.
1379 If you are not absolutely sure what you are doing, leave this
1383 bool "3G/1G user/kernel split"
1385 bool "2G/2G user/kernel split"
1387 bool "1G/3G user/kernel split"
1392 default 0x40000000 if VMSPLIT_1G
1393 default 0x80000000 if VMSPLIT_2G
1397 int "Maximum number of CPUs (2-32)"
1403 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1404 depends on SMP && HOTPLUG && EXPERIMENTAL
1405 depends on !ARCH_MSM
1407 Say Y here to experiment with turning CPUs off and on. CPUs
1408 can be controlled through /sys/devices/system/cpu.
1411 bool "Use local timer interrupts"
1414 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1416 Enable support for local timers on SMP platforms, rather then the
1417 legacy IPI broadcast method. Local timers allows the system
1418 accounting to be spread across the timer interval, preventing a
1419 "thundering herd" at every timer tick.
1421 source kernel/Kconfig.preempt
1425 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1426 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
1427 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1428 default AT91_TIMER_HZ if ARCH_AT91
1429 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1432 config THUMB2_KERNEL
1433 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1434 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1436 select ARM_ASM_UNIFIED
1438 By enabling this option, the kernel will be compiled in
1439 Thumb-2 mode. A compiler/assembler that understand the unified
1440 ARM-Thumb syntax is needed.
1444 config THUMB2_AVOID_R_ARM_THM_JUMP11
1445 bool "Work around buggy Thumb-2 short branch relocations in gas"
1446 depends on THUMB2_KERNEL && MODULES
1449 Various binutils versions can resolve Thumb-2 branches to
1450 locally-defined, preemptible global symbols as short-range "b.n"
1451 branch instructions.
1453 This is a problem, because there's no guarantee the final
1454 destination of the symbol, or any candidate locations for a
1455 trampoline, are within range of the branch. For this reason, the
1456 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1457 relocation in modules at all, and it makes little sense to add
1460 The symptom is that the kernel fails with an "unsupported
1461 relocation" error when loading some modules.
1463 Until fixed tools are available, passing
1464 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1465 code which hits this problem, at the cost of a bit of extra runtime
1466 stack usage in some cases.
1468 The problem is described in more detail at:
1469 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1471 Only Thumb-2 kernels are affected.
1473 Unless you are sure your tools don't have this problem, say Y.
1475 config ARM_ASM_UNIFIED
1479 bool "Use the ARM EABI to compile the kernel"
1481 This option allows for the kernel to be compiled using the latest
1482 ARM ABI (aka EABI). This is only useful if you are using a user
1483 space environment that is also compiled with EABI.
1485 Since there are major incompatibilities between the legacy ABI and
1486 EABI, especially with regard to structure member alignment, this
1487 option also changes the kernel syscall calling convention to
1488 disambiguate both ABIs and allow for backward compatibility support
1489 (selected with CONFIG_OABI_COMPAT).
1491 To use this you need GCC version 4.0.0 or later.
1494 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1495 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1498 This option preserves the old syscall interface along with the
1499 new (ARM EABI) one. It also provides a compatibility layer to
1500 intercept syscalls that have structure arguments which layout
1501 in memory differs between the legacy ABI and the new ARM EABI
1502 (only for non "thumb" binaries). This option adds a tiny
1503 overhead to all syscalls and produces a slightly larger kernel.
1504 If you know you'll be using only pure EABI user space then you
1505 can say N here. If this option is not selected and you attempt
1506 to execute a legacy ABI binary then the result will be
1507 UNPREDICTABLE (in fact it can be predicted that it won't work
1508 at all). If in doubt say Y.
1510 config ARCH_HAS_HOLES_MEMORYMODEL
1513 config ARCH_SPARSEMEM_ENABLE
1516 config ARCH_SPARSEMEM_DEFAULT
1517 def_bool ARCH_SPARSEMEM_ENABLE
1519 config ARCH_SELECT_MEMORY_MODEL
1520 def_bool ARCH_SPARSEMEM_ENABLE
1523 bool "High Memory Support (EXPERIMENTAL)"
1524 depends on MMU && EXPERIMENTAL
1526 The address space of ARM processors is only 4 Gigabytes large
1527 and it has to accommodate user address space, kernel address
1528 space as well as some memory mapped IO. That means that, if you
1529 have a large amount of physical memory and/or IO, not all of the
1530 memory can be "permanently mapped" by the kernel. The physical
1531 memory that is not permanently mapped is called "high memory".
1533 Depending on the selected kernel/user memory split, minimum
1534 vmalloc space and actual amount of RAM, you may not need this
1535 option which should result in a slightly faster kernel.
1540 bool "Allocate 2nd-level pagetables from highmem"
1542 depends on !OUTER_CACHE
1544 config HW_PERF_EVENTS
1545 bool "Enable hardware performance counter support for perf events"
1546 depends on PERF_EVENTS && CPU_HAS_PMU
1549 Enable hardware performance counter support for perf events. If
1550 disabled, perf events will use software events only.
1554 config FORCE_MAX_ZONEORDER
1555 int "Maximum zone order" if ARCH_SHMOBILE
1556 range 11 64 if ARCH_SHMOBILE
1557 default "9" if SA1111
1560 The kernel memory allocator divides physically contiguous memory
1561 blocks into "zones", where each zone is a power of two number of
1562 pages. This option selects the largest power of two that the kernel
1563 keeps in the memory allocator. If you need to allocate very large
1564 blocks of physically contiguous memory, then you may need to
1565 increase this value.
1567 This config option is actually maximum order plus one. For example,
1568 a value of 11 means that the largest free memory block is 2^10 pages.
1571 bool "Timer and CPU usage LEDs"
1572 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1573 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1574 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1575 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1576 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1577 ARCH_AT91 || ARCH_DAVINCI || \
1578 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1580 If you say Y here, the LEDs on your machine will be used
1581 to provide useful information about your current system status.
1583 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1584 be able to select which LEDs are active using the options below. If
1585 you are compiling a kernel for the EBSA-110 or the LART however, the
1586 red LED will simply flash regularly to indicate that the system is
1587 still functional. It is safe to say Y here if you have a CATS
1588 system, but the driver will do nothing.
1591 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1592 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1593 || MACH_OMAP_PERSEUS2
1595 depends on !GENERIC_CLOCKEVENTS
1596 default y if ARCH_EBSA110
1598 If you say Y here, one of the system LEDs (the green one on the
1599 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1600 will flash regularly to indicate that the system is still
1601 operational. This is mainly useful to kernel hackers who are
1602 debugging unstable kernels.
1604 The LART uses the same LED for both Timer LED and CPU usage LED
1605 functions. You may choose to use both, but the Timer LED function
1606 will overrule the CPU usage LED.
1609 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1611 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1612 || MACH_OMAP_PERSEUS2
1615 If you say Y here, the red LED will be used to give a good real
1616 time indication of CPU usage, by lighting whenever the idle task
1617 is not currently executing.
1619 The LART uses the same LED for both Timer LED and CPU usage LED
1620 functions. You may choose to use both, but the Timer LED function
1621 will overrule the CPU usage LED.
1623 config ALIGNMENT_TRAP
1625 depends on CPU_CP15_MMU
1626 default y if !ARCH_EBSA110
1627 select HAVE_PROC_CPU if PROC_FS
1629 ARM processors cannot fetch/store information which is not
1630 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1631 address divisible by 4. On 32-bit ARM processors, these non-aligned
1632 fetch/store instructions will be emulated in software if you say
1633 here, which has a severe performance impact. This is necessary for
1634 correct operation of some network protocols. With an IP-only
1635 configuration it is safe to say N, otherwise say Y.
1637 config UACCESS_WITH_MEMCPY
1638 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1639 depends on MMU && EXPERIMENTAL
1640 default y if CPU_FEROCEON
1642 Implement faster copy_to_user and clear_user methods for CPU
1643 cores where a 8-word STM instruction give significantly higher
1644 memory write throughput than a sequence of individual 32bit stores.
1646 A possible side effect is a slight increase in scheduling latency
1647 between threads sharing the same address space if they invoke
1648 such copy operations with large buffers.
1650 However, if the CPU data cache is using a write-allocate mode,
1651 this option is unlikely to provide any performance gain.
1655 prompt "Enable seccomp to safely compute untrusted bytecode"
1657 This kernel feature is useful for number crunching applications
1658 that may need to compute untrusted bytecode during their
1659 execution. By using pipes or other transports made available to
1660 the process as file descriptors supporting the read/write
1661 syscalls, it's possible to isolate those applications in
1662 their own address space using seccomp. Once seccomp is
1663 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1664 and the task is only allowed to execute a few safe syscalls
1665 defined by each seccomp mode.
1667 config CC_STACKPROTECTOR
1668 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1669 depends on EXPERIMENTAL
1671 This option turns on the -fstack-protector GCC feature. This
1672 feature puts, at the beginning of functions, a canary value on
1673 the stack just before the return address, and validates
1674 the value just before actually returning. Stack based buffer
1675 overflows (that need to overwrite this return address) now also
1676 overwrite the canary, which gets detected and the attack is then
1677 neutralized via a kernel panic.
1678 This feature requires gcc version 4.2 or above.
1680 config DEPRECATED_PARAM_STRUCT
1681 bool "Provide old way to pass kernel parameters"
1683 This was deprecated in 2001 and announced to live on for 5 years.
1684 Some old boot loaders still use this way.
1690 # Compressed boot loader in ROM. Yes, we really want to ask about
1691 # TEXT and BSS so we preserve their values in the config files.
1692 config ZBOOT_ROM_TEXT
1693 hex "Compressed ROM boot loader base address"
1696 The physical address at which the ROM-able zImage is to be
1697 placed in the target. Platforms which normally make use of
1698 ROM-able zImage formats normally set this to a suitable
1699 value in their defconfig file.
1701 If ZBOOT_ROM is not enabled, this has no effect.
1703 config ZBOOT_ROM_BSS
1704 hex "Compressed ROM boot loader BSS address"
1707 The base address of an area of read/write memory in the target
1708 for the ROM-able zImage which must be available while the
1709 decompressor is running. It must be large enough to hold the
1710 entire decompressed kernel plus an additional 128 KiB.
1711 Platforms which normally make use of ROM-able zImage formats
1712 normally set this to a suitable value in their defconfig file.
1714 If ZBOOT_ROM is not enabled, this has no effect.
1717 bool "Compressed boot loader in ROM/flash"
1718 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1720 Say Y here if you intend to execute your compressed kernel image
1721 (zImage) directly from ROM or flash. If unsure, say N.
1723 config ZBOOT_ROM_MMCIF
1724 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1725 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1727 Say Y here to include experimental MMCIF loading code in the
1728 ROM-able zImage. With this enabled it is possible to write the
1729 the ROM-able zImage kernel image to an MMC card and boot the
1730 kernel straight from the reset vector. At reset the processor
1731 Mask ROM will load the first part of the the ROM-able zImage
1732 which in turn loads the rest the kernel image to RAM using the
1733 MMCIF hardware block.
1736 string "Default kernel command string"
1739 On some architectures (EBSA110 and CATS), there is currently no way
1740 for the boot loader to pass arguments to the kernel. For these
1741 architectures, you should supply some command-line options at build
1742 time by entering them here. As a minimum, you should specify the
1743 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1745 config CMDLINE_FORCE
1746 bool "Always use the default kernel command string"
1747 depends on CMDLINE != ""
1749 Always use the default kernel command string, even if the boot
1750 loader passes other arguments to the kernel.
1751 This is useful if you cannot or don't want to change the
1752 command-line options your boot loader passes to the kernel.
1757 bool "Kernel Execute-In-Place from ROM"
1758 depends on !ZBOOT_ROM
1760 Execute-In-Place allows the kernel to run from non-volatile storage
1761 directly addressable by the CPU, such as NOR flash. This saves RAM
1762 space since the text section of the kernel is not loaded from flash
1763 to RAM. Read-write sections, such as the data section and stack,
1764 are still copied to RAM. The XIP kernel is not compressed since
1765 it has to run directly from flash, so it will take more space to
1766 store it. The flash address used to link the kernel object files,
1767 and for storing it, is configuration dependent. Therefore, if you
1768 say Y here, you must know the proper physical address where to
1769 store the kernel image depending on your own flash memory usage.
1771 Also note that the make target becomes "make xipImage" rather than
1772 "make zImage" or "make Image". The final kernel binary to put in
1773 ROM memory will be arch/arm/boot/xipImage.
1777 config XIP_PHYS_ADDR
1778 hex "XIP Kernel Physical Location"
1779 depends on XIP_KERNEL
1780 default "0x00080000"
1782 This is the physical address in your flash memory the kernel will
1783 be linked for and stored to. This address is dependent on your
1787 bool "Kexec system call (EXPERIMENTAL)"
1788 depends on EXPERIMENTAL
1790 kexec is a system call that implements the ability to shutdown your
1791 current kernel, and to start another kernel. It is like a reboot
1792 but it is independent of the system firmware. And like a reboot
1793 you can start any kernel with it, not just Linux.
1795 It is an ongoing process to be certain the hardware in a machine
1796 is properly shutdown, so do not be surprised if this code does not
1797 initially work for you. It may help to enable device hotplugging
1801 bool "Export atags in procfs"
1805 Should the atags used to boot the kernel be exported in an "atags"
1806 file in procfs. Useful with kexec.
1809 bool "Build kdump crash kernel (EXPERIMENTAL)"
1810 depends on EXPERIMENTAL
1812 Generate crash dump after being started by kexec. This should
1813 be normally only set in special crash dump kernels which are
1814 loaded in the main kernel with kexec-tools into a specially
1815 reserved region and then later executed after a crash by
1816 kdump/kexec. The crash dump kernel must be compiled to a
1817 memory address not used by the main kernel
1819 For more details see Documentation/kdump/kdump.txt
1821 config AUTO_ZRELADDR
1822 bool "Auto calculation of the decompressed kernel image address"
1823 depends on !ZBOOT_ROM && !ARCH_U300
1825 ZRELADDR is the physical address where the decompressed kernel
1826 image will be placed. If AUTO_ZRELADDR is selected, the address
1827 will be determined at run-time by masking the current IP with
1828 0xf8000000. This assumes the zImage being placed in the first 128MB
1829 from start of memory.
1833 menu "CPU Power Management"
1837 source "drivers/cpufreq/Kconfig"
1840 tristate "CPUfreq driver for i.MX CPUs"
1841 depends on ARCH_MXC && CPU_FREQ
1843 This enables the CPUfreq driver for i.MX CPUs.
1845 config CPU_FREQ_SA1100
1848 config CPU_FREQ_SA1110
1851 config CPU_FREQ_INTEGRATOR
1852 tristate "CPUfreq driver for ARM Integrator CPUs"
1853 depends on ARCH_INTEGRATOR && CPU_FREQ
1856 This enables the CPUfreq driver for ARM Integrator CPUs.
1858 For details, take a look at <file:Documentation/cpu-freq>.
1864 depends on CPU_FREQ && ARCH_PXA && PXA25x
1866 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1868 config CPU_FREQ_S3C64XX
1869 bool "CPUfreq support for Samsung S3C64XX CPUs"
1870 depends on CPU_FREQ && CPU_S3C6410
1875 Internal configuration node for common cpufreq on Samsung SoC
1877 config CPU_FREQ_S3C24XX
1878 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1879 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1882 This enables the CPUfreq driver for the Samsung S3C24XX family
1885 For details, take a look at <file:Documentation/cpu-freq>.
1889 config CPU_FREQ_S3C24XX_PLL
1890 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1891 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1893 Compile in support for changing the PLL frequency from the
1894 S3C24XX series CPUfreq driver. The PLL takes time to settle
1895 after a frequency change, so by default it is not enabled.
1897 This also means that the PLL tables for the selected CPU(s) will
1898 be built which may increase the size of the kernel image.
1900 config CPU_FREQ_S3C24XX_DEBUG
1901 bool "Debug CPUfreq Samsung driver core"
1902 depends on CPU_FREQ_S3C24XX
1904 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1906 config CPU_FREQ_S3C24XX_IODEBUG
1907 bool "Debug CPUfreq Samsung driver IO timing"
1908 depends on CPU_FREQ_S3C24XX
1910 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1912 config CPU_FREQ_S3C24XX_DEBUGFS
1913 bool "Export debugfs for CPUFreq"
1914 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1916 Export status information via debugfs.
1920 source "drivers/cpuidle/Kconfig"
1924 menu "Floating point emulation"
1926 comment "At least one emulation must be selected"
1929 bool "NWFPE math emulation"
1930 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1932 Say Y to include the NWFPE floating point emulator in the kernel.
1933 This is necessary to run most binaries. Linux does not currently
1934 support floating point hardware so you need to say Y here even if
1935 your machine has an FPA or floating point co-processor podule.
1937 You may say N here if you are going to load the Acorn FPEmulator
1938 early in the bootup.
1941 bool "Support extended precision"
1942 depends on FPE_NWFPE
1944 Say Y to include 80-bit support in the kernel floating-point
1945 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1946 Note that gcc does not generate 80-bit operations by default,
1947 so in most cases this option only enlarges the size of the
1948 floating point emulator without any good reason.
1950 You almost surely want to say N here.
1953 bool "FastFPE math emulation (EXPERIMENTAL)"
1954 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1956 Say Y here to include the FAST floating point emulator in the kernel.
1957 This is an experimental much faster emulator which now also has full
1958 precision for the mantissa. It does not support any exceptions.
1959 It is very simple, and approximately 3-6 times faster than NWFPE.
1961 It should be sufficient for most programs. It may be not suitable
1962 for scientific calculations, but you have to check this for yourself.
1963 If you do not feel you need a faster FP emulation you should better
1967 bool "VFP-format floating point maths"
1968 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1970 Say Y to include VFP support code in the kernel. This is needed
1971 if your hardware includes a VFP unit.
1973 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1974 release notes and additional status information.
1976 Say N if your target does not have VFP hardware.
1984 bool "Advanced SIMD (NEON) Extension support"
1985 depends on VFPv3 && CPU_V7
1987 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1992 menu "Userspace binary formats"
1994 source "fs/Kconfig.binfmt"
1997 tristate "RISC OS personality"
2000 Say Y here to include the kernel code necessary if you want to run
2001 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2002 experimental; if this sounds frightening, say N and sleep in peace.
2003 You can also say M here to compile this support as a module (which
2004 will be called arthur).
2008 menu "Power management options"
2010 source "kernel/power/Kconfig"
2012 config ARCH_SUSPEND_POSSIBLE
2017 source "net/Kconfig"
2019 source "drivers/Kconfig"
2023 source "arch/arm/Kconfig.debug"
2025 source "security/Kconfig"
2027 source "crypto/Kconfig"
2029 source "lib/Kconfig"