4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_GENERIC_SPINLOCK
172 config RWSEM_XCHGADD_ALGORITHM
175 config ARCH_HAS_ILOG2_U32
178 config ARCH_HAS_ILOG2_U64
181 config ARCH_HAS_CPUFREQ
184 Internal node to signify that the ARCH has CPUFREQ support
185 and that the relevant menu configurations are displayed for
188 config ARCH_HAS_BANDGAP
191 config GENERIC_HWEIGHT
195 config GENERIC_CALIBRATE_DELAY
199 config ARCH_MAY_HAVE_PC_FDC
205 config NEED_DMA_MAP_STATE
208 config ARCH_SUPPORTS_UPROBES
211 config ARCH_HAS_DMA_SET_COHERENT_MASK
214 config GENERIC_ISA_DMA
220 config NEED_RET_TO_USER
228 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
229 default DRAM_BASE if REMAP_VECTORS_TO_RAM
232 The base address of exception vectors. This must be two pages
235 config ARM_PATCH_PHYS_VIRT
236 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 depends on !XIP_KERNEL && MMU
239 depends on !ARCH_REALVIEW || !SPARSEMEM
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_GPIO_H
255 Select this when mach/gpio.h is required to provide special
256 definitions for this platform. The need for mach/gpio.h should
257 be avoided when possible.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
276 default DRAM_BASE if !MMU
278 Please provide the physical address corresponding to the
279 location of main memory in your system.
285 source "init/Kconfig"
287 source "kernel/Kconfig.freezer"
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
296 support by paged memory management. If unsure, say 'Y'.
299 # The "ARM system type" choice list is ordered alphabetically by option
300 # text. Please add new entries in the option alphabetic order.
303 prompt "ARM system type"
304 default ARCH_VERSATILE if !MMU
305 default ARCH_MULTIPLATFORM if MMU
307 config ARCH_MULTIPLATFORM
308 bool "Allow multiple platforms to be selected"
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_HAS_SG_CHAIN
312 select ARM_PATCH_PHYS_VIRT
316 select GENERIC_CLOCKEVENTS
317 select MULTI_IRQ_HANDLER
321 config ARCH_INTEGRATOR
322 bool "ARM Ltd. Integrator family"
323 select ARCH_HAS_CPUFREQ
325 select ARM_PATCH_PHYS_VIRT
328 select COMMON_CLK_VERSATILE
329 select GENERIC_CLOCKEVENTS
332 select MULTI_IRQ_HANDLER
333 select NEED_MACH_MEMORY_H
334 select PLAT_VERSATILE
337 select VERSATILE_FPGA_IRQ
339 Support for ARM's Integrator platform.
342 bool "ARM Ltd. RealView family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_TIMER_SP804
347 select COMMON_CLK_VERSATILE
348 select GENERIC_CLOCKEVENTS
349 select GPIO_PL061 if GPIOLIB
351 select NEED_MACH_MEMORY_H
352 select PLAT_VERSATILE
353 select PLAT_VERSATILE_CLCD
355 This enables support for ARM Ltd RealView boards.
357 config ARCH_VERSATILE
358 bool "ARM Ltd. Versatile family"
359 select ARCH_WANT_OPTIONAL_GPIOLIB
361 select ARM_TIMER_SP804
364 select GENERIC_CLOCKEVENTS
365 select HAVE_MACH_CLKDEV
367 select PLAT_VERSATILE
368 select PLAT_VERSATILE_CLCD
369 select PLAT_VERSATILE_CLOCK
370 select VERSATILE_FPGA_IRQ
372 This enables support for ARM Ltd Versatile board.
376 select ARCH_REQUIRE_GPIOLIB
379 select NEED_MACH_GPIO_H
380 select NEED_MACH_IO_H if PCCARD
382 select PINCTRL_AT91 if USE_OF
384 This enables support for systems based on Atmel
385 AT91RM9200 and AT91SAM9* processors.
388 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
389 select ARCH_REQUIRE_GPIOLIB
394 select GENERIC_CLOCKEVENTS
397 Support for Cirrus Logic 711x/721x/731x based boards.
400 bool "Cortina Systems Gemini"
401 select ARCH_REQUIRE_GPIOLIB
404 select GENERIC_CLOCKEVENTS
406 Support for the Cortina Systems Gemini family SoCs
410 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_IO_H
414 select NEED_MACH_MEMORY_H
417 This is an evaluation board for the StrongARM processor available
418 from Digital. It has limited hardware on-board, including an
419 Ethernet interface, two PCMCIA sockets, two serial ports and a
423 bool "Energy Micro efm32"
425 select ARCH_REQUIRE_GPIOLIB
431 select GENERIC_CLOCKEVENTS
437 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
442 select ARCH_HAS_HOLES_MEMORYMODEL
443 select ARCH_REQUIRE_GPIOLIB
444 select ARCH_USES_GETTIMEOFFSET
449 select NEED_MACH_MEMORY_H
451 This enables support for the Cirrus EP93xx series of CPUs.
453 config ARCH_FOOTBRIDGE
457 select GENERIC_CLOCKEVENTS
459 select NEED_MACH_IO_H if !MMU
460 select NEED_MACH_MEMORY_H
462 Support for systems based on the DC21285 companion chip
463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 bool "Hilscher NetX based"
470 select GENERIC_CLOCKEVENTS
472 This enables support for systems based on the Hilscher NetX Soc
478 select NEED_MACH_MEMORY_H
479 select NEED_RET_TO_USER
484 Support for Intel's IOP13XX (XScale) family of processors.
489 select ARCH_REQUIRE_GPIOLIB
492 select NEED_RET_TO_USER
496 Support for Intel's 80219 and IOP32X (XScale) family of
502 select ARCH_REQUIRE_GPIOLIB
505 select NEED_RET_TO_USER
509 Support for Intel's IOP33X (XScale) family of processors.
514 select ARCH_HAS_DMA_SET_COHERENT_MASK
515 select ARCH_REQUIRE_GPIOLIB
516 select ARCH_SUPPORTS_BIG_ENDIAN
519 select DMABOUNCE if PCI
520 select GENERIC_CLOCKEVENTS
521 select MIGHT_HAVE_PCI
522 select NEED_MACH_IO_H
523 select USB_EHCI_BIG_ENDIAN_DESC
524 select USB_EHCI_BIG_ENDIAN_MMIO
526 Support for Intel's IXP4XX (XScale) family of processors.
530 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
533 select MIGHT_HAVE_PCI
537 select PLAT_ORION_LEGACY
539 Support for the Marvell Dove SoC 88AP510
542 bool "Marvell Kirkwood"
543 select ARCH_HAS_CPUFREQ
544 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
551 select PINCTRL_KIRKWOOD
552 select PLAT_ORION_LEGACY
554 Support for the following Marvell Kirkwood series SoCs:
555 88F6180, 88F6192 and 88F6281.
558 bool "Marvell MV78xx0"
559 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_CLOCKEVENTS
564 select PLAT_ORION_LEGACY
566 Support for the following Marvell MV78xx0 series SoCs:
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
577 select PLAT_ORION_LEGACY
579 Support for the following Marvell Orion 5x series SoCs:
580 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
581 Orion-2 (5281), Orion-1-90 (6183).
584 bool "Marvell PXA168/910/MMP2"
586 select ARCH_REQUIRE_GPIOLIB
588 select GENERIC_ALLOCATOR
589 select GENERIC_CLOCKEVENTS
592 select MULTI_IRQ_HANDLER
597 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
600 bool "Micrel/Kendin KS8695"
601 select ARCH_REQUIRE_GPIOLIB
604 select GENERIC_CLOCKEVENTS
605 select NEED_MACH_MEMORY_H
607 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
608 System-on-Chip devices.
611 bool "Nuvoton W90X900 CPU"
612 select ARCH_REQUIRE_GPIOLIB
616 select GENERIC_CLOCKEVENTS
618 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
619 At present, the w90x900 has been renamed nuc900, regarding
620 the ARM series product line, you can login the following
621 link address to know more.
623 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
624 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
628 select ARCH_REQUIRE_GPIOLIB
633 select GENERIC_CLOCKEVENTS
637 Support for the NXP LPC32XX family of processors
640 bool "PXA2xx/PXA3xx-based"
642 select ARCH_HAS_CPUFREQ
644 select ARCH_REQUIRE_GPIOLIB
645 select ARM_CPU_SUSPEND if PM
649 select GENERIC_CLOCKEVENTS
652 select MULTI_IRQ_HANDLER
656 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
659 bool "Qualcomm MSM (non-multiplatform)"
660 select ARCH_REQUIRE_GPIOLIB
662 select GENERIC_CLOCKEVENTS
664 Support for Qualcomm MSM/QSD based systems. This runs on the
665 apps processor of the MSM/QSD and depends on a shared memory
666 interface to the modem processor which runs the baseband
667 stack and controls some vital subsystems
668 (clock and power control, etc).
670 config ARCH_SHMOBILE_LEGACY
671 bool "Renesas ARM SoCs (non-multiplatform)"
673 select ARM_PATCH_PHYS_VIRT
675 select GENERIC_CLOCKEVENTS
676 select HAVE_ARM_SCU if SMP
677 select HAVE_ARM_TWD if SMP
678 select HAVE_MACH_CLKDEV
680 select MIGHT_HAVE_CACHE_L2X0
681 select MULTI_IRQ_HANDLER
684 select PM_GENERIC_DOMAINS if PM
687 Support for Renesas ARM SoC platforms using a non-multiplatform
688 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
694 select ARCH_MAY_HAVE_PC_FDC
695 select ARCH_SPARSEMEM_ENABLE
696 select ARCH_USES_GETTIMEOFFSET
700 select HAVE_PATA_PLATFORM
702 select NEED_MACH_IO_H
703 select NEED_MACH_MEMORY_H
707 On the Acorn Risc-PC, Linux can support the internal IDE disk and
708 CD-ROM interface, serial and parallel port, and the floppy drive.
712 select ARCH_HAS_CPUFREQ
714 select ARCH_REQUIRE_GPIOLIB
715 select ARCH_SPARSEMEM_ENABLE
720 select GENERIC_CLOCKEVENTS
723 select NEED_MACH_MEMORY_H
726 Support for StrongARM 11x0 based boards.
729 bool "Samsung S3C24XX SoCs"
730 select ARCH_HAS_CPUFREQ
731 select ARCH_REQUIRE_GPIOLIB
734 select CLKSRC_SAMSUNG_PWM
735 select GENERIC_CLOCKEVENTS
737 select HAVE_S3C2410_I2C if I2C
738 select HAVE_S3C2410_WATCHDOG if WATCHDOG
739 select HAVE_S3C_RTC if RTC_CLASS
740 select MULTI_IRQ_HANDLER
741 select NEED_MACH_IO_H
744 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
745 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
746 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
747 Samsung SMDK2410 development board (and derivatives).
750 bool "Samsung S3C64XX"
751 select ARCH_HAS_CPUFREQ
752 select ARCH_REQUIRE_GPIOLIB
757 select CLKSRC_SAMSUNG_PWM
760 select GENERIC_CLOCKEVENTS
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
767 select PM_GENERIC_DOMAINS if PM
769 select S3C_GPIO_TRACK
771 select SAMSUNG_WAKEMASK
772 select SAMSUNG_WDT_RESET
774 Samsung S3C64XX series based systems
777 bool "Samsung S5P6440 S5P6450"
780 select CLKSRC_SAMSUNG_PWM
782 select GENERIC_CLOCKEVENTS
784 select HAVE_S3C2410_I2C if I2C
785 select HAVE_S3C2410_WATCHDOG if WATCHDOG
786 select HAVE_S3C_RTC if RTC_CLASS
787 select NEED_MACH_GPIO_H
789 select SAMSUNG_WDT_RESET
791 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
795 bool "Samsung S5PC100"
796 select ARCH_REQUIRE_GPIOLIB
799 select CLKSRC_SAMSUNG_PWM
801 select GENERIC_CLOCKEVENTS
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 select HAVE_S3C_RTC if RTC_CLASS
806 select NEED_MACH_GPIO_H
808 select SAMSUNG_WDT_RESET
810 Samsung S5PC100 series based systems
813 bool "Samsung S5PV210/S5PC110"
814 select ARCH_HAS_CPUFREQ
815 select ARCH_HAS_HOLES_MEMORYMODEL
816 select ARCH_SPARSEMEM_ENABLE
819 select CLKSRC_SAMSUNG_PWM
821 select GENERIC_CLOCKEVENTS
823 select HAVE_S3C2410_I2C if I2C
824 select HAVE_S3C2410_WATCHDOG if WATCHDOG
825 select HAVE_S3C_RTC if RTC_CLASS
826 select NEED_MACH_GPIO_H
827 select NEED_MACH_MEMORY_H
830 Samsung S5PV210/S5PC110 series based systems
833 bool "Samsung EXYNOS"
834 select ARCH_HAS_CPUFREQ
835 select ARCH_HAS_HOLES_MEMORYMODEL
836 select ARCH_REQUIRE_GPIOLIB
837 select ARCH_SPARSEMEM_ENABLE
841 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select HAVE_S3C_RTC if RTC_CLASS
845 select NEED_MACH_MEMORY_H
849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
853 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_REQUIRE_GPIOLIB
856 select GENERIC_ALLOCATOR
857 select GENERIC_CLOCKEVENTS
858 select GENERIC_IRQ_CHIP
864 Support for TI's DaVinci platform.
869 select ARCH_HAS_CPUFREQ
870 select ARCH_HAS_HOLES_MEMORYMODEL
872 select ARCH_REQUIRE_GPIOLIB
875 select GENERIC_CLOCKEVENTS
876 select GENERIC_IRQ_CHIP
879 select NEED_MACH_IO_H if PCCARD
880 select NEED_MACH_MEMORY_H
882 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
886 menu "Multiple platform selection"
887 depends on ARCH_MULTIPLATFORM
889 comment "CPU Core family selection"
892 bool "ARMv4 based platforms (FA526)"
893 depends on !ARCH_MULTI_V6_V7
894 select ARCH_MULTI_V4_V5
897 config ARCH_MULTI_V4T
898 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
899 depends on !ARCH_MULTI_V6_V7
900 select ARCH_MULTI_V4_V5
901 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
902 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
903 CPU_ARM925T || CPU_ARM940T)
906 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
907 depends on !ARCH_MULTI_V6_V7
908 select ARCH_MULTI_V4_V5
909 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
910 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
911 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
913 config ARCH_MULTI_V4_V5
917 bool "ARMv6 based platforms (ARM11)"
918 select ARCH_MULTI_V6_V7
922 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
924 select ARCH_MULTI_V6_V7
928 config ARCH_MULTI_V6_V7
930 select MIGHT_HAVE_CACHE_L2X0
932 config ARCH_MULTI_CPU_AUTO
933 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
939 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
943 select HAVE_ARM_ARCH_TIMER
946 # This is sorted alphabetically by mach-* pathname. However, plat-*
947 # Kconfigs may be included either alphabetically (according to the
948 # plat- suffix) or along side the corresponding mach-* source.
950 source "arch/arm/mach-mvebu/Kconfig"
952 source "arch/arm/mach-at91/Kconfig"
954 source "arch/arm/mach-bcm/Kconfig"
956 source "arch/arm/mach-berlin/Kconfig"
958 source "arch/arm/mach-clps711x/Kconfig"
960 source "arch/arm/mach-cns3xxx/Kconfig"
962 source "arch/arm/mach-davinci/Kconfig"
964 source "arch/arm/mach-dove/Kconfig"
966 source "arch/arm/mach-ep93xx/Kconfig"
968 source "arch/arm/mach-footbridge/Kconfig"
970 source "arch/arm/mach-gemini/Kconfig"
972 source "arch/arm/mach-highbank/Kconfig"
974 source "arch/arm/mach-hisi/Kconfig"
976 source "arch/arm/mach-integrator/Kconfig"
978 source "arch/arm/mach-iop32x/Kconfig"
980 source "arch/arm/mach-iop33x/Kconfig"
982 source "arch/arm/mach-iop13xx/Kconfig"
984 source "arch/arm/mach-ixp4xx/Kconfig"
986 source "arch/arm/mach-keystone/Kconfig"
988 source "arch/arm/mach-kirkwood/Kconfig"
990 source "arch/arm/mach-ks8695/Kconfig"
992 source "arch/arm/mach-msm/Kconfig"
994 source "arch/arm/mach-moxart/Kconfig"
996 source "arch/arm/mach-mv78xx0/Kconfig"
998 source "arch/arm/mach-imx/Kconfig"
1000 source "arch/arm/mach-mxs/Kconfig"
1002 source "arch/arm/mach-netx/Kconfig"
1004 source "arch/arm/mach-nomadik/Kconfig"
1006 source "arch/arm/mach-nspire/Kconfig"
1008 source "arch/arm/plat-omap/Kconfig"
1010 source "arch/arm/mach-omap1/Kconfig"
1012 source "arch/arm/mach-omap2/Kconfig"
1014 source "arch/arm/mach-orion5x/Kconfig"
1016 source "arch/arm/mach-picoxcell/Kconfig"
1018 source "arch/arm/mach-pxa/Kconfig"
1019 source "arch/arm/plat-pxa/Kconfig"
1021 source "arch/arm/mach-mmp/Kconfig"
1023 source "arch/arm/mach-qcom/Kconfig"
1025 source "arch/arm/mach-realview/Kconfig"
1027 source "arch/arm/mach-rockchip/Kconfig"
1029 source "arch/arm/mach-sa1100/Kconfig"
1031 source "arch/arm/plat-samsung/Kconfig"
1033 source "arch/arm/mach-socfpga/Kconfig"
1035 source "arch/arm/mach-spear/Kconfig"
1037 source "arch/arm/mach-sti/Kconfig"
1039 source "arch/arm/mach-s3c24xx/Kconfig"
1041 source "arch/arm/mach-s3c64xx/Kconfig"
1043 source "arch/arm/mach-s5p64x0/Kconfig"
1045 source "arch/arm/mach-s5pc100/Kconfig"
1047 source "arch/arm/mach-s5pv210/Kconfig"
1049 source "arch/arm/mach-exynos/Kconfig"
1051 source "arch/arm/mach-shmobile/Kconfig"
1053 source "arch/arm/mach-sunxi/Kconfig"
1055 source "arch/arm/mach-prima2/Kconfig"
1057 source "arch/arm/mach-tegra/Kconfig"
1059 source "arch/arm/mach-u300/Kconfig"
1061 source "arch/arm/mach-ux500/Kconfig"
1063 source "arch/arm/mach-versatile/Kconfig"
1065 source "arch/arm/mach-vexpress/Kconfig"
1066 source "arch/arm/plat-versatile/Kconfig"
1068 source "arch/arm/mach-vt8500/Kconfig"
1070 source "arch/arm/mach-w90x900/Kconfig"
1072 source "arch/arm/mach-zynq/Kconfig"
1074 # Definitions to make life easier
1080 select GENERIC_CLOCKEVENTS
1086 select GENERIC_IRQ_CHIP
1089 config PLAT_ORION_LEGACY
1096 config PLAT_VERSATILE
1099 config ARM_TIMER_SP804
1102 select CLKSRC_OF if OF
1104 source "arch/arm/firmware/Kconfig"
1106 source arch/arm/mm/Kconfig
1110 default 16 if ARCH_EP93XX
1114 bool "Enable iWMMXt support"
1115 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1116 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1118 Enable support for iWMMXt context switching at run time if
1119 running on a CPU that supports it.
1121 config MULTI_IRQ_HANDLER
1124 Allow each machine to specify it's own IRQ handler at run time.
1127 source "arch/arm/Kconfig-nommu"
1130 config PJ4B_ERRATA_4742
1131 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1132 depends on CPU_PJ4B && MACH_ARMADA_370
1135 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1136 Event (WFE) IDLE states, a specific timing sensitivity exists between
1137 the retiring WFI/WFE instructions and the newly issued subsequent
1138 instructions. This sensitivity can result in a CPU hang scenario.
1140 The software must insert either a Data Synchronization Barrier (DSB)
1141 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1144 config ARM_ERRATA_326103
1145 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1148 Executing a SWP instruction to read-only memory does not set bit 11
1149 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1150 treat the access as a read, preventing a COW from occurring and
1151 causing the faulting task to livelock.
1153 config ARM_ERRATA_411920
1154 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1155 depends on CPU_V6 || CPU_V6K
1157 Invalidation of the Instruction Cache operation can
1158 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1159 It does not affect the MPCore. This option enables the ARM Ltd.
1160 recommended workaround.
1162 config ARM_ERRATA_430973
1163 bool "ARM errata: Stale prediction on replaced interworking branch"
1166 This option enables the workaround for the 430973 Cortex-A8
1167 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1168 interworking branch is replaced with another code sequence at the
1169 same virtual address, whether due to self-modifying code or virtual
1170 to physical address re-mapping, Cortex-A8 does not recover from the
1171 stale interworking branch prediction. This results in Cortex-A8
1172 executing the new code sequence in the incorrect ARM or Thumb state.
1173 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1174 and also flushes the branch target cache at every context switch.
1175 Note that setting specific bits in the ACTLR register may not be
1176 available in non-secure mode.
1178 config ARM_ERRATA_458693
1179 bool "ARM errata: Processor deadlock when a false hazard is created"
1181 depends on !ARCH_MULTIPLATFORM
1183 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1184 erratum. For very specific sequences of memory operations, it is
1185 possible for a hazard condition intended for a cache line to instead
1186 be incorrectly associated with a different cache line. This false
1187 hazard might then cause a processor deadlock. The workaround enables
1188 the L1 caching of the NEON accesses and disables the PLD instruction
1189 in the ACTLR register. Note that setting specific bits in the ACTLR
1190 register may not be available in non-secure mode.
1192 config ARM_ERRATA_460075
1193 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1195 depends on !ARCH_MULTIPLATFORM
1197 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1198 erratum. Any asynchronous access to the L2 cache may encounter a
1199 situation in which recent store transactions to the L2 cache are lost
1200 and overwritten with stale memory contents from external memory. The
1201 workaround disables the write-allocate mode for the L2 cache via the
1202 ACTLR register. Note that setting specific bits in the ACTLR register
1203 may not be available in non-secure mode.
1205 config ARM_ERRATA_742230
1206 bool "ARM errata: DMB operation may be faulty"
1207 depends on CPU_V7 && SMP
1208 depends on !ARCH_MULTIPLATFORM
1210 This option enables the workaround for the 742230 Cortex-A9
1211 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1212 between two write operations may not ensure the correct visibility
1213 ordering of the two writes. This workaround sets a specific bit in
1214 the diagnostic register of the Cortex-A9 which causes the DMB
1215 instruction to behave as a DSB, ensuring the correct behaviour of
1218 config ARM_ERRATA_742231
1219 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1220 depends on CPU_V7 && SMP
1221 depends on !ARCH_MULTIPLATFORM
1223 This option enables the workaround for the 742231 Cortex-A9
1224 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1225 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1226 accessing some data located in the same cache line, may get corrupted
1227 data due to bad handling of the address hazard when the line gets
1228 replaced from one of the CPUs at the same time as another CPU is
1229 accessing it. This workaround sets specific bits in the diagnostic
1230 register of the Cortex-A9 which reduces the linefill issuing
1231 capabilities of the processor.
1233 config PL310_ERRATA_588369
1234 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1235 depends on CACHE_L2X0
1237 The PL310 L2 cache controller implements three types of Clean &
1238 Invalidate maintenance operations: by Physical Address
1239 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1240 They are architecturally defined to behave as the execution of a
1241 clean operation followed immediately by an invalidate operation,
1242 both performing to the same memory location. This functionality
1243 is not correctly implemented in PL310 as clean lines are not
1244 invalidated as a result of these operations.
1246 config ARM_ERRATA_643719
1247 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1248 depends on CPU_V7 && SMP
1250 This option enables the workaround for the 643719 Cortex-A9 (prior to
1251 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1252 register returns zero when it should return one. The workaround
1253 corrects this value, ensuring cache maintenance operations which use
1254 it behave as intended and avoiding data corruption.
1256 config ARM_ERRATA_720789
1257 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1260 This option enables the workaround for the 720789 Cortex-A9 (prior to
1261 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1262 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1263 As a consequence of this erratum, some TLB entries which should be
1264 invalidated are not, resulting in an incoherency in the system page
1265 tables. The workaround changes the TLB flushing routines to invalidate
1266 entries regardless of the ASID.
1268 config PL310_ERRATA_727915
1269 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1270 depends on CACHE_L2X0
1272 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1273 operation (offset 0x7FC). This operation runs in background so that
1274 PL310 can handle normal accesses while it is in progress. Under very
1275 rare circumstances, due to this erratum, write data can be lost when
1276 PL310 treats a cacheable write transaction during a Clean &
1277 Invalidate by Way operation.
1279 config ARM_ERRATA_743622
1280 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1282 depends on !ARCH_MULTIPLATFORM
1284 This option enables the workaround for the 743622 Cortex-A9
1285 (r2p*) erratum. Under very rare conditions, a faulty
1286 optimisation in the Cortex-A9 Store Buffer may lead to data
1287 corruption. This workaround sets a specific bit in the diagnostic
1288 register of the Cortex-A9 which disables the Store Buffer
1289 optimisation, preventing the defect from occurring. This has no
1290 visible impact on the overall performance or power consumption of the
1293 config ARM_ERRATA_751472
1294 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1296 depends on !ARCH_MULTIPLATFORM
1298 This option enables the workaround for the 751472 Cortex-A9 (prior
1299 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1300 completion of a following broadcasted operation if the second
1301 operation is received by a CPU before the ICIALLUIS has completed,
1302 potentially leading to corrupted entries in the cache or TLB.
1304 config PL310_ERRATA_753970
1305 bool "PL310 errata: cache sync operation may be faulty"
1306 depends on CACHE_PL310
1308 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1310 Under some condition the effect of cache sync operation on
1311 the store buffer still remains when the operation completes.
1312 This means that the store buffer is always asked to drain and
1313 this prevents it from merging any further writes. The workaround
1314 is to replace the normal offset of cache sync operation (0x730)
1315 by another offset targeting an unmapped PL310 register 0x740.
1316 This has the same effect as the cache sync operation: store buffer
1317 drain and waiting for all buffers empty.
1319 config ARM_ERRATA_754322
1320 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1323 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1324 r3p*) erratum. A speculative memory access may cause a page table walk
1325 which starts prior to an ASID switch but completes afterwards. This
1326 can populate the micro-TLB with a stale entry which may be hit with
1327 the new ASID. This workaround places two dsb instructions in the mm
1328 switching code so that no page table walks can cross the ASID switch.
1330 config ARM_ERRATA_754327
1331 bool "ARM errata: no automatic Store Buffer drain"
1332 depends on CPU_V7 && SMP
1334 This option enables the workaround for the 754327 Cortex-A9 (prior to
1335 r2p0) erratum. The Store Buffer does not have any automatic draining
1336 mechanism and therefore a livelock may occur if an external agent
1337 continuously polls a memory location waiting to observe an update.
1338 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1339 written polling loops from denying visibility of updates to memory.
1341 config ARM_ERRATA_364296
1342 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1345 This options enables the workaround for the 364296 ARM1136
1346 r0p2 erratum (possible cache data corruption with
1347 hit-under-miss enabled). It sets the undocumented bit 31 in
1348 the auxiliary control register and the FI bit in the control
1349 register, thus disabling hit-under-miss without putting the
1350 processor into full low interrupt latency mode. ARM11MPCore
1353 config ARM_ERRATA_764369
1354 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1355 depends on CPU_V7 && SMP
1357 This option enables the workaround for erratum 764369
1358 affecting Cortex-A9 MPCore with two or more processors (all
1359 current revisions). Under certain timing circumstances, a data
1360 cache line maintenance operation by MVA targeting an Inner
1361 Shareable memory region may fail to proceed up to either the
1362 Point of Coherency or to the Point of Unification of the
1363 system. This workaround adds a DSB instruction before the
1364 relevant cache maintenance functions and sets a specific bit
1365 in the diagnostic control register of the SCU.
1367 config PL310_ERRATA_769419
1368 bool "PL310 errata: no automatic Store Buffer drain"
1369 depends on CACHE_L2X0
1371 On revisions of the PL310 prior to r3p2, the Store Buffer does
1372 not automatically drain. This can cause normal, non-cacheable
1373 writes to be retained when the memory system is idle, leading
1374 to suboptimal I/O performance for drivers using coherent DMA.
1375 This option adds a write barrier to the cpu_idle loop so that,
1376 on systems with an outer cache, the store buffer is drained
1379 config ARM_ERRATA_775420
1380 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1383 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1384 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1385 operation aborts with MMU exception, it might cause the processor
1386 to deadlock. This workaround puts DSB before executing ISB if
1387 an abort may occur on cache maintenance.
1389 config ARM_ERRATA_798181
1390 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1391 depends on CPU_V7 && SMP
1393 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1394 adequately shooting down all use of the old entries. This
1395 option enables the Linux kernel workaround for this erratum
1396 which sends an IPI to the CPUs that are running the same ASID
1397 as the one being invalidated.
1399 config ARM_ERRATA_773022
1400 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1403 This option enables the workaround for the 773022 Cortex-A15
1404 (up to r0p4) erratum. In certain rare sequences of code, the
1405 loop buffer may deliver incorrect instructions. This
1406 workaround disables the loop buffer to avoid the erratum.
1410 source "arch/arm/common/Kconfig"
1420 Find out whether you have ISA slots on your motherboard. ISA is the
1421 name of a bus system, i.e. the way the CPU talks to the other stuff
1422 inside your box. Other bus systems are PCI, EISA, MicroChannel
1423 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1424 newer boards don't support it. If you have ISA, say Y, otherwise N.
1426 # Select ISA DMA controller support
1431 # Select ISA DMA interface
1436 bool "PCI support" if MIGHT_HAVE_PCI
1438 Find out whether you have a PCI motherboard. PCI is the name of a
1439 bus system, i.e. the way the CPU talks to the other stuff inside
1440 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1441 VESA. If you have PCI, say Y, otherwise N.
1447 config PCI_NANOENGINE
1448 bool "BSE nanoEngine PCI support"
1449 depends on SA1100_NANOENGINE
1451 Enable PCI on the BSE nanoEngine board.
1456 config PCI_HOST_ITE8152
1458 depends on PCI && MACH_ARMCORE
1462 source "drivers/pci/Kconfig"
1463 source "drivers/pci/pcie/Kconfig"
1465 source "drivers/pcmcia/Kconfig"
1469 menu "Kernel Features"
1474 This option should be selected by machines which have an SMP-
1477 The only effect of this option is to make the SMP-related
1478 options available to the user for configuration.
1481 bool "Symmetric Multi-Processing"
1482 depends on CPU_V6K || CPU_V7
1483 depends on GENERIC_CLOCKEVENTS
1485 depends on MMU || ARM_MPU
1487 This enables support for systems with more than one CPU. If you have
1488 a system with only one CPU, say N. If you have a system with more
1489 than one CPU, say Y.
1491 If you say N here, the kernel will run on uni- and multiprocessor
1492 machines, but will use only one CPU of a multiprocessor machine. If
1493 you say Y here, the kernel will run on many, but not all,
1494 uniprocessor machines. On a uniprocessor machine, the kernel
1495 will run faster if you say N here.
1497 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1498 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1499 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1501 If you don't know what to do here, say N.
1504 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1505 depends on SMP && !XIP_KERNEL && MMU
1508 SMP kernels contain instructions which fail on non-SMP processors.
1509 Enabling this option allows the kernel to modify itself to make
1510 these instructions safe. Disabling it allows about 1K of space
1513 If you don't know what to do here, say Y.
1515 config ARM_CPU_TOPOLOGY
1516 bool "Support cpu topology definition"
1517 depends on SMP && CPU_V7
1520 Support ARM cpu topology definition. The MPIDR register defines
1521 affinity between processors which is then used to describe the cpu
1522 topology of an ARM System.
1525 bool "Multi-core scheduler support"
1526 depends on ARM_CPU_TOPOLOGY
1528 Multi-core scheduler support improves the CPU scheduler's decision
1529 making when dealing with multi-core CPU chips at a cost of slightly
1530 increased overhead in some places. If unsure say N here.
1533 bool "SMT scheduler support"
1534 depends on ARM_CPU_TOPOLOGY
1536 Improves the CPU scheduler's decision making when dealing with
1537 MultiThreading at a cost of slightly increased overhead in some
1538 places. If unsure say N here.
1543 This option enables support for the ARM system coherency unit
1545 config HAVE_ARM_ARCH_TIMER
1546 bool "Architected timer support"
1548 select ARM_ARCH_TIMER
1549 select GENERIC_CLOCKEVENTS
1551 This option enables support for the ARM architected timer
1556 select CLKSRC_OF if OF
1558 This options enables support for the ARM timer and watchdog unit
1561 bool "Multi-Cluster Power Management"
1562 depends on CPU_V7 && SMP
1564 This option provides the common power management infrastructure
1565 for (multi-)cluster based systems, such as big.LITTLE based
1569 bool "big.LITTLE support (Experimental)"
1570 depends on CPU_V7 && SMP
1573 This option enables support selections for the big.LITTLE
1574 system architecture.
1577 bool "big.LITTLE switcher support"
1578 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1579 select ARM_CPU_SUSPEND
1582 The big.LITTLE "switcher" provides the core functionality to
1583 transparently handle transition between a cluster of A15's
1584 and a cluster of A7's in a big.LITTLE system.
1586 config BL_SWITCHER_DUMMY_IF
1587 tristate "Simple big.LITTLE switcher user interface"
1588 depends on BL_SWITCHER && DEBUG_KERNEL
1590 This is a simple and dummy char dev interface to control
1591 the big.LITTLE switcher core code. It is meant for
1592 debugging purposes only.
1595 prompt "Memory split"
1599 Select the desired split between kernel and user memory.
1601 If you are not absolutely sure what you are doing, leave this
1605 bool "3G/1G user/kernel split"
1607 bool "2G/2G user/kernel split"
1609 bool "1G/3G user/kernel split"
1614 default PHYS_OFFSET if !MMU
1615 default 0x40000000 if VMSPLIT_1G
1616 default 0x80000000 if VMSPLIT_2G
1620 int "Maximum number of CPUs (2-32)"
1626 bool "Support for hot-pluggable CPUs"
1629 Say Y here to experiment with turning CPUs off and on. CPUs
1630 can be controlled through /sys/devices/system/cpu.
1633 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1636 Say Y here if you want Linux to communicate with system firmware
1637 implementing the PSCI specification for CPU-centric power
1638 management operations described in ARM document number ARM DEN
1639 0022A ("Power State Coordination Interface System Software on
1642 # The GPIO number here must be sorted by descending number. In case of
1643 # a multiplatform kernel, we just want the highest value required by the
1644 # selected platforms.
1647 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1648 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1649 default 392 if ARCH_U8500
1650 default 352 if ARCH_VT8500
1651 default 288 if ARCH_SUNXI
1652 default 264 if MACH_H4700
1655 Maximum number of GPIOs in the system.
1657 If unsure, leave the default value.
1659 source kernel/Kconfig.preempt
1663 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1664 ARCH_S5PV210 || ARCH_EXYNOS4
1665 default AT91_TIMER_HZ if ARCH_AT91
1666 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1670 depends on HZ_FIXED = 0
1671 prompt "Timer frequency"
1695 default HZ_FIXED if HZ_FIXED != 0
1696 default 100 if HZ_100
1697 default 200 if HZ_200
1698 default 250 if HZ_250
1699 default 300 if HZ_300
1700 default 500 if HZ_500
1704 def_bool HIGH_RES_TIMERS
1706 config THUMB2_KERNEL
1707 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1708 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1709 default y if CPU_THUMBONLY
1711 select ARM_ASM_UNIFIED
1714 By enabling this option, the kernel will be compiled in
1715 Thumb-2 mode. A compiler/assembler that understand the unified
1716 ARM-Thumb syntax is needed.
1720 config THUMB2_AVOID_R_ARM_THM_JUMP11
1721 bool "Work around buggy Thumb-2 short branch relocations in gas"
1722 depends on THUMB2_KERNEL && MODULES
1725 Various binutils versions can resolve Thumb-2 branches to
1726 locally-defined, preemptible global symbols as short-range "b.n"
1727 branch instructions.
1729 This is a problem, because there's no guarantee the final
1730 destination of the symbol, or any candidate locations for a
1731 trampoline, are within range of the branch. For this reason, the
1732 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1733 relocation in modules at all, and it makes little sense to add
1736 The symptom is that the kernel fails with an "unsupported
1737 relocation" error when loading some modules.
1739 Until fixed tools are available, passing
1740 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1741 code which hits this problem, at the cost of a bit of extra runtime
1742 stack usage in some cases.
1744 The problem is described in more detail at:
1745 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1747 Only Thumb-2 kernels are affected.
1749 Unless you are sure your tools don't have this problem, say Y.
1751 config ARM_ASM_UNIFIED
1755 bool "Use the ARM EABI to compile the kernel"
1757 This option allows for the kernel to be compiled using the latest
1758 ARM ABI (aka EABI). This is only useful if you are using a user
1759 space environment that is also compiled with EABI.
1761 Since there are major incompatibilities between the legacy ABI and
1762 EABI, especially with regard to structure member alignment, this
1763 option also changes the kernel syscall calling convention to
1764 disambiguate both ABIs and allow for backward compatibility support
1765 (selected with CONFIG_OABI_COMPAT).
1767 To use this you need GCC version 4.0.0 or later.
1770 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1771 depends on AEABI && !THUMB2_KERNEL
1773 This option preserves the old syscall interface along with the
1774 new (ARM EABI) one. It also provides a compatibility layer to
1775 intercept syscalls that have structure arguments which layout
1776 in memory differs between the legacy ABI and the new ARM EABI
1777 (only for non "thumb" binaries). This option adds a tiny
1778 overhead to all syscalls and produces a slightly larger kernel.
1780 The seccomp filter system will not be available when this is
1781 selected, since there is no way yet to sensibly distinguish
1782 between calling conventions during filtering.
1784 If you know you'll be using only pure EABI user space then you
1785 can say N here. If this option is not selected and you attempt
1786 to execute a legacy ABI binary then the result will be
1787 UNPREDICTABLE (in fact it can be predicted that it won't work
1788 at all). If in doubt say N.
1790 config ARCH_HAS_HOLES_MEMORYMODEL
1793 config ARCH_SPARSEMEM_ENABLE
1796 config ARCH_SPARSEMEM_DEFAULT
1797 def_bool ARCH_SPARSEMEM_ENABLE
1799 config ARCH_SELECT_MEMORY_MODEL
1800 def_bool ARCH_SPARSEMEM_ENABLE
1802 config HAVE_ARCH_PFN_VALID
1803 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1806 bool "High Memory Support"
1809 The address space of ARM processors is only 4 Gigabytes large
1810 and it has to accommodate user address space, kernel address
1811 space as well as some memory mapped IO. That means that, if you
1812 have a large amount of physical memory and/or IO, not all of the
1813 memory can be "permanently mapped" by the kernel. The physical
1814 memory that is not permanently mapped is called "high memory".
1816 Depending on the selected kernel/user memory split, minimum
1817 vmalloc space and actual amount of RAM, you may not need this
1818 option which should result in a slightly faster kernel.
1823 bool "Allocate 2nd-level pagetables from highmem"
1826 config HW_PERF_EVENTS
1827 bool "Enable hardware performance counter support for perf events"
1828 depends on PERF_EVENTS
1831 Enable hardware performance counter support for perf events. If
1832 disabled, perf events will use software events only.
1834 config SYS_SUPPORTS_HUGETLBFS
1838 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1842 config ARCH_WANT_GENERAL_HUGETLB
1847 config FORCE_MAX_ZONEORDER
1848 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1849 range 11 64 if ARCH_SHMOBILE_LEGACY
1850 default "12" if SOC_AM33XX
1851 default "9" if SA1111 || ARCH_EFM32
1854 The kernel memory allocator divides physically contiguous memory
1855 blocks into "zones", where each zone is a power of two number of
1856 pages. This option selects the largest power of two that the kernel
1857 keeps in the memory allocator. If you need to allocate very large
1858 blocks of physically contiguous memory, then you may need to
1859 increase this value.
1861 This config option is actually maximum order plus one. For example,
1862 a value of 11 means that the largest free memory block is 2^10 pages.
1864 config ALIGNMENT_TRAP
1866 depends on CPU_CP15_MMU
1867 default y if !ARCH_EBSA110
1868 select HAVE_PROC_CPU if PROC_FS
1870 ARM processors cannot fetch/store information which is not
1871 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1872 address divisible by 4. On 32-bit ARM processors, these non-aligned
1873 fetch/store instructions will be emulated in software if you say
1874 here, which has a severe performance impact. This is necessary for
1875 correct operation of some network protocols. With an IP-only
1876 configuration it is safe to say N, otherwise say Y.
1878 config UACCESS_WITH_MEMCPY
1879 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1881 default y if CPU_FEROCEON
1883 Implement faster copy_to_user and clear_user methods for CPU
1884 cores where a 8-word STM instruction give significantly higher
1885 memory write throughput than a sequence of individual 32bit stores.
1887 A possible side effect is a slight increase in scheduling latency
1888 between threads sharing the same address space if they invoke
1889 such copy operations with large buffers.
1891 However, if the CPU data cache is using a write-allocate mode,
1892 this option is unlikely to provide any performance gain.
1896 prompt "Enable seccomp to safely compute untrusted bytecode"
1898 This kernel feature is useful for number crunching applications
1899 that may need to compute untrusted bytecode during their
1900 execution. By using pipes or other transports made available to
1901 the process as file descriptors supporting the read/write
1902 syscalls, it's possible to isolate those applications in
1903 their own address space using seccomp. Once seccomp is
1904 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1905 and the task is only allowed to execute a few safe syscalls
1906 defined by each seccomp mode.
1919 bool "Xen guest support on ARM (EXPERIMENTAL)"
1920 depends on ARM && AEABI && OF
1921 depends on CPU_V7 && !CPU_V6
1922 depends on !GENERIC_ATOMIC64
1924 select ARCH_DMA_ADDR_T_64BIT
1928 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1935 bool "Flattened Device Tree support"
1938 select OF_EARLY_FLATTREE
1939 select OF_RESERVED_MEM
1941 Include support for flattened device tree machine descriptions.
1944 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1947 This is the traditional way of passing data to the kernel at boot
1948 time. If you are solely relying on the flattened device tree (or
1949 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1950 to remove ATAGS support from your kernel binary. If unsure,
1953 config DEPRECATED_PARAM_STRUCT
1954 bool "Provide old way to pass kernel parameters"
1957 This was deprecated in 2001 and announced to live on for 5 years.
1958 Some old boot loaders still use this way.
1960 # Compressed boot loader in ROM. Yes, we really want to ask about
1961 # TEXT and BSS so we preserve their values in the config files.
1962 config ZBOOT_ROM_TEXT
1963 hex "Compressed ROM boot loader base address"
1966 The physical address at which the ROM-able zImage is to be
1967 placed in the target. Platforms which normally make use of
1968 ROM-able zImage formats normally set this to a suitable
1969 value in their defconfig file.
1971 If ZBOOT_ROM is not enabled, this has no effect.
1973 config ZBOOT_ROM_BSS
1974 hex "Compressed ROM boot loader BSS address"
1977 The base address of an area of read/write memory in the target
1978 for the ROM-able zImage which must be available while the
1979 decompressor is running. It must be large enough to hold the
1980 entire decompressed kernel plus an additional 128 KiB.
1981 Platforms which normally make use of ROM-able zImage formats
1982 normally set this to a suitable value in their defconfig file.
1984 If ZBOOT_ROM is not enabled, this has no effect.
1987 bool "Compressed boot loader in ROM/flash"
1988 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1989 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1991 Say Y here if you intend to execute your compressed kernel image
1992 (zImage) directly from ROM or flash. If unsure, say N.
1995 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1996 depends on ZBOOT_ROM && ARCH_SH7372
1997 default ZBOOT_ROM_NONE
1999 Include experimental SD/MMC loading code in the ROM-able zImage.
2000 With this enabled it is possible to write the ROM-able zImage
2001 kernel image to an MMC or SD card and boot the kernel straight
2002 from the reset vector. At reset the processor Mask ROM will load
2003 the first part of the ROM-able zImage which in turn loads the
2004 rest the kernel image to RAM.
2006 config ZBOOT_ROM_NONE
2007 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2009 Do not load image from SD or MMC
2011 config ZBOOT_ROM_MMCIF
2012 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2014 Load image from MMCIF hardware block.
2016 config ZBOOT_ROM_SH_MOBILE_SDHI
2017 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2019 Load image from SDHI hardware block
2023 config ARM_APPENDED_DTB
2024 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2027 With this option, the boot code will look for a device tree binary
2028 (DTB) appended to zImage
2029 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2031 This is meant as a backward compatibility convenience for those
2032 systems with a bootloader that can't be upgraded to accommodate
2033 the documented boot protocol using a device tree.
2035 Beware that there is very little in terms of protection against
2036 this option being confused by leftover garbage in memory that might
2037 look like a DTB header after a reboot if no actual DTB is appended
2038 to zImage. Do not leave this option active in a production kernel
2039 if you don't intend to always append a DTB. Proper passing of the
2040 location into r2 of a bootloader provided DTB is always preferable
2043 config ARM_ATAG_DTB_COMPAT
2044 bool "Supplement the appended DTB with traditional ATAG information"
2045 depends on ARM_APPENDED_DTB
2047 Some old bootloaders can't be updated to a DTB capable one, yet
2048 they provide ATAGs with memory configuration, the ramdisk address,
2049 the kernel cmdline string, etc. Such information is dynamically
2050 provided by the bootloader and can't always be stored in a static
2051 DTB. To allow a device tree enabled kernel to be used with such
2052 bootloaders, this option allows zImage to extract the information
2053 from the ATAG list and store it at run time into the appended DTB.
2056 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2057 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2059 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2060 bool "Use bootloader kernel arguments if available"
2062 Uses the command-line options passed by the boot loader instead of
2063 the device tree bootargs property. If the boot loader doesn't provide
2064 any, the device tree bootargs property will be used.
2066 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2067 bool "Extend with bootloader kernel arguments"
2069 The command-line arguments provided by the boot loader will be
2070 appended to the the device tree bootargs property.
2075 string "Default kernel command string"
2078 On some architectures (EBSA110 and CATS), there is currently no way
2079 for the boot loader to pass arguments to the kernel. For these
2080 architectures, you should supply some command-line options at build
2081 time by entering them here. As a minimum, you should specify the
2082 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2085 prompt "Kernel command line type" if CMDLINE != ""
2086 default CMDLINE_FROM_BOOTLOADER
2089 config CMDLINE_FROM_BOOTLOADER
2090 bool "Use bootloader kernel arguments if available"
2092 Uses the command-line options passed by the boot loader. If
2093 the boot loader doesn't provide any, the default kernel command
2094 string provided in CMDLINE will be used.
2096 config CMDLINE_EXTEND
2097 bool "Extend bootloader kernel arguments"
2099 The command-line arguments provided by the boot loader will be
2100 appended to the default kernel command string.
2102 config CMDLINE_FORCE
2103 bool "Always use the default kernel command string"
2105 Always use the default kernel command string, even if the boot
2106 loader passes other arguments to the kernel.
2107 This is useful if you cannot or don't want to change the
2108 command-line options your boot loader passes to the kernel.
2112 bool "Kernel Execute-In-Place from ROM"
2113 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2115 Execute-In-Place allows the kernel to run from non-volatile storage
2116 directly addressable by the CPU, such as NOR flash. This saves RAM
2117 space since the text section of the kernel is not loaded from flash
2118 to RAM. Read-write sections, such as the data section and stack,
2119 are still copied to RAM. The XIP kernel is not compressed since
2120 it has to run directly from flash, so it will take more space to
2121 store it. The flash address used to link the kernel object files,
2122 and for storing it, is configuration dependent. Therefore, if you
2123 say Y here, you must know the proper physical address where to
2124 store the kernel image depending on your own flash memory usage.
2126 Also note that the make target becomes "make xipImage" rather than
2127 "make zImage" or "make Image". The final kernel binary to put in
2128 ROM memory will be arch/arm/boot/xipImage.
2132 config XIP_PHYS_ADDR
2133 hex "XIP Kernel Physical Location"
2134 depends on XIP_KERNEL
2135 default "0x00080000"
2137 This is the physical address in your flash memory the kernel will
2138 be linked for and stored to. This address is dependent on your
2142 bool "Kexec system call (EXPERIMENTAL)"
2143 depends on (!SMP || PM_SLEEP_SMP)
2145 kexec is a system call that implements the ability to shutdown your
2146 current kernel, and to start another kernel. It is like a reboot
2147 but it is independent of the system firmware. And like a reboot
2148 you can start any kernel with it, not just Linux.
2150 It is an ongoing process to be certain the hardware in a machine
2151 is properly shutdown, so do not be surprised if this code does not
2152 initially work for you.
2155 bool "Export atags in procfs"
2156 depends on ATAGS && KEXEC
2159 Should the atags used to boot the kernel be exported in an "atags"
2160 file in procfs. Useful with kexec.
2163 bool "Build kdump crash kernel (EXPERIMENTAL)"
2165 Generate crash dump after being started by kexec. This should
2166 be normally only set in special crash dump kernels which are
2167 loaded in the main kernel with kexec-tools into a specially
2168 reserved region and then later executed after a crash by
2169 kdump/kexec. The crash dump kernel must be compiled to a
2170 memory address not used by the main kernel
2172 For more details see Documentation/kdump/kdump.txt
2174 config AUTO_ZRELADDR
2175 bool "Auto calculation of the decompressed kernel image address"
2177 ZRELADDR is the physical address where the decompressed kernel
2178 image will be placed. If AUTO_ZRELADDR is selected, the address
2179 will be determined at run-time by masking the current IP with
2180 0xf8000000. This assumes the zImage being placed in the first 128MB
2181 from start of memory.
2185 menu "CPU Power Management"
2188 source "drivers/cpufreq/Kconfig"
2191 source "drivers/cpuidle/Kconfig"
2195 menu "Floating point emulation"
2197 comment "At least one emulation must be selected"
2200 bool "NWFPE math emulation"
2201 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2203 Say Y to include the NWFPE floating point emulator in the kernel.
2204 This is necessary to run most binaries. Linux does not currently
2205 support floating point hardware so you need to say Y here even if
2206 your machine has an FPA or floating point co-processor podule.
2208 You may say N here if you are going to load the Acorn FPEmulator
2209 early in the bootup.
2212 bool "Support extended precision"
2213 depends on FPE_NWFPE
2215 Say Y to include 80-bit support in the kernel floating-point
2216 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2217 Note that gcc does not generate 80-bit operations by default,
2218 so in most cases this option only enlarges the size of the
2219 floating point emulator without any good reason.
2221 You almost surely want to say N here.
2224 bool "FastFPE math emulation (EXPERIMENTAL)"
2225 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2227 Say Y here to include the FAST floating point emulator in the kernel.
2228 This is an experimental much faster emulator which now also has full
2229 precision for the mantissa. It does not support any exceptions.
2230 It is very simple, and approximately 3-6 times faster than NWFPE.
2232 It should be sufficient for most programs. It may be not suitable
2233 for scientific calculations, but you have to check this for yourself.
2234 If you do not feel you need a faster FP emulation you should better
2238 bool "VFP-format floating point maths"
2239 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2241 Say Y to include VFP support code in the kernel. This is needed
2242 if your hardware includes a VFP unit.
2244 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2245 release notes and additional status information.
2247 Say N if your target does not have VFP hardware.
2255 bool "Advanced SIMD (NEON) Extension support"
2256 depends on VFPv3 && CPU_V7
2258 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2261 config KERNEL_MODE_NEON
2262 bool "Support for NEON in kernel mode"
2263 depends on NEON && AEABI
2265 Say Y to include support for NEON in kernel mode.
2269 menu "Userspace binary formats"
2271 source "fs/Kconfig.binfmt"
2274 tristate "RISC OS personality"
2277 Say Y here to include the kernel code necessary if you want to run
2278 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2279 experimental; if this sounds frightening, say N and sleep in peace.
2280 You can also say M here to compile this support as a module (which
2281 will be called arthur).
2285 menu "Power management options"
2287 source "kernel/power/Kconfig"
2289 config ARCH_SUSPEND_POSSIBLE
2290 depends on !ARCH_S5PC100
2291 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2292 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2295 config ARM_CPU_SUSPEND
2300 source "net/Kconfig"
2302 source "drivers/Kconfig"
2306 source "arch/arm/Kconfig.debug"
2308 source "security/Kconfig"
2310 source "crypto/Kconfig"
2312 source "lib/Kconfig"
2314 source "arch/arm/kvm/Kconfig"