4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
39 select HAVE_ARCH_TRACEHOOK
41 select HAVE_CC_STACKPROTECTOR
42 select HAVE_CONTEXT_TRACKING
43 select HAVE_C_RECORDMCOUNT
44 select HAVE_DEBUG_KMEMLEAK
45 select HAVE_DMA_API_DEBUG
47 select HAVE_DMA_CONTIGUOUS if MMU
48 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
49 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
50 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
51 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
52 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
53 select HAVE_GENERIC_DMA_COHERENT
54 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
55 select HAVE_IDE if PCI || ISA || PCMCIA
56 select HAVE_IRQ_TIME_ACCOUNTING
57 select HAVE_KERNEL_GZIP
58 select HAVE_KERNEL_LZ4
59 select HAVE_KERNEL_LZMA
60 select HAVE_KERNEL_LZO
62 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
63 select HAVE_KRETPROBES if (HAVE_KPROBES)
65 select HAVE_MOD_ARCH_SPECIFIC
66 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
67 select HAVE_OPTPROBES if !THUMB2_KERNEL
68 select HAVE_PERF_EVENTS
70 select HAVE_PERF_USER_STACK_DUMP
71 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
72 select HAVE_REGS_AND_STACK_ACCESS_API
73 select HAVE_SYSCALL_TRACEPOINTS
75 select HAVE_VIRT_CPU_ACCOUNTING_GEN
76 select IRQ_FORCED_THREADING
77 select MODULES_USE_ELF_REL
80 select OLD_SIGSUSPEND3
81 select PERF_USE_VMALLOC
83 select SYS_SUPPORTS_APM_EMULATION
84 # Above selects are sorted alphabetically; please add new ones
85 # according to that. Thanks.
87 The ARM series is a line of low-power-consumption RISC chip designs
88 licensed by ARM Ltd and targeted at embedded applications and
89 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
90 manufactured, but legacy ARM-based PC hardware remains popular in
91 Europe. There is an ARM Linux project with a web page at
92 <http://www.arm.linux.org.uk/>.
94 config ARM_HAS_SG_CHAIN
95 select ARCH_HAS_SG_CHAIN
98 config NEED_SG_DMA_LENGTH
101 config ARM_DMA_USE_IOMMU
103 select ARM_HAS_SG_CHAIN
104 select NEED_SG_DMA_LENGTH
108 config ARM_DMA_IOMMU_ALIGNMENT
109 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
113 DMA mapping framework by default aligns all buffers to the smallest
114 PAGE_SIZE order which is greater than or equal to the requested buffer
115 size. This works well for buffers up to a few hundreds kilobytes, but
116 for larger buffers it just a waste of address space. Drivers which has
117 relatively small addressing window (like 64Mib) might run out of
118 virtual space with just a few allocations.
120 With this parameter you can specify the maximum PAGE_SIZE order for
121 DMA IOMMU buffers. Larger buffers will be aligned only to this
122 specified order. The order is expressed as a power of two multiplied
127 config MIGHT_HAVE_PCI
130 config SYS_SUPPORTS_APM_EMULATION
135 select GENERIC_ALLOCATOR
146 The Extended Industry Standard Architecture (EISA) bus was
147 developed as an open alternative to the IBM MicroChannel bus.
149 The EISA bus provided some of the features of the IBM MicroChannel
150 bus while maintaining backward compatibility with cards made for
151 the older ISA bus. The EISA bus saw limited use between 1988 and
152 1995 when it was made obsolete by the PCI bus.
154 Say Y here if you are building a kernel for an EISA-based machine.
161 config STACKTRACE_SUPPORT
165 config HAVE_LATENCYTOP_SUPPORT
170 config LOCKDEP_SUPPORT
174 config TRACE_IRQFLAGS_SUPPORT
178 config RWSEM_XCHGADD_ALGORITHM
182 config ARCH_HAS_ILOG2_U32
185 config ARCH_HAS_ILOG2_U64
188 config ARCH_HAS_BANDGAP
191 config GENERIC_HWEIGHT
195 config GENERIC_CALIBRATE_DELAY
199 config ARCH_MAY_HAVE_PC_FDC
205 config NEED_DMA_MAP_STATE
208 config ARCH_SUPPORTS_UPROBES
211 config ARCH_HAS_DMA_SET_COHERENT_MASK
214 config GENERIC_ISA_DMA
220 config NEED_RET_TO_USER
228 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
229 default DRAM_BASE if REMAP_VECTORS_TO_RAM
232 The base address of exception vectors. This must be two pages
235 config ARM_PATCH_PHYS_VIRT
236 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 depends on !XIP_KERNEL && MMU
239 depends on !ARCH_REALVIEW || !SPARSEMEM
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_IO_H
255 Select this when mach/io.h is required to provide special
256 definitions for this platform. The need for mach/io.h should
257 be avoided when possible.
259 config NEED_MACH_MEMORY_H
262 Select this when mach/memory.h is required to provide special
263 definitions for this platform. The need for mach/memory.h should
264 be avoided when possible.
267 hex "Physical address of main memory" if MMU
268 depends on !ARM_PATCH_PHYS_VIRT
269 default DRAM_BASE if !MMU
270 default 0x00000000 if ARCH_EBSA110 || \
271 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
276 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
277 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
278 default 0x20000000 if ARCH_S5PV210
279 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
280 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
281 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
282 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
283 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
285 Please provide the physical address corresponding to the
286 location of main memory in your system.
292 config PGTABLE_LEVELS
294 default 3 if ARM_LPAE
297 source "init/Kconfig"
299 source "kernel/Kconfig.freezer"
304 bool "MMU-based Paged Memory Management Support"
307 Select if you want MMU-based virtualised addressing space
308 support by paged memory management. If unsure, say 'Y'.
311 # The "ARM system type" choice list is ordered alphabetically by option
312 # text. Please add new entries in the option alphabetic order.
315 prompt "ARM system type"
316 default ARCH_VERSATILE if !MMU
317 default ARCH_MULTIPLATFORM if MMU
319 config ARCH_MULTIPLATFORM
320 bool "Allow multiple platforms to be selected"
322 select ARCH_WANT_OPTIONAL_GPIOLIB
323 select ARM_HAS_SG_CHAIN
324 select ARM_PATCH_PHYS_VIRT
328 select GENERIC_CLOCKEVENTS
329 select MIGHT_HAVE_PCI
330 select MULTI_IRQ_HANDLER
334 config ARM_SINGLE_ARMV7M
335 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
337 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select GENERIC_CLOCKEVENTS
349 bool "ARM Ltd. RealView family"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
352 select ARM_TIMER_SP804
354 select COMMON_CLK_VERSATILE
355 select GENERIC_CLOCKEVENTS
356 select GPIO_PL061 if GPIOLIB
358 select NEED_MACH_MEMORY_H
359 select PLAT_VERSATILE
360 select PLAT_VERSATILE_SCHED_CLOCK
362 This enables support for ARM Ltd RealView boards.
364 config ARCH_VERSATILE
365 bool "ARM Ltd. Versatile family"
366 select ARCH_WANT_OPTIONAL_GPIOLIB
368 select ARM_TIMER_SP804
371 select GENERIC_CLOCKEVENTS
372 select HAVE_MACH_CLKDEV
374 select PLAT_VERSATILE
375 select PLAT_VERSATILE_CLOCK
376 select PLAT_VERSATILE_SCHED_CLOCK
377 select VERSATILE_FPGA_IRQ
379 This enables support for ARM Ltd Versatile board.
382 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
383 select ARCH_REQUIRE_GPIOLIB
388 select GENERIC_CLOCKEVENTS
392 Support for Cirrus Logic 711x/721x/731x based boards.
395 bool "Cortina Systems Gemini"
396 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_CLOCKEVENTS
401 Support for the Cortina Systems Gemini family SoCs
405 select ARCH_USES_GETTIMEOFFSET
408 select NEED_MACH_IO_H
409 select NEED_MACH_MEMORY_H
412 This is an evaluation board for the StrongARM processor available
413 from Digital. It has limited hardware on-board, including an
414 Ethernet interface, two PCMCIA sockets, two serial ports and a
419 select ARCH_HAS_HOLES_MEMORYMODEL
420 select ARCH_REQUIRE_GPIOLIB
421 select ARCH_USES_GETTIMEOFFSET
427 This enables support for the Cirrus EP93xx series of CPUs.
429 config ARCH_FOOTBRIDGE
433 select GENERIC_CLOCKEVENTS
435 select NEED_MACH_IO_H if !MMU
436 select NEED_MACH_MEMORY_H
438 Support for systems based on the DC21285 companion chip
439 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
442 bool "Hilscher NetX based"
446 select GENERIC_CLOCKEVENTS
448 This enables support for systems based on the Hilscher NetX Soc
454 select NEED_MACH_MEMORY_H
455 select NEED_RET_TO_USER
461 Support for Intel's IOP13XX (XScale) family of processors.
466 select ARCH_REQUIRE_GPIOLIB
469 select NEED_RET_TO_USER
473 Support for Intel's 80219 and IOP32X (XScale) family of
479 select ARCH_REQUIRE_GPIOLIB
482 select NEED_RET_TO_USER
486 Support for Intel's IOP33X (XScale) family of processors.
491 select ARCH_HAS_DMA_SET_COHERENT_MASK
492 select ARCH_REQUIRE_GPIOLIB
493 select ARCH_SUPPORTS_BIG_ENDIAN
496 select DMABOUNCE if PCI
497 select GENERIC_CLOCKEVENTS
498 select MIGHT_HAVE_PCI
499 select NEED_MACH_IO_H
500 select USB_EHCI_BIG_ENDIAN_DESC
501 select USB_EHCI_BIG_ENDIAN_MMIO
503 Support for Intel's IXP4XX (XScale) family of processors.
507 select ARCH_REQUIRE_GPIOLIB
509 select GENERIC_CLOCKEVENTS
510 select MIGHT_HAVE_PCI
514 select PLAT_ORION_LEGACY
516 Support for the Marvell Dove SoC 88AP510
519 bool "Marvell MV78xx0"
520 select ARCH_REQUIRE_GPIOLIB
522 select GENERIC_CLOCKEVENTS
525 select PLAT_ORION_LEGACY
527 Support for the following Marvell MV78xx0 series SoCs:
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
538 select PLAT_ORION_LEGACY
540 Support for the following Marvell Orion 5x series SoCs:
541 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
542 Orion-2 (5281), Orion-1-90 (6183).
545 bool "Marvell PXA168/910/MMP2"
547 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_ALLOCATOR
550 select GENERIC_CLOCKEVENTS
553 select MULTI_IRQ_HANDLER
558 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
561 bool "Micrel/Kendin KS8695"
562 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_CLOCKEVENTS
566 select NEED_MACH_MEMORY_H
568 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
569 System-on-Chip devices.
572 bool "Nuvoton W90X900 CPU"
573 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
579 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
580 At present, the w90x900 has been renamed nuc900, regarding
581 the ARM series product line, you can login the following
582 link address to know more.
584 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
585 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
589 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
598 Support for the NXP LPC32XX family of processors
601 bool "PXA2xx/PXA3xx-based"
604 select ARCH_REQUIRE_GPIOLIB
605 select ARM_CPU_SUSPEND if PM
611 select GENERIC_CLOCKEVENTS
615 select MULTI_IRQ_HANDLER
619 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
621 config ARCH_SHMOBILE_LEGACY
622 bool "Renesas ARM SoCs (non-multiplatform)"
624 select ARM_PATCH_PHYS_VIRT if MMU
627 select GENERIC_CLOCKEVENTS
628 select HAVE_ARM_SCU if SMP
629 select HAVE_ARM_TWD if SMP
631 select MIGHT_HAVE_CACHE_L2X0
632 select MULTI_IRQ_HANDLER
635 select PM_GENERIC_DOMAINS if PM
639 Support for Renesas ARM SoC platforms using a non-multiplatform
640 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
646 select ARCH_MAY_HAVE_PC_FDC
647 select ARCH_SPARSEMEM_ENABLE
648 select ARCH_USES_GETTIMEOFFSET
652 select HAVE_PATA_PLATFORM
654 select NEED_MACH_IO_H
655 select NEED_MACH_MEMORY_H
659 On the Acorn Risc-PC, Linux can support the internal IDE disk and
660 CD-ROM interface, serial and parallel port, and the floppy drive.
665 select ARCH_REQUIRE_GPIOLIB
666 select ARCH_SPARSEMEM_ENABLE
671 select GENERIC_CLOCKEVENTS
675 select MULTI_IRQ_HANDLER
676 select NEED_MACH_MEMORY_H
679 Support for StrongARM 11x0 based boards.
682 bool "Samsung S3C24XX SoCs"
683 select ARCH_REQUIRE_GPIOLIB
686 select CLKSRC_SAMSUNG_PWM
687 select GENERIC_CLOCKEVENTS
689 select HAVE_S3C2410_I2C if I2C
690 select HAVE_S3C2410_WATCHDOG if WATCHDOG
691 select HAVE_S3C_RTC if RTC_CLASS
692 select MULTI_IRQ_HANDLER
693 select NEED_MACH_IO_H
696 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
697 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
698 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
699 Samsung SMDK2410 development board (and derivatives).
702 bool "Samsung S3C64XX"
703 select ARCH_REQUIRE_GPIOLIB
708 select CLKSRC_SAMSUNG_PWM
709 select COMMON_CLK_SAMSUNG
711 select GENERIC_CLOCKEVENTS
713 select HAVE_S3C2410_I2C if I2C
714 select HAVE_S3C2410_WATCHDOG if WATCHDOG
718 select PM_GENERIC_DOMAINS if PM
720 select S3C_GPIO_TRACK
722 select SAMSUNG_WAKEMASK
723 select SAMSUNG_WDT_RESET
725 Samsung S3C64XX series based systems
729 select ARCH_HAS_HOLES_MEMORYMODEL
730 select ARCH_REQUIRE_GPIOLIB
732 select GENERIC_ALLOCATOR
733 select GENERIC_CLOCKEVENTS
734 select GENERIC_IRQ_CHIP
740 Support for TI's DaVinci platform.
745 select ARCH_HAS_HOLES_MEMORYMODEL
747 select ARCH_REQUIRE_GPIOLIB
750 select GENERIC_CLOCKEVENTS
751 select GENERIC_IRQ_CHIP
754 select MULTI_IRQ_HANDLER
755 select NEED_MACH_IO_H if PCCARD
756 select NEED_MACH_MEMORY_H
759 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
763 menu "Multiple platform selection"
764 depends on ARCH_MULTIPLATFORM
766 comment "CPU Core family selection"
769 bool "ARMv4 based platforms (FA526)"
770 depends on !ARCH_MULTI_V6_V7
771 select ARCH_MULTI_V4_V5
774 config ARCH_MULTI_V4T
775 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
776 depends on !ARCH_MULTI_V6_V7
777 select ARCH_MULTI_V4_V5
778 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
779 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
780 CPU_ARM925T || CPU_ARM940T)
783 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
784 depends on !ARCH_MULTI_V6_V7
785 select ARCH_MULTI_V4_V5
786 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
787 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
788 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
790 config ARCH_MULTI_V4_V5
794 bool "ARMv6 based platforms (ARM11)"
795 select ARCH_MULTI_V6_V7
799 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
801 select ARCH_MULTI_V6_V7
805 config ARCH_MULTI_V6_V7
807 select MIGHT_HAVE_CACHE_L2X0
809 config ARCH_MULTI_CPU_AUTO
810 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
816 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
820 select HAVE_ARM_ARCH_TIMER
823 # This is sorted alphabetically by mach-* pathname. However, plat-*
824 # Kconfigs may be included either alphabetically (according to the
825 # plat- suffix) or along side the corresponding mach-* source.
827 source "arch/arm/mach-mvebu/Kconfig"
829 source "arch/arm/mach-alpine/Kconfig"
831 source "arch/arm/mach-asm9260/Kconfig"
833 source "arch/arm/mach-at91/Kconfig"
835 source "arch/arm/mach-axxia/Kconfig"
837 source "arch/arm/mach-bcm/Kconfig"
839 source "arch/arm/mach-berlin/Kconfig"
841 source "arch/arm/mach-clps711x/Kconfig"
843 source "arch/arm/mach-cns3xxx/Kconfig"
845 source "arch/arm/mach-davinci/Kconfig"
847 source "arch/arm/mach-digicolor/Kconfig"
849 source "arch/arm/mach-dove/Kconfig"
851 source "arch/arm/mach-ep93xx/Kconfig"
853 source "arch/arm/mach-footbridge/Kconfig"
855 source "arch/arm/mach-gemini/Kconfig"
857 source "arch/arm/mach-highbank/Kconfig"
859 source "arch/arm/mach-hisi/Kconfig"
861 source "arch/arm/mach-integrator/Kconfig"
863 source "arch/arm/mach-iop32x/Kconfig"
865 source "arch/arm/mach-iop33x/Kconfig"
867 source "arch/arm/mach-iop13xx/Kconfig"
869 source "arch/arm/mach-ixp4xx/Kconfig"
871 source "arch/arm/mach-keystone/Kconfig"
873 source "arch/arm/mach-ks8695/Kconfig"
875 source "arch/arm/mach-meson/Kconfig"
877 source "arch/arm/mach-moxart/Kconfig"
879 source "arch/arm/mach-mv78xx0/Kconfig"
881 source "arch/arm/mach-imx/Kconfig"
883 source "arch/arm/mach-mediatek/Kconfig"
885 source "arch/arm/mach-mxs/Kconfig"
887 source "arch/arm/mach-netx/Kconfig"
889 source "arch/arm/mach-nomadik/Kconfig"
891 source "arch/arm/mach-nspire/Kconfig"
893 source "arch/arm/plat-omap/Kconfig"
895 source "arch/arm/mach-omap1/Kconfig"
897 source "arch/arm/mach-omap2/Kconfig"
899 source "arch/arm/mach-orion5x/Kconfig"
901 source "arch/arm/mach-picoxcell/Kconfig"
903 source "arch/arm/mach-pxa/Kconfig"
904 source "arch/arm/plat-pxa/Kconfig"
906 source "arch/arm/mach-mmp/Kconfig"
908 source "arch/arm/mach-qcom/Kconfig"
910 source "arch/arm/mach-realview/Kconfig"
912 source "arch/arm/mach-rockchip/Kconfig"
914 source "arch/arm/mach-sa1100/Kconfig"
916 source "arch/arm/mach-socfpga/Kconfig"
918 source "arch/arm/mach-spear/Kconfig"
920 source "arch/arm/mach-sti/Kconfig"
922 source "arch/arm/mach-s3c24xx/Kconfig"
924 source "arch/arm/mach-s3c64xx/Kconfig"
926 source "arch/arm/mach-s5pv210/Kconfig"
928 source "arch/arm/mach-exynos/Kconfig"
929 source "arch/arm/plat-samsung/Kconfig"
931 source "arch/arm/mach-shmobile/Kconfig"
933 source "arch/arm/mach-sunxi/Kconfig"
935 source "arch/arm/mach-prima2/Kconfig"
937 source "arch/arm/mach-tegra/Kconfig"
939 source "arch/arm/mach-u300/Kconfig"
941 source "arch/arm/mach-uniphier/Kconfig"
943 source "arch/arm/mach-ux500/Kconfig"
945 source "arch/arm/mach-versatile/Kconfig"
947 source "arch/arm/mach-vexpress/Kconfig"
948 source "arch/arm/plat-versatile/Kconfig"
950 source "arch/arm/mach-vt8500/Kconfig"
952 source "arch/arm/mach-w90x900/Kconfig"
954 source "arch/arm/mach-zx/Kconfig"
956 source "arch/arm/mach-zynq/Kconfig"
958 # ARMv7-M architecture
960 bool "Energy Micro efm32"
961 depends on ARM_SINGLE_ARMV7M
962 select ARCH_REQUIRE_GPIOLIB
964 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
968 bool "NXP LPC18xx/LPC43xx"
969 depends on ARM_SINGLE_ARMV7M
970 select ARCH_HAS_RESET_CONTROLLER
972 select CLKSRC_LPC32XX
975 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
976 high performance microcontrollers.
979 bool "STMicrolectronics STM32"
980 depends on ARM_SINGLE_ARMV7M
981 select ARCH_HAS_RESET_CONTROLLER
982 select ARMV7M_SYSTICK
984 select RESET_CONTROLLER
986 Support for STMicroelectronics STM32 processors.
988 # Definitions to make life easier
994 select GENERIC_CLOCKEVENTS
1000 select GENERIC_IRQ_CHIP
1003 config PLAT_ORION_LEGACY
1010 config PLAT_VERSATILE
1013 source "arch/arm/firmware/Kconfig"
1015 source arch/arm/mm/Kconfig
1018 bool "Enable iWMMXt support"
1019 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1020 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1022 Enable support for iWMMXt context switching at run time if
1023 running on a CPU that supports it.
1025 config MULTI_IRQ_HANDLER
1028 Allow each machine to specify it's own IRQ handler at run time.
1031 source "arch/arm/Kconfig-nommu"
1034 config PJ4B_ERRATA_4742
1035 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1036 depends on CPU_PJ4B && MACH_ARMADA_370
1039 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1040 Event (WFE) IDLE states, a specific timing sensitivity exists between
1041 the retiring WFI/WFE instructions and the newly issued subsequent
1042 instructions. This sensitivity can result in a CPU hang scenario.
1044 The software must insert either a Data Synchronization Barrier (DSB)
1045 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1048 config ARM_ERRATA_326103
1049 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1052 Executing a SWP instruction to read-only memory does not set bit 11
1053 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1054 treat the access as a read, preventing a COW from occurring and
1055 causing the faulting task to livelock.
1057 config ARM_ERRATA_411920
1058 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1059 depends on CPU_V6 || CPU_V6K
1061 Invalidation of the Instruction Cache operation can
1062 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1063 It does not affect the MPCore. This option enables the ARM Ltd.
1064 recommended workaround.
1066 config ARM_ERRATA_430973
1067 bool "ARM errata: Stale prediction on replaced interworking branch"
1070 This option enables the workaround for the 430973 Cortex-A8
1071 r1p* erratum. If a code sequence containing an ARM/Thumb
1072 interworking branch is replaced with another code sequence at the
1073 same virtual address, whether due to self-modifying code or virtual
1074 to physical address re-mapping, Cortex-A8 does not recover from the
1075 stale interworking branch prediction. This results in Cortex-A8
1076 executing the new code sequence in the incorrect ARM or Thumb state.
1077 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1078 and also flushes the branch target cache at every context switch.
1079 Note that setting specific bits in the ACTLR register may not be
1080 available in non-secure mode.
1082 config ARM_ERRATA_458693
1083 bool "ARM errata: Processor deadlock when a false hazard is created"
1085 depends on !ARCH_MULTIPLATFORM
1087 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1088 erratum. For very specific sequences of memory operations, it is
1089 possible for a hazard condition intended for a cache line to instead
1090 be incorrectly associated with a different cache line. This false
1091 hazard might then cause a processor deadlock. The workaround enables
1092 the L1 caching of the NEON accesses and disables the PLD instruction
1093 in the ACTLR register. Note that setting specific bits in the ACTLR
1094 register may not be available in non-secure mode.
1096 config ARM_ERRATA_460075
1097 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1099 depends on !ARCH_MULTIPLATFORM
1101 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1102 erratum. Any asynchronous access to the L2 cache may encounter a
1103 situation in which recent store transactions to the L2 cache are lost
1104 and overwritten with stale memory contents from external memory. The
1105 workaround disables the write-allocate mode for the L2 cache via the
1106 ACTLR register. Note that setting specific bits in the ACTLR register
1107 may not be available in non-secure mode.
1109 config ARM_ERRATA_742230
1110 bool "ARM errata: DMB operation may be faulty"
1111 depends on CPU_V7 && SMP
1112 depends on !ARCH_MULTIPLATFORM
1114 This option enables the workaround for the 742230 Cortex-A9
1115 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1116 between two write operations may not ensure the correct visibility
1117 ordering of the two writes. This workaround sets a specific bit in
1118 the diagnostic register of the Cortex-A9 which causes the DMB
1119 instruction to behave as a DSB, ensuring the correct behaviour of
1122 config ARM_ERRATA_742231
1123 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1124 depends on CPU_V7 && SMP
1125 depends on !ARCH_MULTIPLATFORM
1127 This option enables the workaround for the 742231 Cortex-A9
1128 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1129 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1130 accessing some data located in the same cache line, may get corrupted
1131 data due to bad handling of the address hazard when the line gets
1132 replaced from one of the CPUs at the same time as another CPU is
1133 accessing it. This workaround sets specific bits in the diagnostic
1134 register of the Cortex-A9 which reduces the linefill issuing
1135 capabilities of the processor.
1137 config ARM_ERRATA_643719
1138 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1139 depends on CPU_V7 && SMP
1142 This option enables the workaround for the 643719 Cortex-A9 (prior to
1143 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1144 register returns zero when it should return one. The workaround
1145 corrects this value, ensuring cache maintenance operations which use
1146 it behave as intended and avoiding data corruption.
1148 config ARM_ERRATA_720789
1149 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1152 This option enables the workaround for the 720789 Cortex-A9 (prior to
1153 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1154 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1155 As a consequence of this erratum, some TLB entries which should be
1156 invalidated are not, resulting in an incoherency in the system page
1157 tables. The workaround changes the TLB flushing routines to invalidate
1158 entries regardless of the ASID.
1160 config ARM_ERRATA_743622
1161 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1163 depends on !ARCH_MULTIPLATFORM
1165 This option enables the workaround for the 743622 Cortex-A9
1166 (r2p*) erratum. Under very rare conditions, a faulty
1167 optimisation in the Cortex-A9 Store Buffer may lead to data
1168 corruption. This workaround sets a specific bit in the diagnostic
1169 register of the Cortex-A9 which disables the Store Buffer
1170 optimisation, preventing the defect from occurring. This has no
1171 visible impact on the overall performance or power consumption of the
1174 config ARM_ERRATA_751472
1175 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1177 depends on !ARCH_MULTIPLATFORM
1179 This option enables the workaround for the 751472 Cortex-A9 (prior
1180 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1181 completion of a following broadcasted operation if the second
1182 operation is received by a CPU before the ICIALLUIS has completed,
1183 potentially leading to corrupted entries in the cache or TLB.
1185 config ARM_ERRATA_754322
1186 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1189 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1190 r3p*) erratum. A speculative memory access may cause a page table walk
1191 which starts prior to an ASID switch but completes afterwards. This
1192 can populate the micro-TLB with a stale entry which may be hit with
1193 the new ASID. This workaround places two dsb instructions in the mm
1194 switching code so that no page table walks can cross the ASID switch.
1196 config ARM_ERRATA_754327
1197 bool "ARM errata: no automatic Store Buffer drain"
1198 depends on CPU_V7 && SMP
1200 This option enables the workaround for the 754327 Cortex-A9 (prior to
1201 r2p0) erratum. The Store Buffer does not have any automatic draining
1202 mechanism and therefore a livelock may occur if an external agent
1203 continuously polls a memory location waiting to observe an update.
1204 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1205 written polling loops from denying visibility of updates to memory.
1207 config ARM_ERRATA_364296
1208 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1211 This options enables the workaround for the 364296 ARM1136
1212 r0p2 erratum (possible cache data corruption with
1213 hit-under-miss enabled). It sets the undocumented bit 31 in
1214 the auxiliary control register and the FI bit in the control
1215 register, thus disabling hit-under-miss without putting the
1216 processor into full low interrupt latency mode. ARM11MPCore
1219 config ARM_ERRATA_764369
1220 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1221 depends on CPU_V7 && SMP
1223 This option enables the workaround for erratum 764369
1224 affecting Cortex-A9 MPCore with two or more processors (all
1225 current revisions). Under certain timing circumstances, a data
1226 cache line maintenance operation by MVA targeting an Inner
1227 Shareable memory region may fail to proceed up to either the
1228 Point of Coherency or to the Point of Unification of the
1229 system. This workaround adds a DSB instruction before the
1230 relevant cache maintenance functions and sets a specific bit
1231 in the diagnostic control register of the SCU.
1233 config ARM_ERRATA_775420
1234 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1237 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1238 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1239 operation aborts with MMU exception, it might cause the processor
1240 to deadlock. This workaround puts DSB before executing ISB if
1241 an abort may occur on cache maintenance.
1243 config ARM_ERRATA_798181
1244 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1245 depends on CPU_V7 && SMP
1247 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1248 adequately shooting down all use of the old entries. This
1249 option enables the Linux kernel workaround for this erratum
1250 which sends an IPI to the CPUs that are running the same ASID
1251 as the one being invalidated.
1253 config ARM_ERRATA_773022
1254 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1257 This option enables the workaround for the 773022 Cortex-A15
1258 (up to r0p4) erratum. In certain rare sequences of code, the
1259 loop buffer may deliver incorrect instructions. This
1260 workaround disables the loop buffer to avoid the erratum.
1264 source "arch/arm/common/Kconfig"
1271 Find out whether you have ISA slots on your motherboard. ISA is the
1272 name of a bus system, i.e. the way the CPU talks to the other stuff
1273 inside your box. Other bus systems are PCI, EISA, MicroChannel
1274 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1275 newer boards don't support it. If you have ISA, say Y, otherwise N.
1277 # Select ISA DMA controller support
1282 # Select ISA DMA interface
1287 bool "PCI support" if MIGHT_HAVE_PCI
1289 Find out whether you have a PCI motherboard. PCI is the name of a
1290 bus system, i.e. the way the CPU talks to the other stuff inside
1291 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1292 VESA. If you have PCI, say Y, otherwise N.
1298 config PCI_DOMAINS_GENERIC
1299 def_bool PCI_DOMAINS
1301 config PCI_NANOENGINE
1302 bool "BSE nanoEngine PCI support"
1303 depends on SA1100_NANOENGINE
1305 Enable PCI on the BSE nanoEngine board.
1310 config PCI_HOST_ITE8152
1312 depends on PCI && MACH_ARMCORE
1316 source "drivers/pci/Kconfig"
1317 source "drivers/pci/pcie/Kconfig"
1319 source "drivers/pcmcia/Kconfig"
1323 menu "Kernel Features"
1328 This option should be selected by machines which have an SMP-
1331 The only effect of this option is to make the SMP-related
1332 options available to the user for configuration.
1335 bool "Symmetric Multi-Processing"
1336 depends on CPU_V6K || CPU_V7
1337 depends on GENERIC_CLOCKEVENTS
1339 depends on MMU || ARM_MPU
1342 This enables support for systems with more than one CPU. If you have
1343 a system with only one CPU, say N. If you have a system with more
1344 than one CPU, say Y.
1346 If you say N here, the kernel will run on uni- and multiprocessor
1347 machines, but will use only one CPU of a multiprocessor machine. If
1348 you say Y here, the kernel will run on many, but not all,
1349 uniprocessor machines. On a uniprocessor machine, the kernel
1350 will run faster if you say N here.
1352 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1353 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1354 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1356 If you don't know what to do here, say N.
1359 bool "Allow booting SMP kernel on uniprocessor systems"
1360 depends on SMP && !XIP_KERNEL && MMU
1363 SMP kernels contain instructions which fail on non-SMP processors.
1364 Enabling this option allows the kernel to modify itself to make
1365 these instructions safe. Disabling it allows about 1K of space
1368 If you don't know what to do here, say Y.
1370 config ARM_CPU_TOPOLOGY
1371 bool "Support cpu topology definition"
1372 depends on SMP && CPU_V7
1375 Support ARM cpu topology definition. The MPIDR register defines
1376 affinity between processors which is then used to describe the cpu
1377 topology of an ARM System.
1380 bool "Multi-core scheduler support"
1381 depends on ARM_CPU_TOPOLOGY
1383 Multi-core scheduler support improves the CPU scheduler's decision
1384 making when dealing with multi-core CPU chips at a cost of slightly
1385 increased overhead in some places. If unsure say N here.
1388 bool "SMT scheduler support"
1389 depends on ARM_CPU_TOPOLOGY
1391 Improves the CPU scheduler's decision making when dealing with
1392 MultiThreading at a cost of slightly increased overhead in some
1393 places. If unsure say N here.
1398 This option enables support for the ARM system coherency unit
1400 config HAVE_ARM_ARCH_TIMER
1401 bool "Architected timer support"
1403 select ARM_ARCH_TIMER
1404 select GENERIC_CLOCKEVENTS
1406 This option enables support for the ARM architected timer
1411 select CLKSRC_OF if OF
1413 This options enables support for the ARM timer and watchdog unit
1416 bool "Multi-Cluster Power Management"
1417 depends on CPU_V7 && SMP
1419 This option provides the common power management infrastructure
1420 for (multi-)cluster based systems, such as big.LITTLE based
1423 config MCPM_QUAD_CLUSTER
1427 To avoid wasting resources unnecessarily, MCPM only supports up
1428 to 2 clusters by default.
1429 Platforms with 3 or 4 clusters that use MCPM must select this
1430 option to allow the additional clusters to be managed.
1433 bool "big.LITTLE support (Experimental)"
1434 depends on CPU_V7 && SMP
1437 This option enables support selections for the big.LITTLE
1438 system architecture.
1441 bool "big.LITTLE switcher support"
1442 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1443 select ARM_CPU_SUSPEND
1446 The big.LITTLE "switcher" provides the core functionality to
1447 transparently handle transition between a cluster of A15's
1448 and a cluster of A7's in a big.LITTLE system.
1450 config BL_SWITCHER_DUMMY_IF
1451 tristate "Simple big.LITTLE switcher user interface"
1452 depends on BL_SWITCHER && DEBUG_KERNEL
1454 This is a simple and dummy char dev interface to control
1455 the big.LITTLE switcher core code. It is meant for
1456 debugging purposes only.
1459 prompt "Memory split"
1463 Select the desired split between kernel and user memory.
1465 If you are not absolutely sure what you are doing, leave this
1469 bool "3G/1G user/kernel split"
1471 bool "2G/2G user/kernel split"
1473 bool "1G/3G user/kernel split"
1478 default PHYS_OFFSET if !MMU
1479 default 0x40000000 if VMSPLIT_1G
1480 default 0x80000000 if VMSPLIT_2G
1484 int "Maximum number of CPUs (2-32)"
1490 bool "Support for hot-pluggable CPUs"
1493 Say Y here to experiment with turning CPUs off and on. CPUs
1494 can be controlled through /sys/devices/system/cpu.
1497 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1500 Say Y here if you want Linux to communicate with system firmware
1501 implementing the PSCI specification for CPU-centric power
1502 management operations described in ARM document number ARM DEN
1503 0022A ("Power State Coordination Interface System Software on
1506 # The GPIO number here must be sorted by descending number. In case of
1507 # a multiplatform kernel, we just want the highest value required by the
1508 # selected platforms.
1511 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1513 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1514 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1515 default 416 if ARCH_SUNXI
1516 default 392 if ARCH_U8500
1517 default 352 if ARCH_VT8500
1518 default 288 if ARCH_ROCKCHIP
1519 default 264 if MACH_H4700
1522 Maximum number of GPIOs in the system.
1524 If unsure, leave the default value.
1526 source kernel/Kconfig.preempt
1530 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1531 ARCH_S5PV210 || ARCH_EXYNOS4
1532 default 128 if SOC_AT91RM9200
1533 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1537 depends on HZ_FIXED = 0
1538 prompt "Timer frequency"
1562 default HZ_FIXED if HZ_FIXED != 0
1563 default 100 if HZ_100
1564 default 200 if HZ_200
1565 default 250 if HZ_250
1566 default 300 if HZ_300
1567 default 500 if HZ_500
1571 def_bool HIGH_RES_TIMERS
1573 config THUMB2_KERNEL
1574 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1575 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1576 default y if CPU_THUMBONLY
1578 select ARM_ASM_UNIFIED
1581 By enabling this option, the kernel will be compiled in
1582 Thumb-2 mode. A compiler/assembler that understand the unified
1583 ARM-Thumb syntax is needed.
1587 config THUMB2_AVOID_R_ARM_THM_JUMP11
1588 bool "Work around buggy Thumb-2 short branch relocations in gas"
1589 depends on THUMB2_KERNEL && MODULES
1592 Various binutils versions can resolve Thumb-2 branches to
1593 locally-defined, preemptible global symbols as short-range "b.n"
1594 branch instructions.
1596 This is a problem, because there's no guarantee the final
1597 destination of the symbol, or any candidate locations for a
1598 trampoline, are within range of the branch. For this reason, the
1599 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1600 relocation in modules at all, and it makes little sense to add
1603 The symptom is that the kernel fails with an "unsupported
1604 relocation" error when loading some modules.
1606 Until fixed tools are available, passing
1607 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1608 code which hits this problem, at the cost of a bit of extra runtime
1609 stack usage in some cases.
1611 The problem is described in more detail at:
1612 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1614 Only Thumb-2 kernels are affected.
1616 Unless you are sure your tools don't have this problem, say Y.
1618 config ARM_ASM_UNIFIED
1622 bool "Use the ARM EABI to compile the kernel"
1624 This option allows for the kernel to be compiled using the latest
1625 ARM ABI (aka EABI). This is only useful if you are using a user
1626 space environment that is also compiled with EABI.
1628 Since there are major incompatibilities between the legacy ABI and
1629 EABI, especially with regard to structure member alignment, this
1630 option also changes the kernel syscall calling convention to
1631 disambiguate both ABIs and allow for backward compatibility support
1632 (selected with CONFIG_OABI_COMPAT).
1634 To use this you need GCC version 4.0.0 or later.
1637 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1638 depends on AEABI && !THUMB2_KERNEL
1640 This option preserves the old syscall interface along with the
1641 new (ARM EABI) one. It also provides a compatibility layer to
1642 intercept syscalls that have structure arguments which layout
1643 in memory differs between the legacy ABI and the new ARM EABI
1644 (only for non "thumb" binaries). This option adds a tiny
1645 overhead to all syscalls and produces a slightly larger kernel.
1647 The seccomp filter system will not be available when this is
1648 selected, since there is no way yet to sensibly distinguish
1649 between calling conventions during filtering.
1651 If you know you'll be using only pure EABI user space then you
1652 can say N here. If this option is not selected and you attempt
1653 to execute a legacy ABI binary then the result will be
1654 UNPREDICTABLE (in fact it can be predicted that it won't work
1655 at all). If in doubt say N.
1657 config ARCH_HAS_HOLES_MEMORYMODEL
1660 config ARCH_SPARSEMEM_ENABLE
1663 config ARCH_SPARSEMEM_DEFAULT
1664 def_bool ARCH_SPARSEMEM_ENABLE
1666 config ARCH_SELECT_MEMORY_MODEL
1667 def_bool ARCH_SPARSEMEM_ENABLE
1669 config HAVE_ARCH_PFN_VALID
1670 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1672 config HAVE_GENERIC_RCU_GUP
1677 bool "High Memory Support"
1680 The address space of ARM processors is only 4 Gigabytes large
1681 and it has to accommodate user address space, kernel address
1682 space as well as some memory mapped IO. That means that, if you
1683 have a large amount of physical memory and/or IO, not all of the
1684 memory can be "permanently mapped" by the kernel. The physical
1685 memory that is not permanently mapped is called "high memory".
1687 Depending on the selected kernel/user memory split, minimum
1688 vmalloc space and actual amount of RAM, you may not need this
1689 option which should result in a slightly faster kernel.
1694 bool "Allocate 2nd-level pagetables from highmem"
1697 The VM uses one page of physical memory for each page table.
1698 For systems with a lot of processes, this can use a lot of
1699 precious low memory, eventually leading to low memory being
1700 consumed by page tables. Setting this option will allow
1701 user-space 2nd level page tables to reside in high memory.
1703 config HW_PERF_EVENTS
1704 bool "Enable hardware performance counter support for perf events"
1705 depends on PERF_EVENTS
1708 Enable hardware performance counter support for perf events. If
1709 disabled, perf events will use software events only.
1711 config SYS_SUPPORTS_HUGETLBFS
1715 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1719 config ARCH_WANT_GENERAL_HUGETLB
1722 config ARM_MODULE_PLTS
1723 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1726 Allocate PLTs when loading modules so that jumps and calls whose
1727 targets are too far away for their relative offsets to be encoded
1728 in the instructions themselves can be bounced via veneers in the
1729 module's PLT. This allows modules to be allocated in the generic
1730 vmalloc area after the dedicated module memory area has been
1731 exhausted. The modules will use slightly more memory, but after
1732 rounding up to page size, the actual memory footprint is usually
1735 Say y if you are getting out of memory errors while loading modules
1739 config FORCE_MAX_ZONEORDER
1740 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1741 range 11 64 if ARCH_SHMOBILE_LEGACY
1742 default "12" if SOC_AM33XX
1743 default "9" if SA1111 || ARCH_EFM32
1746 The kernel memory allocator divides physically contiguous memory
1747 blocks into "zones", where each zone is a power of two number of
1748 pages. This option selects the largest power of two that the kernel
1749 keeps in the memory allocator. If you need to allocate very large
1750 blocks of physically contiguous memory, then you may need to
1751 increase this value.
1753 This config option is actually maximum order plus one. For example,
1754 a value of 11 means that the largest free memory block is 2^10 pages.
1756 config ALIGNMENT_TRAP
1758 depends on CPU_CP15_MMU
1759 default y if !ARCH_EBSA110
1760 select HAVE_PROC_CPU if PROC_FS
1762 ARM processors cannot fetch/store information which is not
1763 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1764 address divisible by 4. On 32-bit ARM processors, these non-aligned
1765 fetch/store instructions will be emulated in software if you say
1766 here, which has a severe performance impact. This is necessary for
1767 correct operation of some network protocols. With an IP-only
1768 configuration it is safe to say N, otherwise say Y.
1770 config UACCESS_WITH_MEMCPY
1771 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1773 default y if CPU_FEROCEON
1775 Implement faster copy_to_user and clear_user methods for CPU
1776 cores where a 8-word STM instruction give significantly higher
1777 memory write throughput than a sequence of individual 32bit stores.
1779 A possible side effect is a slight increase in scheduling latency
1780 between threads sharing the same address space if they invoke
1781 such copy operations with large buffers.
1783 However, if the CPU data cache is using a write-allocate mode,
1784 this option is unlikely to provide any performance gain.
1788 prompt "Enable seccomp to safely compute untrusted bytecode"
1790 This kernel feature is useful for number crunching applications
1791 that may need to compute untrusted bytecode during their
1792 execution. By using pipes or other transports made available to
1793 the process as file descriptors supporting the read/write
1794 syscalls, it's possible to isolate those applications in
1795 their own address space using seccomp. Once seccomp is
1796 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1797 and the task is only allowed to execute a few safe syscalls
1798 defined by each seccomp mode.
1811 bool "Xen guest support on ARM"
1812 depends on ARM && AEABI && OF
1813 depends on CPU_V7 && !CPU_V6
1814 depends on !GENERIC_ATOMIC64
1816 select ARCH_DMA_ADDR_T_64BIT
1820 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1827 bool "Flattened Device Tree support"
1830 select OF_EARLY_FLATTREE
1831 select OF_RESERVED_MEM
1833 Include support for flattened device tree machine descriptions.
1836 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1839 This is the traditional way of passing data to the kernel at boot
1840 time. If you are solely relying on the flattened device tree (or
1841 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1842 to remove ATAGS support from your kernel binary. If unsure,
1845 config DEPRECATED_PARAM_STRUCT
1846 bool "Provide old way to pass kernel parameters"
1849 This was deprecated in 2001 and announced to live on for 5 years.
1850 Some old boot loaders still use this way.
1852 # Compressed boot loader in ROM. Yes, we really want to ask about
1853 # TEXT and BSS so we preserve their values in the config files.
1854 config ZBOOT_ROM_TEXT
1855 hex "Compressed ROM boot loader base address"
1858 The physical address at which the ROM-able zImage is to be
1859 placed in the target. Platforms which normally make use of
1860 ROM-able zImage formats normally set this to a suitable
1861 value in their defconfig file.
1863 If ZBOOT_ROM is not enabled, this has no effect.
1865 config ZBOOT_ROM_BSS
1866 hex "Compressed ROM boot loader BSS address"
1869 The base address of an area of read/write memory in the target
1870 for the ROM-able zImage which must be available while the
1871 decompressor is running. It must be large enough to hold the
1872 entire decompressed kernel plus an additional 128 KiB.
1873 Platforms which normally make use of ROM-able zImage formats
1874 normally set this to a suitable value in their defconfig file.
1876 If ZBOOT_ROM is not enabled, this has no effect.
1879 bool "Compressed boot loader in ROM/flash"
1880 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1881 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1883 Say Y here if you intend to execute your compressed kernel image
1884 (zImage) directly from ROM or flash. If unsure, say N.
1886 config ARM_APPENDED_DTB
1887 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1890 With this option, the boot code will look for a device tree binary
1891 (DTB) appended to zImage
1892 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1894 This is meant as a backward compatibility convenience for those
1895 systems with a bootloader that can't be upgraded to accommodate
1896 the documented boot protocol using a device tree.
1898 Beware that there is very little in terms of protection against
1899 this option being confused by leftover garbage in memory that might
1900 look like a DTB header after a reboot if no actual DTB is appended
1901 to zImage. Do not leave this option active in a production kernel
1902 if you don't intend to always append a DTB. Proper passing of the
1903 location into r2 of a bootloader provided DTB is always preferable
1906 config ARM_ATAG_DTB_COMPAT
1907 bool "Supplement the appended DTB with traditional ATAG information"
1908 depends on ARM_APPENDED_DTB
1910 Some old bootloaders can't be updated to a DTB capable one, yet
1911 they provide ATAGs with memory configuration, the ramdisk address,
1912 the kernel cmdline string, etc. Such information is dynamically
1913 provided by the bootloader and can't always be stored in a static
1914 DTB. To allow a device tree enabled kernel to be used with such
1915 bootloaders, this option allows zImage to extract the information
1916 from the ATAG list and store it at run time into the appended DTB.
1919 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1920 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1922 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1923 bool "Use bootloader kernel arguments if available"
1925 Uses the command-line options passed by the boot loader instead of
1926 the device tree bootargs property. If the boot loader doesn't provide
1927 any, the device tree bootargs property will be used.
1929 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1930 bool "Extend with bootloader kernel arguments"
1932 The command-line arguments provided by the boot loader will be
1933 appended to the the device tree bootargs property.
1938 string "Default kernel command string"
1941 On some architectures (EBSA110 and CATS), there is currently no way
1942 for the boot loader to pass arguments to the kernel. For these
1943 architectures, you should supply some command-line options at build
1944 time by entering them here. As a minimum, you should specify the
1945 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1948 prompt "Kernel command line type" if CMDLINE != ""
1949 default CMDLINE_FROM_BOOTLOADER
1952 config CMDLINE_FROM_BOOTLOADER
1953 bool "Use bootloader kernel arguments if available"
1955 Uses the command-line options passed by the boot loader. If
1956 the boot loader doesn't provide any, the default kernel command
1957 string provided in CMDLINE will be used.
1959 config CMDLINE_EXTEND
1960 bool "Extend bootloader kernel arguments"
1962 The command-line arguments provided by the boot loader will be
1963 appended to the default kernel command string.
1965 config CMDLINE_FORCE
1966 bool "Always use the default kernel command string"
1968 Always use the default kernel command string, even if the boot
1969 loader passes other arguments to the kernel.
1970 This is useful if you cannot or don't want to change the
1971 command-line options your boot loader passes to the kernel.
1975 bool "Kernel Execute-In-Place from ROM"
1976 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1978 Execute-In-Place allows the kernel to run from non-volatile storage
1979 directly addressable by the CPU, such as NOR flash. This saves RAM
1980 space since the text section of the kernel is not loaded from flash
1981 to RAM. Read-write sections, such as the data section and stack,
1982 are still copied to RAM. The XIP kernel is not compressed since
1983 it has to run directly from flash, so it will take more space to
1984 store it. The flash address used to link the kernel object files,
1985 and for storing it, is configuration dependent. Therefore, if you
1986 say Y here, you must know the proper physical address where to
1987 store the kernel image depending on your own flash memory usage.
1989 Also note that the make target becomes "make xipImage" rather than
1990 "make zImage" or "make Image". The final kernel binary to put in
1991 ROM memory will be arch/arm/boot/xipImage.
1995 config XIP_PHYS_ADDR
1996 hex "XIP Kernel Physical Location"
1997 depends on XIP_KERNEL
1998 default "0x00080000"
2000 This is the physical address in your flash memory the kernel will
2001 be linked for and stored to. This address is dependent on your
2005 bool "Kexec system call (EXPERIMENTAL)"
2006 depends on (!SMP || PM_SLEEP_SMP)
2009 kexec is a system call that implements the ability to shutdown your
2010 current kernel, and to start another kernel. It is like a reboot
2011 but it is independent of the system firmware. And like a reboot
2012 you can start any kernel with it, not just Linux.
2014 It is an ongoing process to be certain the hardware in a machine
2015 is properly shutdown, so do not be surprised if this code does not
2016 initially work for you.
2019 bool "Export atags in procfs"
2020 depends on ATAGS && KEXEC
2023 Should the atags used to boot the kernel be exported in an "atags"
2024 file in procfs. Useful with kexec.
2027 bool "Build kdump crash kernel (EXPERIMENTAL)"
2029 Generate crash dump after being started by kexec. This should
2030 be normally only set in special crash dump kernels which are
2031 loaded in the main kernel with kexec-tools into a specially
2032 reserved region and then later executed after a crash by
2033 kdump/kexec. The crash dump kernel must be compiled to a
2034 memory address not used by the main kernel
2036 For more details see Documentation/kdump/kdump.txt
2038 config AUTO_ZRELADDR
2039 bool "Auto calculation of the decompressed kernel image address"
2041 ZRELADDR is the physical address where the decompressed kernel
2042 image will be placed. If AUTO_ZRELADDR is selected, the address
2043 will be determined at run-time by masking the current IP with
2044 0xf8000000. This assumes the zImage being placed in the first 128MB
2045 from start of memory.
2049 menu "CPU Power Management"
2051 source "drivers/cpufreq/Kconfig"
2053 source "drivers/cpuidle/Kconfig"
2057 menu "Floating point emulation"
2059 comment "At least one emulation must be selected"
2062 bool "NWFPE math emulation"
2063 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2065 Say Y to include the NWFPE floating point emulator in the kernel.
2066 This is necessary to run most binaries. Linux does not currently
2067 support floating point hardware so you need to say Y here even if
2068 your machine has an FPA or floating point co-processor podule.
2070 You may say N here if you are going to load the Acorn FPEmulator
2071 early in the bootup.
2074 bool "Support extended precision"
2075 depends on FPE_NWFPE
2077 Say Y to include 80-bit support in the kernel floating-point
2078 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2079 Note that gcc does not generate 80-bit operations by default,
2080 so in most cases this option only enlarges the size of the
2081 floating point emulator without any good reason.
2083 You almost surely want to say N here.
2086 bool "FastFPE math emulation (EXPERIMENTAL)"
2087 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2089 Say Y here to include the FAST floating point emulator in the kernel.
2090 This is an experimental much faster emulator which now also has full
2091 precision for the mantissa. It does not support any exceptions.
2092 It is very simple, and approximately 3-6 times faster than NWFPE.
2094 It should be sufficient for most programs. It may be not suitable
2095 for scientific calculations, but you have to check this for yourself.
2096 If you do not feel you need a faster FP emulation you should better
2100 bool "VFP-format floating point maths"
2101 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2103 Say Y to include VFP support code in the kernel. This is needed
2104 if your hardware includes a VFP unit.
2106 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2107 release notes and additional status information.
2109 Say N if your target does not have VFP hardware.
2117 bool "Advanced SIMD (NEON) Extension support"
2118 depends on VFPv3 && CPU_V7
2120 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2123 config KERNEL_MODE_NEON
2124 bool "Support for NEON in kernel mode"
2125 depends on NEON && AEABI
2127 Say Y to include support for NEON in kernel mode.
2131 menu "Userspace binary formats"
2133 source "fs/Kconfig.binfmt"
2137 menu "Power management options"
2139 source "kernel/power/Kconfig"
2141 config ARCH_SUSPEND_POSSIBLE
2142 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2143 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2146 config ARM_CPU_SUSPEND
2149 config ARCH_HIBERNATION_POSSIBLE
2152 default y if ARCH_SUSPEND_POSSIBLE
2156 source "net/Kconfig"
2158 source "drivers/Kconfig"
2160 source "drivers/firmware/Kconfig"
2164 source "arch/arm/Kconfig.debug"
2166 source "security/Kconfig"
2168 source "crypto/Kconfig"
2170 source "arch/arm/crypto/Kconfig"
2173 source "lib/Kconfig"
2175 source "arch/arm/kvm/Kconfig"