5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
47 config SYS_SUPPORTS_APM_EMULATION
50 config HAVE_SCHED_CLOCK
56 config ARCH_USES_GETTIMEOFFSET
60 config GENERIC_CLOCKEVENTS
63 config GENERIC_CLOCKEVENTS_BROADCAST
65 depends on GENERIC_CLOCKEVENTS
74 select GENERIC_ALLOCATOR
85 The Extended Industry Standard Architecture (EISA) bus was
86 developed as an open alternative to the IBM MicroChannel bus.
88 The EISA bus provided some of the features of the IBM MicroChannel
89 bus while maintaining backward compatibility with cards made for
90 the older ISA bus. The EISA bus saw limited use between 1988 and
91 1995 when it was made obsolete by the PCI bus.
93 Say Y here if you are building a kernel for an EISA-based machine.
103 MicroChannel Architecture is found in some IBM PS/2 machines and
104 laptops. It is a bus system similar to PCI or ISA. See
105 <file:Documentation/mca.txt> (and especially the web page given
106 there) before attempting to build an MCA bus kernel.
108 config STACKTRACE_SUPPORT
112 config HAVE_LATENCYTOP_SUPPORT
117 config LOCKDEP_SUPPORT
121 config TRACE_IRQFLAGS_SUPPORT
125 config HARDIRQS_SW_RESEND
129 config GENERIC_IRQ_PROBE
133 config GENERIC_LOCKBREAK
136 depends on SMP && PREEMPT
138 config RWSEM_GENERIC_SPINLOCK
142 config RWSEM_XCHGADD_ALGORITHM
145 config ARCH_HAS_ILOG2_U32
148 config ARCH_HAS_ILOG2_U64
151 config ARCH_HAS_CPUFREQ
154 Internal node to signify that the ARCH has CPUFREQ support
155 and that the relevant menu configurations are displayed for
158 config ARCH_HAS_CPU_IDLE_WAIT
161 config GENERIC_HWEIGHT
165 config GENERIC_CALIBRATE_DELAY
169 config ARCH_MAY_HAVE_PC_FDC
175 config NEED_DMA_MAP_STATE
178 config GENERIC_ISA_DMA
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
197 depends on EXPERIMENTAL
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary, or theoretically 64K
207 for the MSM machine class.
209 config ARM_PATCH_PHYS_VIRT_16BIT
211 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
213 This option extends the physical to virtual translation patching
214 to allow physical memory down to a theoretical minimum of 64K
217 source "init/Kconfig"
219 source "kernel/Kconfig.freezer"
224 bool "MMU-based Paged Memory Management Support"
227 Select if you want MMU-based virtualised addressing space
228 support by paged memory management. If unsure, say 'Y'.
231 # The "ARM system type" choice list is ordered alphabetically by option
232 # text. Please add new entries in the option alphabetic order.
235 prompt "ARM system type"
236 default ARCH_VERSATILE
238 config ARCH_INTEGRATOR
239 bool "ARM Ltd. Integrator family"
241 select ARCH_HAS_CPUFREQ
244 select GENERIC_CLOCKEVENTS
245 select PLAT_VERSATILE
246 select PLAT_VERSATILE_FPGA_IRQ
248 Support for ARM's Integrator platform.
251 bool "ARM Ltd. RealView family"
255 select GENERIC_CLOCKEVENTS
256 select ARCH_WANT_OPTIONAL_GPIOLIB
257 select PLAT_VERSATILE
258 select PLAT_VERSATILE_CLCD
259 select ARM_TIMER_SP804
260 select GPIO_PL061 if GPIOLIB
262 This enables support for ARM Ltd RealView boards.
264 config ARCH_VERSATILE
265 bool "ARM Ltd. Versatile family"
270 select GENERIC_CLOCKEVENTS
271 select ARCH_WANT_OPTIONAL_GPIOLIB
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_CLCD
274 select PLAT_VERSATILE_FPGA_IRQ
275 select ARM_TIMER_SP804
277 This enables support for ARM Ltd Versatile board.
280 bool "ARM Ltd. Versatile Express family"
281 select ARCH_WANT_OPTIONAL_GPIOLIB
283 select ARM_TIMER_SP804
285 select GENERIC_CLOCKEVENTS
287 select HAVE_PATA_PLATFORM
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
292 This enables support for the ARM Ltd Versatile Express boards.
296 select ARCH_REQUIRE_GPIOLIB
299 select ARM_PATCH_PHYS_VIRT if MMU
301 This enables support for systems based on the Atmel AT91RM9200,
302 AT91SAM9 and AT91CAP9 processors.
305 bool "Broadcom BCMRING"
309 select ARM_TIMER_SP804
311 select GENERIC_CLOCKEVENTS
312 select ARCH_WANT_OPTIONAL_GPIOLIB
314 Support for Broadcom's BCMRing platform.
317 bool "Cirrus Logic CLPS711x/EP721x-based"
319 select ARCH_USES_GETTIMEOFFSET
321 Support for Cirrus Logic 711x/721x based boards.
324 bool "Cavium Networks CNS3XXX family"
326 select GENERIC_CLOCKEVENTS
328 select MIGHT_HAVE_PCI
329 select PCI_DOMAINS if PCI
331 Support for Cavium Networks CNS3XXX platform.
334 bool "Cortina Systems Gemini"
336 select ARCH_REQUIRE_GPIOLIB
337 select ARCH_USES_GETTIMEOFFSET
339 Support for the Cortina Systems Gemini family SoCs
346 select ARCH_USES_GETTIMEOFFSET
348 This is an evaluation board for the StrongARM processor available
349 from Digital. It has limited hardware on-board, including an
350 Ethernet interface, two PCMCIA sockets, two serial ports and a
359 select ARCH_REQUIRE_GPIOLIB
360 select ARCH_HAS_HOLES_MEMORYMODEL
361 select ARCH_USES_GETTIMEOFFSET
363 This enables support for the Cirrus EP93xx series of CPUs.
365 config ARCH_FOOTBRIDGE
369 select GENERIC_CLOCKEVENTS
371 Support for systems based on the DC21285 companion chip
372 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
375 bool "Freescale MXC/iMX-based"
376 select GENERIC_CLOCKEVENTS
377 select ARCH_REQUIRE_GPIOLIB
380 select HAVE_SCHED_CLOCK
382 Support for Freescale MXC/iMX-based family of processors
385 bool "Freescale MXS-based"
386 select GENERIC_CLOCKEVENTS
387 select ARCH_REQUIRE_GPIOLIB
391 Support for Freescale MXS-based family of processors
394 bool "Hilscher NetX based"
398 select GENERIC_CLOCKEVENTS
400 This enables support for systems based on the Hilscher NetX Soc
403 bool "Hynix HMS720x-based"
406 select ARCH_USES_GETTIMEOFFSET
408 This enables support for systems based on the Hynix HMS720x
416 select ARCH_SUPPORTS_MSI
419 Support for Intel's IOP13XX (XScale) family of processors.
427 select ARCH_REQUIRE_GPIOLIB
429 Support for Intel's 80219 and IOP32X (XScale) family of
438 select ARCH_REQUIRE_GPIOLIB
440 Support for Intel's IOP33X (XScale) family of processors.
447 select ARCH_USES_GETTIMEOFFSET
449 Support for Intel's IXP23xx (XScale) family of processors.
452 bool "IXP2400/2800-based"
456 select ARCH_USES_GETTIMEOFFSET
458 Support for Intel's IXP2400/2800 (XScale) family of processors.
466 select GENERIC_CLOCKEVENTS
467 select HAVE_SCHED_CLOCK
468 select MIGHT_HAVE_PCI
469 select DMABOUNCE if PCI
471 Support for Intel's IXP4XX (XScale) family of processors.
477 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
481 Support for the Marvell Dove SoC 88AP510
484 bool "Marvell Kirkwood"
487 select ARCH_REQUIRE_GPIOLIB
488 select GENERIC_CLOCKEVENTS
491 Support for the following Marvell Kirkwood series SoCs:
492 88F6180, 88F6192 and 88F6281.
495 bool "Marvell Loki (88RC8480)"
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Loki (88RC8480) SoC.
506 select ARCH_REQUIRE_GPIOLIB
509 select USB_ARCH_HAS_OHCI
512 select GENERIC_CLOCKEVENTS
514 Support for the NXP LPC32XX family of processors
517 bool "Marvell MV78xx0"
520 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
524 Support for the following Marvell MV78xx0 series SoCs:
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
536 Support for the following Marvell Orion 5x series SoCs:
537 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
538 Orion-2 (5281), Orion-1-90 (6183).
541 bool "Marvell PXA168/910/MMP2"
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
546 select HAVE_SCHED_CLOCK
551 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
554 bool "Micrel/Kendin KS8695"
556 select ARCH_REQUIRE_GPIOLIB
557 select ARCH_USES_GETTIMEOFFSET
559 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
560 System-on-Chip devices.
563 bool "Nuvoton W90X900 CPU"
565 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
570 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
571 At present, the w90x900 has been renamed nuc900, regarding
572 the ARM series product line, you can login the following
573 link address to know more.
575 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
576 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
579 bool "Nuvoton NUC93X CPU"
583 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
584 low-power and high performance MPEG-4/JPEG multimedia controller chip.
591 select GENERIC_CLOCKEVENTS
594 select HAVE_SCHED_CLOCK
595 select ARCH_HAS_BARRIERS if CACHE_L2X0
596 select ARCH_HAS_CPUFREQ
598 This enables support for NVIDIA Tegra based systems (Tegra APX,
599 Tegra 6xx and Tegra 2 series).
602 bool "Philips Nexperia PNX4008 Mobile"
605 select ARCH_USES_GETTIMEOFFSET
607 This enables support for Philips PNX4008 mobile platform.
610 bool "PXA2xx/PXA3xx-based"
613 select ARCH_HAS_CPUFREQ
616 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
618 select HAVE_SCHED_CLOCK
623 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
628 select GENERIC_CLOCKEVENTS
629 select ARCH_REQUIRE_GPIOLIB
632 Support for Qualcomm MSM/QSD based systems. This runs on the
633 apps processor of the MSM/QSD and depends on a shared memory
634 interface to the modem processor which runs the baseband
635 stack and controls some vital subsystems
636 (clock and power control, etc).
639 bool "Renesas SH-Mobile / R-Mobile"
642 select GENERIC_CLOCKEVENTS
645 select MULTI_IRQ_HANDLER
647 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
654 select ARCH_MAY_HAVE_PC_FDC
655 select HAVE_PATA_PLATFORM
658 select ARCH_SPARSEMEM_ENABLE
659 select ARCH_USES_GETTIMEOFFSET
661 On the Acorn Risc-PC, Linux can support the internal IDE disk and
662 CD-ROM interface, serial and parallel port, and the floppy drive.
669 select ARCH_SPARSEMEM_ENABLE
671 select ARCH_HAS_CPUFREQ
673 select GENERIC_CLOCKEVENTS
675 select HAVE_SCHED_CLOCK
677 select ARCH_REQUIRE_GPIOLIB
679 Support for StrongARM 11x0 based boards.
682 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
684 select ARCH_HAS_CPUFREQ
686 select ARCH_USES_GETTIMEOFFSET
687 select HAVE_S3C2410_I2C if I2C
689 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
690 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
691 the Samsung SMDK2410 development board (and derivatives).
693 Note, the S3C2416 and the S3C2450 are so close that they even share
694 the same SoC ID code. This means that there is no separate machine
695 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
698 bool "Samsung S3C64XX"
704 select ARCH_USES_GETTIMEOFFSET
705 select ARCH_HAS_CPUFREQ
706 select ARCH_REQUIRE_GPIOLIB
707 select SAMSUNG_CLKSRC
708 select SAMSUNG_IRQ_VIC_TIMER
709 select SAMSUNG_IRQ_UART
710 select S3C_GPIO_TRACK
711 select S3C_GPIO_PULL_UPDOWN
712 select S3C_GPIO_CFG_S3C24XX
713 select S3C_GPIO_CFG_S3C64XX
715 select USB_ARCH_HAS_OHCI
716 select SAMSUNG_GPIOLIB_4BIT
717 select HAVE_S3C2410_I2C if I2C
718 select HAVE_S3C2410_WATCHDOG if WATCHDOG
720 Samsung S3C64XX series based systems
723 bool "Samsung S5P6440 S5P6450"
727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
728 select GENERIC_CLOCKEVENTS
729 select HAVE_SCHED_CLOCK
730 select HAVE_S3C2410_I2C if I2C
731 select HAVE_S3C_RTC if RTC_CLASS
733 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
737 bool "Samsung S5PC100"
741 select ARM_L1_CACHE_SHIFT_6
742 select ARCH_USES_GETTIMEOFFSET
743 select HAVE_S3C2410_I2C if I2C
744 select HAVE_S3C_RTC if RTC_CLASS
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 Samsung S5PC100 series based systems
750 bool "Samsung S5PV210/S5PC110"
752 select ARCH_SPARSEMEM_ENABLE
755 select ARM_L1_CACHE_SHIFT_6
756 select ARCH_HAS_CPUFREQ
757 select GENERIC_CLOCKEVENTS
758 select HAVE_SCHED_CLOCK
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C_RTC if RTC_CLASS
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 Samsung S5PV210/S5PC110 series based systems
766 bool "Samsung EXYNOS4"
768 select ARCH_SPARSEMEM_ENABLE
771 select ARCH_HAS_CPUFREQ
772 select GENERIC_CLOCKEVENTS
773 select HAVE_S3C_RTC if RTC_CLASS
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 Samsung EXYNOS4 series based systems
786 select ARCH_USES_GETTIMEOFFSET
788 Support for the StrongARM based Digital DNARD machine, also known
789 as "Shark" (<http://www.shark-linux.de/shark.html>).
792 bool "Telechips TCC ARM926-based systems"
797 select GENERIC_CLOCKEVENTS
799 Support for Telechips TCC ARM926-based systems.
802 bool "ST-Ericsson U300 Series"
806 select HAVE_SCHED_CLOCK
810 select GENERIC_CLOCKEVENTS
814 Support for ST-Ericsson U300 series mobile platforms.
817 bool "ST-Ericsson U8500 Series"
820 select GENERIC_CLOCKEVENTS
822 select ARCH_REQUIRE_GPIOLIB
823 select ARCH_HAS_CPUFREQ
825 Support for ST-Ericsson's Ux500 architecture
828 bool "STMicroelectronics Nomadik"
833 select GENERIC_CLOCKEVENTS
834 select ARCH_REQUIRE_GPIOLIB
836 Support for the Nomadik platform by ST-Ericsson
840 select GENERIC_CLOCKEVENTS
841 select ARCH_REQUIRE_GPIOLIB
845 select GENERIC_ALLOCATOR
846 select GENERIC_IRQ_CHIP
847 select ARCH_HAS_HOLES_MEMORYMODEL
849 Support for TI's DaVinci platform.
854 select ARCH_REQUIRE_GPIOLIB
855 select ARCH_HAS_CPUFREQ
856 select GENERIC_CLOCKEVENTS
857 select HAVE_SCHED_CLOCK
858 select ARCH_HAS_HOLES_MEMORYMODEL
860 Support for TI's OMAP platform (OMAP1/2/3/4).
863 bool "Rockchip RK29xx"
870 select ARM_L1_CACHE_SHIFT_6
872 Support for Rockchip's RK29xx SoCs.
875 bool "Rockchip RK2928"
880 select MIGHT_HAVE_CACHE_L2X0
881 select ARM_ERRATA_754322
883 Support for Rockchip's RK2928 SoCs.
886 bool "Rockchip RK30xx"
892 select MIGHT_HAVE_CACHE_L2X0
893 select ARM_ERRATA_764369
894 select ARM_ERRATA_754322
896 Support for Rockchip's RK30xx SoCs.
899 bool "Rockchip RK31xx"
905 select MIGHT_HAVE_CACHE_L2X0
906 select ARM_ERRATA_764369
907 select ARM_ERRATA_754322
909 Support for Rockchip's RK31xx SoCs.
914 select ARCH_REQUIRE_GPIOLIB
917 select GENERIC_CLOCKEVENTS
920 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
923 bool "VIA/WonderMedia 85xx"
926 select ARCH_HAS_CPUFREQ
927 select GENERIC_CLOCKEVENTS
928 select ARCH_REQUIRE_GPIOLIB
931 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
935 # This is sorted alphabetically by mach-* pathname. However, plat-*
936 # Kconfigs may be included either alphabetically (according to the
937 # plat- suffix) or along side the corresponding mach-* source.
939 source "arch/arm/mach-at91/Kconfig"
941 source "arch/arm/mach-bcmring/Kconfig"
943 source "arch/arm/mach-clps711x/Kconfig"
945 source "arch/arm/mach-cns3xxx/Kconfig"
947 source "arch/arm/mach-davinci/Kconfig"
949 source "arch/arm/mach-dove/Kconfig"
951 source "arch/arm/mach-ep93xx/Kconfig"
953 source "arch/arm/mach-footbridge/Kconfig"
955 source "arch/arm/mach-gemini/Kconfig"
957 source "arch/arm/mach-h720x/Kconfig"
959 source "arch/arm/mach-integrator/Kconfig"
961 source "arch/arm/mach-iop32x/Kconfig"
963 source "arch/arm/mach-iop33x/Kconfig"
965 source "arch/arm/mach-iop13xx/Kconfig"
967 source "arch/arm/mach-ixp4xx/Kconfig"
969 source "arch/arm/mach-ixp2000/Kconfig"
971 source "arch/arm/mach-ixp23xx/Kconfig"
973 source "arch/arm/mach-kirkwood/Kconfig"
975 source "arch/arm/mach-ks8695/Kconfig"
977 source "arch/arm/mach-loki/Kconfig"
979 source "arch/arm/mach-lpc32xx/Kconfig"
981 source "arch/arm/mach-msm/Kconfig"
983 source "arch/arm/mach-mv78xx0/Kconfig"
985 source "arch/arm/plat-mxc/Kconfig"
987 source "arch/arm/mach-mxs/Kconfig"
989 source "arch/arm/mach-netx/Kconfig"
991 source "arch/arm/mach-nomadik/Kconfig"
992 source "arch/arm/plat-nomadik/Kconfig"
994 source "arch/arm/mach-nuc93x/Kconfig"
996 source "arch/arm/plat-omap/Kconfig"
998 source "arch/arm/mach-omap1/Kconfig"
1000 source "arch/arm/mach-omap2/Kconfig"
1002 source "arch/arm/mach-orion5x/Kconfig"
1004 source "arch/arm/mach-pxa/Kconfig"
1005 source "arch/arm/plat-pxa/Kconfig"
1007 source "arch/arm/mach-mmp/Kconfig"
1009 source "arch/arm/mach-realview/Kconfig"
1011 source "arch/arm/plat-rk/Kconfig"
1012 source "arch/arm/mach-rk29/Kconfig"
1013 source "arch/arm/mach-rk2928/Kconfig"
1014 source "arch/arm/mach-rk30/Kconfig"
1016 source "arch/arm/mach-sa1100/Kconfig"
1018 source "arch/arm/plat-samsung/Kconfig"
1019 source "arch/arm/plat-s3c24xx/Kconfig"
1020 source "arch/arm/plat-s5p/Kconfig"
1022 source "arch/arm/plat-spear/Kconfig"
1024 source "arch/arm/plat-tcc/Kconfig"
1027 source "arch/arm/mach-s3c2400/Kconfig"
1028 source "arch/arm/mach-s3c2410/Kconfig"
1029 source "arch/arm/mach-s3c2412/Kconfig"
1030 source "arch/arm/mach-s3c2416/Kconfig"
1031 source "arch/arm/mach-s3c2440/Kconfig"
1032 source "arch/arm/mach-s3c2443/Kconfig"
1036 source "arch/arm/mach-s3c64xx/Kconfig"
1039 source "arch/arm/mach-s5p64x0/Kconfig"
1041 source "arch/arm/mach-s5pc100/Kconfig"
1043 source "arch/arm/mach-s5pv210/Kconfig"
1045 source "arch/arm/mach-exynos4/Kconfig"
1047 source "arch/arm/mach-shmobile/Kconfig"
1049 source "arch/arm/mach-tegra/Kconfig"
1051 source "arch/arm/mach-u300/Kconfig"
1053 source "arch/arm/mach-ux500/Kconfig"
1055 source "arch/arm/mach-versatile/Kconfig"
1057 source "arch/arm/mach-vexpress/Kconfig"
1058 source "arch/arm/plat-versatile/Kconfig"
1060 source "arch/arm/mach-vt8500/Kconfig"
1062 source "arch/arm/mach-w90x900/Kconfig"
1064 # Definitions to make life easier
1070 select GENERIC_CLOCKEVENTS
1071 select HAVE_SCHED_CLOCK
1076 select GENERIC_IRQ_CHIP
1077 select HAVE_SCHED_CLOCK
1084 select CLKDEV_LOOKUP
1085 select HAVE_SCHED_CLOCK
1086 select ARCH_HAS_CPUFREQ
1087 select GENERIC_CLOCKEVENTS
1088 select ARCH_REQUIRE_GPIOLIB
1090 config PLAT_VERSATILE
1093 config ARM_TIMER_SP804
1097 source arch/arm/mm/Kconfig
1100 bool "Enable iWMMXt support"
1101 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1102 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1104 Enable support for iWMMXt context switching at run time if
1105 running on a CPU that supports it.
1107 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1110 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1114 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1115 (!ARCH_OMAP3 || OMAP3_EMU)
1119 config MULTI_IRQ_HANDLER
1122 Allow each machine to specify it's own IRQ handler at run time.
1125 source "arch/arm/Kconfig-nommu"
1128 config ARM_ERRATA_411920
1129 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1130 depends on CPU_V6 || CPU_V6K
1132 Invalidation of the Instruction Cache operation can
1133 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1134 It does not affect the MPCore. This option enables the ARM Ltd.
1135 recommended workaround.
1137 config ARM_ERRATA_430973
1138 bool "ARM errata: Stale prediction on replaced interworking branch"
1141 This option enables the workaround for the 430973 Cortex-A8
1142 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1143 interworking branch is replaced with another code sequence at the
1144 same virtual address, whether due to self-modifying code or virtual
1145 to physical address re-mapping, Cortex-A8 does not recover from the
1146 stale interworking branch prediction. This results in Cortex-A8
1147 executing the new code sequence in the incorrect ARM or Thumb state.
1148 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1149 and also flushes the branch target cache at every context switch.
1150 Note that setting specific bits in the ACTLR register may not be
1151 available in non-secure mode.
1153 config ARM_ERRATA_458693
1154 bool "ARM errata: Processor deadlock when a false hazard is created"
1157 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1158 erratum. For very specific sequences of memory operations, it is
1159 possible for a hazard condition intended for a cache line to instead
1160 be incorrectly associated with a different cache line. This false
1161 hazard might then cause a processor deadlock. The workaround enables
1162 the L1 caching of the NEON accesses and disables the PLD instruction
1163 in the ACTLR register. Note that setting specific bits in the ACTLR
1164 register may not be available in non-secure mode.
1166 config ARM_ERRATA_460075
1167 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1170 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1171 erratum. Any asynchronous access to the L2 cache may encounter a
1172 situation in which recent store transactions to the L2 cache are lost
1173 and overwritten with stale memory contents from external memory. The
1174 workaround disables the write-allocate mode for the L2 cache via the
1175 ACTLR register. Note that setting specific bits in the ACTLR register
1176 may not be available in non-secure mode.
1178 config ARM_ERRATA_742230
1179 bool "ARM errata: DMB operation may be faulty"
1180 depends on CPU_V7 && SMP
1182 This option enables the workaround for the 742230 Cortex-A9
1183 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1184 between two write operations may not ensure the correct visibility
1185 ordering of the two writes. This workaround sets a specific bit in
1186 the diagnostic register of the Cortex-A9 which causes the DMB
1187 instruction to behave as a DSB, ensuring the correct behaviour of
1190 config ARM_ERRATA_742231
1191 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1192 depends on CPU_V7 && SMP
1194 This option enables the workaround for the 742231 Cortex-A9
1195 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1196 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1197 accessing some data located in the same cache line, may get corrupted
1198 data due to bad handling of the address hazard when the line gets
1199 replaced from one of the CPUs at the same time as another CPU is
1200 accessing it. This workaround sets specific bits in the diagnostic
1201 register of the Cortex-A9 which reduces the linefill issuing
1202 capabilities of the processor.
1204 config PL310_ERRATA_588369
1205 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1206 depends on CACHE_L2X0
1208 The PL310 L2 cache controller implements three types of Clean &
1209 Invalidate maintenance operations: by Physical Address
1210 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1211 They are architecturally defined to behave as the execution of a
1212 clean operation followed immediately by an invalidate operation,
1213 both performing to the same memory location. This functionality
1214 is not correctly implemented in PL310 as clean lines are not
1215 invalidated as a result of these operations.
1217 config ARM_ERRATA_720789
1218 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1219 depends on CPU_V7 && SMP
1221 This option enables the workaround for the 720789 Cortex-A9 (prior to
1222 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1223 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1224 As a consequence of this erratum, some TLB entries which should be
1225 invalidated are not, resulting in an incoherency in the system page
1226 tables. The workaround changes the TLB flushing routines to invalidate
1227 entries regardless of the ASID.
1229 config PL310_ERRATA_727915
1230 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1231 depends on CACHE_L2X0
1233 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1234 operation (offset 0x7FC). This operation runs in background so that
1235 PL310 can handle normal accesses while it is in progress. Under very
1236 rare circumstances, due to this erratum, write data can be lost when
1237 PL310 treats a cacheable write transaction during a Clean &
1238 Invalidate by Way operation.
1240 config ARM_ERRATA_743622
1241 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1244 This option enables the workaround for the 743622 Cortex-A9
1245 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1246 optimisation in the Cortex-A9 Store Buffer may lead to data
1247 corruption. This workaround sets a specific bit in the diagnostic
1248 register of the Cortex-A9 which disables the Store Buffer
1249 optimisation, preventing the defect from occurring. This has no
1250 visible impact on the overall performance or power consumption of the
1253 config ARM_ERRATA_751472
1254 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1255 depends on CPU_V7 && SMP
1257 This option enables the workaround for the 751472 Cortex-A9 (prior
1258 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1259 completion of a following broadcasted operation if the second
1260 operation is received by a CPU before the ICIALLUIS has completed,
1261 potentially leading to corrupted entries in the cache or TLB.
1263 config ARM_ERRATA_753970
1264 bool "ARM errata: cache sync operation may be faulty"
1265 depends on CACHE_PL310
1267 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1269 Under some condition the effect of cache sync operation on
1270 the store buffer still remains when the operation completes.
1271 This means that the store buffer is always asked to drain and
1272 this prevents it from merging any further writes. The workaround
1273 is to replace the normal offset of cache sync operation (0x730)
1274 by another offset targeting an unmapped PL310 register 0x740.
1275 This has the same effect as the cache sync operation: store buffer
1276 drain and waiting for all buffers empty.
1278 config ARM_ERRATA_754322
1279 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1282 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1283 r3p*) erratum. A speculative memory access may cause a page table walk
1284 which starts prior to an ASID switch but completes afterwards. This
1285 can populate the micro-TLB with a stale entry which may be hit with
1286 the new ASID. This workaround places two dsb instructions in the mm
1287 switching code so that no page table walks can cross the ASID switch.
1289 config ARM_ERRATA_754327
1290 bool "ARM errata: no automatic Store Buffer drain"
1291 depends on CPU_V7 && SMP
1293 This option enables the workaround for the 754327 Cortex-A9 (prior to
1294 r2p0) erratum. The Store Buffer does not have any automatic draining
1295 mechanism and therefore a livelock may occur if an external agent
1296 continuously polls a memory location waiting to observe an update.
1297 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1298 written polling loops from denying visibility of updates to memory.
1302 source "arch/arm/common/Kconfig"
1312 Find out whether you have ISA slots on your motherboard. ISA is the
1313 name of a bus system, i.e. the way the CPU talks to the other stuff
1314 inside your box. Other bus systems are PCI, EISA, MicroChannel
1315 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1316 newer boards don't support it. If you have ISA, say Y, otherwise N.
1318 # Select ISA DMA controller support
1323 # Select ISA DMA interface
1328 bool "PCI support" if MIGHT_HAVE_PCI
1330 Find out whether you have a PCI motherboard. PCI is the name of a
1331 bus system, i.e. the way the CPU talks to the other stuff inside
1332 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1333 VESA. If you have PCI, say Y, otherwise N.
1339 config PCI_NANOENGINE
1340 bool "BSE nanoEngine PCI support"
1341 depends on SA1100_NANOENGINE
1343 Enable PCI on the BSE nanoEngine board.
1348 # Select the host bridge type
1349 config PCI_HOST_VIA82C505
1351 depends on PCI && ARCH_SHARK
1354 config PCI_HOST_ITE8152
1356 depends on PCI && MACH_ARMCORE
1360 source "drivers/pci/Kconfig"
1362 source "drivers/pcmcia/Kconfig"
1364 config ARM_ERRATA_764369
1365 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1366 depends on CPU_V7 && SMP
1368 This option enables the workaround for erratum 764369
1369 affecting Cortex-A9 MPCore with two or more processors (all
1370 current revisions). Under certain timing circumstances, a data
1371 cache line maintenance operation by MVA targeting an Inner
1372 Shareable memory region may fail to proceed up to either the
1373 Point of Coherency or to the Point of Unification of the
1374 system. This workaround adds a DSB instruction before the
1375 relevant cache maintenance functions and sets a specific bit
1376 in the diagnostic control register of the SCU.
1380 menu "Kernel Features"
1382 source "kernel/time/Kconfig"
1387 This option should be selected by machines which have an SMP-
1390 The only effect of this option is to make the SMP-related
1391 options available to the user for configuration.
1394 bool "Symmetric Multi-Processing"
1395 depends on CPU_V6K || CPU_V7
1396 depends on GENERIC_CLOCKEVENTS
1399 select USE_GENERIC_SMP_HELPERS
1400 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1402 This enables support for systems with more than one CPU. If you have
1403 a system with only one CPU, like most personal computers, say N. If
1404 you have a system with more than one CPU, say Y.
1406 If you say N here, the kernel will run on single and multiprocessor
1407 machines, but will use only one CPU of a multiprocessor machine. If
1408 you say Y here, the kernel will run on many, but not all, single
1409 processor machines. On a single processor machine, the kernel will
1410 run faster if you say N here.
1412 See also <file:Documentation/i386/IO-APIC.txt>,
1413 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1414 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1416 If you don't know what to do here, say N.
1419 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1420 depends on EXPERIMENTAL
1421 depends on SMP && !XIP_KERNEL
1424 SMP kernels contain instructions which fail on non-SMP processors.
1425 Enabling this option allows the kernel to modify itself to make
1426 these instructions safe. Disabling it allows about 1K of space
1429 If you don't know what to do here, say Y.
1435 This option enables support for the ARM system coherency unit
1442 This options enables support for the ARM timer and watchdog unit
1445 prompt "Memory split"
1448 Select the desired split between kernel and user memory.
1450 If you are not absolutely sure what you are doing, leave this
1454 bool "3G/1G user/kernel split"
1456 bool "2G/2G user/kernel split"
1458 bool "1G/3G user/kernel split"
1463 default 0x40000000 if VMSPLIT_1G
1464 default 0x80000000 if VMSPLIT_2G
1468 int "Maximum number of CPUs (2-32)"
1474 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1475 depends on SMP && HOTPLUG && EXPERIMENTAL
1477 Say Y here to experiment with turning CPUs off and on. CPUs
1478 can be controlled through /sys/devices/system/cpu.
1481 bool "Use local timer interrupts"
1484 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1486 Enable support for local timers on SMP platforms, rather then the
1487 legacy IPI broadcast method. Local timers allows the system
1488 accounting to be spread across the timer interval, preventing a
1489 "thundering herd" at every timer tick.
1491 source kernel/Kconfig.preempt
1495 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1496 ARCH_S5PV210 || ARCH_EXYNOS4
1497 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1498 default AT91_TIMER_HZ if ARCH_AT91
1499 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1502 config THUMB2_KERNEL
1503 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1504 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1506 select ARM_ASM_UNIFIED
1508 By enabling this option, the kernel will be compiled in
1509 Thumb-2 mode. A compiler/assembler that understand the unified
1510 ARM-Thumb syntax is needed.
1514 config THUMB2_AVOID_R_ARM_THM_JUMP11
1515 bool "Work around buggy Thumb-2 short branch relocations in gas"
1516 depends on THUMB2_KERNEL && MODULES
1519 Various binutils versions can resolve Thumb-2 branches to
1520 locally-defined, preemptible global symbols as short-range "b.n"
1521 branch instructions.
1523 This is a problem, because there's no guarantee the final
1524 destination of the symbol, or any candidate locations for a
1525 trampoline, are within range of the branch. For this reason, the
1526 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1527 relocation in modules at all, and it makes little sense to add
1530 The symptom is that the kernel fails with an "unsupported
1531 relocation" error when loading some modules.
1533 Until fixed tools are available, passing
1534 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1535 code which hits this problem, at the cost of a bit of extra runtime
1536 stack usage in some cases.
1538 The problem is described in more detail at:
1539 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1541 Only Thumb-2 kernels are affected.
1543 Unless you are sure your tools don't have this problem, say Y.
1545 config ARM_ASM_UNIFIED
1549 bool "Use the ARM EABI to compile the kernel"
1551 This option allows for the kernel to be compiled using the latest
1552 ARM ABI (aka EABI). This is only useful if you are using a user
1553 space environment that is also compiled with EABI.
1555 Since there are major incompatibilities between the legacy ABI and
1556 EABI, especially with regard to structure member alignment, this
1557 option also changes the kernel syscall calling convention to
1558 disambiguate both ABIs and allow for backward compatibility support
1559 (selected with CONFIG_OABI_COMPAT).
1561 To use this you need GCC version 4.0.0 or later.
1564 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1565 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1568 This option preserves the old syscall interface along with the
1569 new (ARM EABI) one. It also provides a compatibility layer to
1570 intercept syscalls that have structure arguments which layout
1571 in memory differs between the legacy ABI and the new ARM EABI
1572 (only for non "thumb" binaries). This option adds a tiny
1573 overhead to all syscalls and produces a slightly larger kernel.
1574 If you know you'll be using only pure EABI user space then you
1575 can say N here. If this option is not selected and you attempt
1576 to execute a legacy ABI binary then the result will be
1577 UNPREDICTABLE (in fact it can be predicted that it won't work
1578 at all). If in doubt say Y.
1580 config ARCH_HAS_HOLES_MEMORYMODEL
1583 config ARCH_SPARSEMEM_ENABLE
1586 config ARCH_SPARSEMEM_DEFAULT
1587 def_bool ARCH_SPARSEMEM_ENABLE
1589 config ARCH_SELECT_MEMORY_MODEL
1590 def_bool ARCH_SPARSEMEM_ENABLE
1592 config HAVE_ARCH_PFN_VALID
1593 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1596 bool "High Memory Support"
1599 The address space of ARM processors is only 4 Gigabytes large
1600 and it has to accommodate user address space, kernel address
1601 space as well as some memory mapped IO. That means that, if you
1602 have a large amount of physical memory and/or IO, not all of the
1603 memory can be "permanently mapped" by the kernel. The physical
1604 memory that is not permanently mapped is called "high memory".
1606 Depending on the selected kernel/user memory split, minimum
1607 vmalloc space and actual amount of RAM, you may not need this
1608 option which should result in a slightly faster kernel.
1613 bool "Allocate 2nd-level pagetables from highmem"
1616 config HW_PERF_EVENTS
1617 bool "Enable hardware performance counter support for perf events"
1618 depends on PERF_EVENTS && CPU_HAS_PMU
1621 Enable hardware performance counter support for perf events. If
1622 disabled, perf events will use software events only.
1626 config FORCE_MAX_ZONEORDER
1627 int "Maximum zone order" if ARCH_SHMOBILE
1628 range 11 64 if ARCH_SHMOBILE
1629 default "9" if SA1111
1632 The kernel memory allocator divides physically contiguous memory
1633 blocks into "zones", where each zone is a power of two number of
1634 pages. This option selects the largest power of two that the kernel
1635 keeps in the memory allocator. If you need to allocate very large
1636 blocks of physically contiguous memory, then you may need to
1637 increase this value.
1639 This config option is actually maximum order plus one. For example,
1640 a value of 11 means that the largest free memory block is 2^10 pages.
1643 bool "Timer and CPU usage LEDs"
1644 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1645 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1646 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1647 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1648 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1649 ARCH_AT91 || ARCH_DAVINCI || \
1650 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1652 If you say Y here, the LEDs on your machine will be used
1653 to provide useful information about your current system status.
1655 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1656 be able to select which LEDs are active using the options below. If
1657 you are compiling a kernel for the EBSA-110 or the LART however, the
1658 red LED will simply flash regularly to indicate that the system is
1659 still functional. It is safe to say Y here if you have a CATS
1660 system, but the driver will do nothing.
1663 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1664 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1665 || MACH_OMAP_PERSEUS2
1667 depends on !GENERIC_CLOCKEVENTS
1668 default y if ARCH_EBSA110
1670 If you say Y here, one of the system LEDs (the green one on the
1671 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1672 will flash regularly to indicate that the system is still
1673 operational. This is mainly useful to kernel hackers who are
1674 debugging unstable kernels.
1676 The LART uses the same LED for both Timer LED and CPU usage LED
1677 functions. You may choose to use both, but the Timer LED function
1678 will overrule the CPU usage LED.
1681 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1683 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1684 || MACH_OMAP_PERSEUS2
1687 If you say Y here, the red LED will be used to give a good real
1688 time indication of CPU usage, by lighting whenever the idle task
1689 is not currently executing.
1691 The LART uses the same LED for both Timer LED and CPU usage LED
1692 functions. You may choose to use both, but the Timer LED function
1693 will overrule the CPU usage LED.
1695 config ALIGNMENT_TRAP
1697 depends on CPU_CP15_MMU
1698 default y if !ARCH_EBSA110
1699 select HAVE_PROC_CPU if PROC_FS
1701 ARM processors cannot fetch/store information which is not
1702 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1703 address divisible by 4. On 32-bit ARM processors, these non-aligned
1704 fetch/store instructions will be emulated in software if you say
1705 here, which has a severe performance impact. This is necessary for
1706 correct operation of some network protocols. With an IP-only
1707 configuration it is safe to say N, otherwise say Y.
1709 config UACCESS_WITH_MEMCPY
1710 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1711 depends on MMU && EXPERIMENTAL
1712 default y if CPU_FEROCEON
1714 Implement faster copy_to_user and clear_user methods for CPU
1715 cores where a 8-word STM instruction give significantly higher
1716 memory write throughput than a sequence of individual 32bit stores.
1718 A possible side effect is a slight increase in scheduling latency
1719 between threads sharing the same address space if they invoke
1720 such copy operations with large buffers.
1722 However, if the CPU data cache is using a write-allocate mode,
1723 this option is unlikely to provide any performance gain.
1727 prompt "Enable seccomp to safely compute untrusted bytecode"
1729 This kernel feature is useful for number crunching applications
1730 that may need to compute untrusted bytecode during their
1731 execution. By using pipes or other transports made available to
1732 the process as file descriptors supporting the read/write
1733 syscalls, it's possible to isolate those applications in
1734 their own address space using seccomp. Once seccomp is
1735 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1736 and the task is only allowed to execute a few safe syscalls
1737 defined by each seccomp mode.
1739 config CC_STACKPROTECTOR
1740 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1741 depends on EXPERIMENTAL
1743 This option turns on the -fstack-protector GCC feature. This
1744 feature puts, at the beginning of functions, a canary value on
1745 the stack just before the return address, and validates
1746 the value just before actually returning. Stack based buffer
1747 overflows (that need to overwrite this return address) now also
1748 overwrite the canary, which gets detected and the attack is then
1749 neutralized via a kernel panic.
1750 This feature requires gcc version 4.2 or above.
1752 config DEPRECATED_PARAM_STRUCT
1753 bool "Provide old way to pass kernel parameters"
1755 This was deprecated in 2001 and announced to live on for 5 years.
1756 Some old boot loaders still use this way.
1758 config ARM_FLUSH_CONSOLE_ON_RESTART
1759 bool "Force flush the console on restart"
1761 If the console is locked while the system is rebooted, the messages
1762 in the temporary logbuffer would not have propogated to all the
1763 console drivers. This option forces the console lock to be
1764 released if it failed to be acquired, which will cause all the
1765 pending messages to be flushed.
1772 bool "Flattened Device Tree support"
1774 select OF_EARLY_FLATTREE
1776 Include support for flattened device tree machine descriptions.
1778 # Compressed boot loader in ROM. Yes, we really want to ask about
1779 # TEXT and BSS so we preserve their values in the config files.
1780 config ZBOOT_ROM_TEXT
1781 hex "Compressed ROM boot loader base address"
1784 The physical address at which the ROM-able zImage is to be
1785 placed in the target. Platforms which normally make use of
1786 ROM-able zImage formats normally set this to a suitable
1787 value in their defconfig file.
1789 If ZBOOT_ROM is not enabled, this has no effect.
1791 config ZBOOT_ROM_BSS
1792 hex "Compressed ROM boot loader BSS address"
1795 The base address of an area of read/write memory in the target
1796 for the ROM-able zImage which must be available while the
1797 decompressor is running. It must be large enough to hold the
1798 entire decompressed kernel plus an additional 128 KiB.
1799 Platforms which normally make use of ROM-able zImage formats
1800 normally set this to a suitable value in their defconfig file.
1802 If ZBOOT_ROM is not enabled, this has no effect.
1805 bool "Compressed boot loader in ROM/flash"
1806 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1808 Say Y here if you intend to execute your compressed kernel image
1809 (zImage) directly from ROM or flash. If unsure, say N.
1811 config ZBOOT_ROM_MMCIF
1812 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1813 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1815 Say Y here to include experimental MMCIF loading code in the
1816 ROM-able zImage. With this enabled it is possible to write the
1817 the ROM-able zImage kernel image to an MMC card and boot the
1818 kernel straight from the reset vector. At reset the processor
1819 Mask ROM will load the first part of the the ROM-able zImage
1820 which in turn loads the rest the kernel image to RAM using the
1821 MMCIF hardware block.
1824 string "Default kernel command string"
1827 On some architectures (EBSA110 and CATS), there is currently no way
1828 for the boot loader to pass arguments to the kernel. For these
1829 architectures, you should supply some command-line options at build
1830 time by entering them here. As a minimum, you should specify the
1831 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1834 prompt "Kernel command line type" if CMDLINE != ""
1835 default CMDLINE_FROM_BOOTLOADER
1837 config CMDLINE_FROM_BOOTLOADER
1838 bool "Use bootloader kernel arguments if available"
1840 Uses the command-line options passed by the boot loader. If
1841 the boot loader doesn't provide any, the default kernel command
1842 string provided in CMDLINE will be used.
1844 config CMDLINE_EXTEND
1845 bool "Extend bootloader kernel arguments"
1847 The command-line arguments provided by the boot loader will be
1848 appended to the default kernel command string.
1850 config CMDLINE_FORCE
1851 bool "Always use the default kernel command string"
1853 Always use the default kernel command string, even if the boot
1854 loader passes other arguments to the kernel.
1855 This is useful if you cannot or don't want to change the
1856 command-line options your boot loader passes to the kernel.
1860 bool "Kernel Execute-In-Place from ROM"
1861 depends on !ZBOOT_ROM
1863 Execute-In-Place allows the kernel to run from non-volatile storage
1864 directly addressable by the CPU, such as NOR flash. This saves RAM
1865 space since the text section of the kernel is not loaded from flash
1866 to RAM. Read-write sections, such as the data section and stack,
1867 are still copied to RAM. The XIP kernel is not compressed since
1868 it has to run directly from flash, so it will take more space to
1869 store it. The flash address used to link the kernel object files,
1870 and for storing it, is configuration dependent. Therefore, if you
1871 say Y here, you must know the proper physical address where to
1872 store the kernel image depending on your own flash memory usage.
1874 Also note that the make target becomes "make xipImage" rather than
1875 "make zImage" or "make Image". The final kernel binary to put in
1876 ROM memory will be arch/arm/boot/xipImage.
1880 config XIP_PHYS_ADDR
1881 hex "XIP Kernel Physical Location"
1882 depends on XIP_KERNEL
1883 default "0x00080000"
1885 This is the physical address in your flash memory the kernel will
1886 be linked for and stored to. This address is dependent on your
1890 bool "Kexec system call (EXPERIMENTAL)"
1891 depends on EXPERIMENTAL
1893 kexec is a system call that implements the ability to shutdown your
1894 current kernel, and to start another kernel. It is like a reboot
1895 but it is independent of the system firmware. And like a reboot
1896 you can start any kernel with it, not just Linux.
1898 It is an ongoing process to be certain the hardware in a machine
1899 is properly shutdown, so do not be surprised if this code does not
1900 initially work for you. It may help to enable device hotplugging
1904 bool "Export atags in procfs"
1908 Should the atags used to boot the kernel be exported in an "atags"
1909 file in procfs. Useful with kexec.
1912 bool "Build kdump crash kernel (EXPERIMENTAL)"
1913 depends on EXPERIMENTAL
1915 Generate crash dump after being started by kexec. This should
1916 be normally only set in special crash dump kernels which are
1917 loaded in the main kernel with kexec-tools into a specially
1918 reserved region and then later executed after a crash by
1919 kdump/kexec. The crash dump kernel must be compiled to a
1920 memory address not used by the main kernel
1922 For more details see Documentation/kdump/kdump.txt
1924 config AUTO_ZRELADDR
1925 bool "Auto calculation of the decompressed kernel image address"
1926 depends on !ZBOOT_ROM && !ARCH_U300
1928 ZRELADDR is the physical address where the decompressed kernel
1929 image will be placed. If AUTO_ZRELADDR is selected, the address
1930 will be determined at run-time by masking the current IP with
1931 0xf8000000. This assumes the zImage being placed in the first 128MB
1932 from start of memory.
1936 menu "CPU Power Management"
1940 source "drivers/cpufreq/Kconfig"
1943 tristate "CPUfreq driver for i.MX CPUs"
1944 depends on ARCH_MXC && CPU_FREQ
1946 This enables the CPUfreq driver for i.MX CPUs.
1948 config CPU_FREQ_SA1100
1951 config CPU_FREQ_SA1110
1954 config CPU_FREQ_INTEGRATOR
1955 tristate "CPUfreq driver for ARM Integrator CPUs"
1956 depends on ARCH_INTEGRATOR && CPU_FREQ
1959 This enables the CPUfreq driver for ARM Integrator CPUs.
1961 For details, take a look at <file:Documentation/cpu-freq>.
1967 depends on CPU_FREQ && ARCH_PXA && PXA25x
1969 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1971 config CPU_FREQ_S3C64XX
1972 bool "CPUfreq support for Samsung S3C64XX CPUs"
1973 depends on CPU_FREQ && CPU_S3C6410
1978 Internal configuration node for common cpufreq on Samsung SoC
1980 config CPU_FREQ_S3C24XX
1981 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1982 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1985 This enables the CPUfreq driver for the Samsung S3C24XX family
1988 For details, take a look at <file:Documentation/cpu-freq>.
1992 config CPU_FREQ_S3C24XX_PLL
1993 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1994 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1996 Compile in support for changing the PLL frequency from the
1997 S3C24XX series CPUfreq driver. The PLL takes time to settle
1998 after a frequency change, so by default it is not enabled.
2000 This also means that the PLL tables for the selected CPU(s) will
2001 be built which may increase the size of the kernel image.
2003 config CPU_FREQ_S3C24XX_DEBUG
2004 bool "Debug CPUfreq Samsung driver core"
2005 depends on CPU_FREQ_S3C24XX
2007 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2009 config CPU_FREQ_S3C24XX_IODEBUG
2010 bool "Debug CPUfreq Samsung driver IO timing"
2011 depends on CPU_FREQ_S3C24XX
2013 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2015 config CPU_FREQ_S3C24XX_DEBUGFS
2016 bool "Export debugfs for CPUFreq"
2017 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2019 Export status information via debugfs.
2023 source "drivers/cpuidle/Kconfig"
2027 menu "Floating point emulation"
2029 comment "At least one emulation must be selected"
2032 bool "NWFPE math emulation"
2033 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2035 Say Y to include the NWFPE floating point emulator in the kernel.
2036 This is necessary to run most binaries. Linux does not currently
2037 support floating point hardware so you need to say Y here even if
2038 your machine has an FPA or floating point co-processor podule.
2040 You may say N here if you are going to load the Acorn FPEmulator
2041 early in the bootup.
2044 bool "Support extended precision"
2045 depends on FPE_NWFPE
2047 Say Y to include 80-bit support in the kernel floating-point
2048 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2049 Note that gcc does not generate 80-bit operations by default,
2050 so in most cases this option only enlarges the size of the
2051 floating point emulator without any good reason.
2053 You almost surely want to say N here.
2056 bool "FastFPE math emulation (EXPERIMENTAL)"
2057 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2059 Say Y here to include the FAST floating point emulator in the kernel.
2060 This is an experimental much faster emulator which now also has full
2061 precision for the mantissa. It does not support any exceptions.
2062 It is very simple, and approximately 3-6 times faster than NWFPE.
2064 It should be sufficient for most programs. It may be not suitable
2065 for scientific calculations, but you have to check this for yourself.
2066 If you do not feel you need a faster FP emulation you should better
2070 bool "VFP-format floating point maths"
2071 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2073 Say Y to include VFP support code in the kernel. This is needed
2074 if your hardware includes a VFP unit.
2076 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2077 release notes and additional status information.
2079 Say N if your target does not have VFP hardware.
2087 bool "Advanced SIMD (NEON) Extension support"
2088 depends on VFPv3 && CPU_V7
2090 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2095 menu "Userspace binary formats"
2097 source "fs/Kconfig.binfmt"
2100 tristate "RISC OS personality"
2103 Say Y here to include the kernel code necessary if you want to run
2104 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2105 experimental; if this sounds frightening, say N and sleep in peace.
2106 You can also say M here to compile this support as a module (which
2107 will be called arthur).
2111 menu "Power management options"
2113 source "kernel/power/Kconfig"
2115 config ARCH_SUSPEND_POSSIBLE
2116 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2117 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2118 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2123 source "net/Kconfig"
2125 source "drivers/Kconfig"
2129 source "arch/arm/Kconfig.debug"
2131 source "security/Kconfig"
2133 source "crypto/Kconfig"
2135 source "lib/Kconfig"