4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_CMPXCHG_LOCKREF
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CLONE_BACKWARDS
13 select CPU_PM if (SUSPEND || CPU_IDLE)
14 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
15 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
16 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
17 select GENERIC_IDLE_POLL_SETUP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_SCHED_CLOCK
22 select GENERIC_SMP_IDLE_THREAD
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select HARDIRQS_SW_RESEND
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
28 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_TRACEHOOK
31 select HAVE_CONTEXT_TRACKING
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_DMA_API_DEBUG
36 select HAVE_DMA_CONTIGUOUS if MMU
37 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
38 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
39 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
40 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
41 select HAVE_GENERIC_DMA_COHERENT
42 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
43 select HAVE_IDE if PCI || ISA || PCMCIA
44 select HAVE_IRQ_TIME_ACCOUNTING
45 select HAVE_KERNEL_GZIP
46 select HAVE_KERNEL_LZ4
47 select HAVE_KERNEL_LZMA
48 select HAVE_KERNEL_LZO
50 select HAVE_KPROBES if !XIP_KERNEL
51 select HAVE_KRETPROBES if (HAVE_KPROBES)
53 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
54 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
55 select HAVE_PERF_EVENTS
57 select HAVE_PERF_USER_STACK_DUMP
58 select HAVE_REGS_AND_STACK_ACCESS_API
59 select HAVE_SYSCALL_TRACEPOINTS
61 select HAVE_VIRT_CPU_ACCOUNTING_GEN
62 select IRQ_FORCED_THREADING
64 select MODULES_USE_ELF_REL
66 select OLD_SIGSUSPEND3
67 select PERF_USE_VMALLOC
69 select SYS_SUPPORTS_APM_EMULATION
70 # Above selects are sorted alphabetically; please add new ones
71 # according to that. Thanks.
73 The ARM series is a line of low-power-consumption RISC chip designs
74 licensed by ARM Ltd and targeted at embedded applications and
75 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
76 manufactured, but legacy ARM-based PC hardware remains popular in
77 Europe. There is an ARM Linux project with a web page at
78 <http://www.arm.linux.org.uk/>.
80 config ARM_HAS_SG_CHAIN
83 config NEED_SG_DMA_LENGTH
86 config ARM_DMA_USE_IOMMU
88 select ARM_HAS_SG_CHAIN
89 select NEED_SG_DMA_LENGTH
93 config ARM_DMA_IOMMU_ALIGNMENT
94 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
98 DMA mapping framework by default aligns all buffers to the smallest
99 PAGE_SIZE order which is greater than or equal to the requested buffer
100 size. This works well for buffers up to a few hundreds kilobytes, but
101 for larger buffers it just a waste of address space. Drivers which has
102 relatively small addressing window (like 64Mib) might run out of
103 virtual space with just a few allocations.
105 With this parameter you can specify the maximum PAGE_SIZE order for
106 DMA IOMMU buffers. Larger buffers will be aligned only to this
107 specified order. The order is expressed as a power of two multiplied
115 config MIGHT_HAVE_PCI
118 config SYS_SUPPORTS_APM_EMULATION
123 select GENERIC_ALLOCATOR
134 The Extended Industry Standard Architecture (EISA) bus was
135 developed as an open alternative to the IBM MicroChannel bus.
137 The EISA bus provided some of the features of the IBM MicroChannel
138 bus while maintaining backward compatibility with cards made for
139 the older ISA bus. The EISA bus saw limited use between 1988 and
140 1995 when it was made obsolete by the PCI bus.
142 Say Y here if you are building a kernel for an EISA-based machine.
149 config STACKTRACE_SUPPORT
153 config HAVE_LATENCYTOP_SUPPORT
158 config LOCKDEP_SUPPORT
162 config TRACE_IRQFLAGS_SUPPORT
166 config RWSEM_GENERIC_SPINLOCK
170 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_CPUFREQ
182 Internal node to signify that the ARCH has CPUFREQ support
183 and that the relevant menu configurations are displayed for
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_HAS_DMA_SET_COHERENT_MASK
209 config GENERIC_ISA_DMA
215 config NEED_RET_TO_USER
223 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
224 default DRAM_BASE if REMAP_VECTORS_TO_RAM
227 The base address of exception vectors. This must be two pages
230 config ARM_PATCH_PHYS_VIRT
231 bool "Patch physical to virtual translations at runtime" if EMBEDDED
233 depends on !XIP_KERNEL && MMU
234 depends on !ARCH_REALVIEW || !SPARSEMEM
236 Patch phys-to-virt and virt-to-phys translation functions at
237 boot and module load time according to the position of the
238 kernel in system memory.
240 This can only be used with non-XIP MMU kernels where the base
241 of physical memory is at a 16MB boundary.
243 Only disable this option if you know that you do not require
244 this feature (eg, building a kernel for a single machine) and
245 you need to shrink the kernel to the minimal size.
247 config NEED_MACH_GPIO_H
250 Select this when mach/gpio.h is required to provide special
251 definitions for this platform. The need for mach/gpio.h should
252 be avoided when possible.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
271 default DRAM_BASE if !MMU
273 Please provide the physical address corresponding to the
274 location of main memory in your system.
280 source "init/Kconfig"
282 source "kernel/Kconfig.freezer"
287 bool "MMU-based Paged Memory Management Support"
290 Select if you want MMU-based virtualised addressing space
291 support by paged memory management. If unsure, say 'Y'.
294 # The "ARM system type" choice list is ordered alphabetically by option
295 # text. Please add new entries in the option alphabetic order.
298 prompt "ARM system type"
299 default ARCH_VERSATILE if !MMU
300 default ARCH_MULTIPLATFORM if MMU
302 config ARCH_MULTIPLATFORM
303 bool "Allow multiple platforms to be selected"
305 select ARM_PATCH_PHYS_VIRT
308 select MULTI_IRQ_HANDLER
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
314 select ARCH_HAS_CPUFREQ
317 select COMMON_CLK_VERSATILE
318 select GENERIC_CLOCKEVENTS
321 select MULTI_IRQ_HANDLER
322 select NEED_MACH_MEMORY_H
323 select PLAT_VERSATILE
326 select VERSATILE_FPGA_IRQ
328 Support for ARM's Integrator platform.
331 bool "ARM Ltd. RealView family"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_TIMER_SP804
336 select COMMON_CLK_VERSATILE
337 select GENERIC_CLOCKEVENTS
338 select GPIO_PL061 if GPIOLIB
340 select NEED_MACH_MEMORY_H
341 select PLAT_VERSATILE
342 select PLAT_VERSATILE_CLCD
344 This enables support for ARM Ltd RealView boards.
346 config ARCH_VERSATILE
347 bool "ARM Ltd. Versatile family"
348 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
354 select HAVE_MACH_CLKDEV
356 select PLAT_VERSATILE
357 select PLAT_VERSATILE_CLCD
358 select PLAT_VERSATILE_CLOCK
359 select VERSATILE_FPGA_IRQ
361 This enables support for ARM Ltd Versatile board.
365 select ARCH_REQUIRE_GPIOLIB
368 select NEED_MACH_GPIO_H
369 select NEED_MACH_IO_H if PCCARD
371 select PINCTRL_AT91 if USE_OF
373 This enables support for systems based on Atmel
374 AT91RM9200 and AT91SAM9* processors.
377 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
378 select ARCH_REQUIRE_GPIOLIB
383 select GENERIC_CLOCKEVENTS
385 select MULTI_IRQ_HANDLER
388 Support for Cirrus Logic 711x/721x/731x based boards.
391 bool "Cortina Systems Gemini"
392 select ARCH_REQUIRE_GPIOLIB
395 select GENERIC_CLOCKEVENTS
397 Support for the Cortina Systems Gemini family SoCs
401 select ARCH_USES_GETTIMEOFFSET
404 select NEED_MACH_IO_H
405 select NEED_MACH_MEMORY_H
408 This is an evaluation board for the StrongARM processor available
409 from Digital. It has limited hardware on-board, including an
410 Ethernet interface, two PCMCIA sockets, two serial ports and a
414 bool "Energy Micro efm32"
416 select ARCH_REQUIRE_GPIOLIB
418 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
419 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
424 select GENERIC_CLOCKEVENTS
430 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
435 select ARCH_HAS_HOLES_MEMORYMODEL
436 select ARCH_REQUIRE_GPIOLIB
437 select ARCH_USES_GETTIMEOFFSET
442 select NEED_MACH_MEMORY_H
444 This enables support for the Cirrus EP93xx series of CPUs.
446 config ARCH_FOOTBRIDGE
450 select GENERIC_CLOCKEVENTS
452 select NEED_MACH_IO_H if !MMU
453 select NEED_MACH_MEMORY_H
455 Support for systems based on the DC21285 companion chip
456 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
459 bool "Hilscher NetX based"
463 select GENERIC_CLOCKEVENTS
465 This enables support for systems based on the Hilscher NetX Soc
471 select NEED_MACH_MEMORY_H
472 select NEED_RET_TO_USER
477 Support for Intel's IOP13XX (XScale) family of processors.
482 select ARCH_REQUIRE_GPIOLIB
485 select NEED_RET_TO_USER
489 Support for Intel's 80219 and IOP32X (XScale) family of
495 select ARCH_REQUIRE_GPIOLIB
498 select NEED_RET_TO_USER
502 Support for Intel's IOP33X (XScale) family of processors.
507 select ARCH_HAS_DMA_SET_COHERENT_MASK
508 select ARCH_SUPPORTS_BIG_ENDIAN
509 select ARCH_REQUIRE_GPIOLIB
512 select DMABOUNCE if PCI
513 select GENERIC_CLOCKEVENTS
514 select MIGHT_HAVE_PCI
515 select NEED_MACH_IO_H
516 select USB_EHCI_BIG_ENDIAN_DESC
517 select USB_EHCI_BIG_ENDIAN_MMIO
519 Support for Intel's IXP4XX (XScale) family of processors.
523 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
526 select MIGHT_HAVE_PCI
530 select PLAT_ORION_LEGACY
531 select USB_ARCH_HAS_EHCI
533 Support for the Marvell Dove SoC 88AP510
536 bool "Marvell Kirkwood"
537 select ARCH_HAS_CPUFREQ
538 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
545 select PINCTRL_KIRKWOOD
546 select PLAT_ORION_LEGACY
548 Support for the following Marvell Kirkwood series SoCs:
549 88F6180, 88F6192 and 88F6281.
552 bool "Marvell MV78xx0"
553 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_CLOCKEVENTS
558 select PLAT_ORION_LEGACY
560 Support for the following Marvell MV78xx0 series SoCs:
566 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
571 select PLAT_ORION_LEGACY
573 Support for the following Marvell Orion 5x series SoCs:
574 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
575 Orion-2 (5281), Orion-1-90 (6183).
578 bool "Marvell PXA168/910/MMP2"
580 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_ALLOCATOR
583 select GENERIC_CLOCKEVENTS
586 select MULTI_IRQ_HANDLER
591 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
594 bool "Micrel/Kendin KS8695"
595 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
599 select NEED_MACH_MEMORY_H
601 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
602 System-on-Chip devices.
605 bool "Nuvoton W90X900 CPU"
606 select ARCH_REQUIRE_GPIOLIB
610 select GENERIC_CLOCKEVENTS
612 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
613 At present, the w90x900 has been renamed nuc900, regarding
614 the ARM series product line, you can login the following
615 link address to know more.
617 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
618 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
622 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
630 select USB_ARCH_HAS_OHCI
633 Support for the NXP LPC32XX family of processors
636 bool "PXA2xx/PXA3xx-based"
638 select ARCH_HAS_CPUFREQ
640 select ARCH_REQUIRE_GPIOLIB
641 select ARM_CPU_SUSPEND if PM
645 select GENERIC_CLOCKEVENTS
648 select MULTI_IRQ_HANDLER
652 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
656 select ARCH_REQUIRE_GPIOLIB
657 select CLKSRC_OF if OF
659 select GENERIC_CLOCKEVENTS
661 Support for Qualcomm MSM/QSD based systems. This runs on the
662 apps processor of the MSM/QSD and depends on a shared memory
663 interface to the modem processor which runs the baseband
664 stack and controls some vital subsystems
665 (clock and power control, etc).
667 config ARCH_SHMOBILE_LEGACY
668 bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)"
670 select ARM_PATCH_PHYS_VIRT
672 select GENERIC_CLOCKEVENTS
673 select HAVE_ARM_SCU if SMP
674 select HAVE_ARM_TWD if SMP
675 select HAVE_MACH_CLKDEV
677 select MIGHT_HAVE_CACHE_L2X0
678 select MULTI_IRQ_HANDLER
681 select PM_GENERIC_DOMAINS if PM
684 Support for Renesas's SH-Mobile and R-Mobile ARM platforms using
685 a non-multiplatform kernel.
690 select ARCH_MAY_HAVE_PC_FDC
691 select ARCH_SPARSEMEM_ENABLE
692 select ARCH_USES_GETTIMEOFFSET
695 select HAVE_PATA_PLATFORM
697 select NEED_MACH_IO_H
698 select NEED_MACH_MEMORY_H
702 On the Acorn Risc-PC, Linux can support the internal IDE disk and
703 CD-ROM interface, serial and parallel port, and the floppy drive.
707 select ARCH_HAS_CPUFREQ
709 select ARCH_REQUIRE_GPIOLIB
710 select ARCH_SPARSEMEM_ENABLE
715 select GENERIC_CLOCKEVENTS
718 select NEED_MACH_MEMORY_H
721 Support for StrongARM 11x0 based boards.
724 bool "Samsung S3C24XX SoCs"
725 select ARCH_HAS_CPUFREQ
726 select ARCH_REQUIRE_GPIOLIB
728 select CLKSRC_SAMSUNG_PWM
729 select GENERIC_CLOCKEVENTS
731 select HAVE_S3C2410_I2C if I2C
732 select HAVE_S3C2410_WATCHDOG if WATCHDOG
733 select HAVE_S3C_RTC if RTC_CLASS
734 select MULTI_IRQ_HANDLER
735 select NEED_MACH_GPIO_H
736 select NEED_MACH_IO_H
739 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
740 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
741 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
742 Samsung SMDK2410 development board (and derivatives).
745 bool "Samsung S3C64XX"
746 select ARCH_HAS_CPUFREQ
747 select ARCH_REQUIRE_GPIOLIB
750 select CLKSRC_SAMSUNG_PWM
753 select GENERIC_CLOCKEVENTS
755 select HAVE_S3C2410_I2C if I2C
756 select HAVE_S3C2410_WATCHDOG if WATCHDOG
758 select NEED_MACH_GPIO_H
761 select PM_GENERIC_DOMAINS
763 select S3C_GPIO_TRACK
765 select SAMSUNG_GPIOLIB_4BIT
766 select SAMSUNG_WAKEMASK
767 select SAMSUNG_WDT_RESET
768 select USB_ARCH_HAS_OHCI
770 Samsung S3C64XX series based systems
773 bool "Samsung S5P6440 S5P6450"
775 select CLKSRC_SAMSUNG_PWM
777 select GENERIC_CLOCKEVENTS
779 select HAVE_S3C2410_I2C if I2C
780 select HAVE_S3C2410_WATCHDOG if WATCHDOG
781 select HAVE_S3C_RTC if RTC_CLASS
782 select NEED_MACH_GPIO_H
784 select SAMSUNG_WDT_RESET
786 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
790 bool "Samsung S5PC100"
791 select ARCH_REQUIRE_GPIOLIB
793 select CLKSRC_SAMSUNG_PWM
795 select GENERIC_CLOCKEVENTS
797 select HAVE_S3C2410_I2C if I2C
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 select HAVE_S3C_RTC if RTC_CLASS
800 select NEED_MACH_GPIO_H
802 select SAMSUNG_WDT_RESET
804 Samsung S5PC100 series based systems
807 bool "Samsung S5PV210/S5PC110"
808 select ARCH_HAS_CPUFREQ
809 select ARCH_HAS_HOLES_MEMORYMODEL
810 select ARCH_SPARSEMEM_ENABLE
812 select CLKSRC_SAMSUNG_PWM
814 select GENERIC_CLOCKEVENTS
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
818 select HAVE_S3C_RTC if RTC_CLASS
819 select NEED_MACH_GPIO_H
820 select NEED_MACH_MEMORY_H
823 Samsung S5PV210/S5PC110 series based systems
826 bool "Samsung EXYNOS"
827 select ARCH_HAS_CPUFREQ
828 select ARCH_HAS_HOLES_MEMORYMODEL
829 select ARCH_REQUIRE_GPIOLIB
830 select ARCH_SPARSEMEM_ENABLE
834 select GENERIC_CLOCKEVENTS
835 select HAVE_S3C2410_I2C if I2C
836 select HAVE_S3C2410_WATCHDOG if WATCHDOG
837 select HAVE_S3C_RTC if RTC_CLASS
838 select NEED_MACH_MEMORY_H
842 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
846 select ARCH_HAS_HOLES_MEMORYMODEL
847 select ARCH_REQUIRE_GPIOLIB
849 select GENERIC_ALLOCATOR
850 select GENERIC_CLOCKEVENTS
851 select GENERIC_IRQ_CHIP
857 Support for TI's DaVinci platform.
862 select ARCH_HAS_CPUFREQ
863 select ARCH_HAS_HOLES_MEMORYMODEL
865 select ARCH_REQUIRE_GPIOLIB
868 select GENERIC_CLOCKEVENTS
869 select GENERIC_IRQ_CHIP
872 select NEED_MACH_IO_H if PCCARD
873 select NEED_MACH_MEMORY_H
875 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
879 menu "Multiple platform selection"
880 depends on ARCH_MULTIPLATFORM
882 comment "CPU Core family selection"
884 config ARCH_MULTI_V4T
885 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
886 depends on !ARCH_MULTI_V6_V7
887 select ARCH_MULTI_V4_V5
888 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
889 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
890 CPU_ARM925T || CPU_ARM940T)
893 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
894 depends on !ARCH_MULTI_V6_V7
895 select ARCH_MULTI_V4_V5
896 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
897 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
898 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
900 config ARCH_MULTI_V4_V5
904 bool "ARMv6 based platforms (ARM11)"
905 select ARCH_MULTI_V6_V7
909 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
911 select ARCH_MULTI_V6_V7
914 config ARCH_MULTI_V6_V7
917 config ARCH_MULTI_CPU_AUTO
918 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
924 # This is sorted alphabetically by mach-* pathname. However, plat-*
925 # Kconfigs may be included either alphabetically (according to the
926 # plat- suffix) or along side the corresponding mach-* source.
928 source "arch/arm/mach-mvebu/Kconfig"
930 source "arch/arm/mach-at91/Kconfig"
932 source "arch/arm/mach-bcm/Kconfig"
934 source "arch/arm/mach-bcm2835/Kconfig"
936 source "arch/arm/mach-berlin/Kconfig"
938 source "arch/arm/mach-clps711x/Kconfig"
940 source "arch/arm/mach-cns3xxx/Kconfig"
942 source "arch/arm/mach-davinci/Kconfig"
944 source "arch/arm/mach-dove/Kconfig"
946 source "arch/arm/mach-ep93xx/Kconfig"
948 source "arch/arm/mach-footbridge/Kconfig"
950 source "arch/arm/mach-gemini/Kconfig"
952 source "arch/arm/mach-highbank/Kconfig"
954 source "arch/arm/mach-integrator/Kconfig"
956 source "arch/arm/mach-iop32x/Kconfig"
958 source "arch/arm/mach-iop33x/Kconfig"
960 source "arch/arm/mach-iop13xx/Kconfig"
962 source "arch/arm/mach-ixp4xx/Kconfig"
964 source "arch/arm/mach-keystone/Kconfig"
966 source "arch/arm/mach-kirkwood/Kconfig"
968 source "arch/arm/mach-ks8695/Kconfig"
970 source "arch/arm/mach-msm/Kconfig"
972 source "arch/arm/mach-moxart/Kconfig"
974 source "arch/arm/mach-mv78xx0/Kconfig"
976 source "arch/arm/mach-imx/Kconfig"
978 source "arch/arm/mach-mxs/Kconfig"
980 source "arch/arm/mach-netx/Kconfig"
982 source "arch/arm/mach-nomadik/Kconfig"
984 source "arch/arm/mach-nspire/Kconfig"
986 source "arch/arm/plat-omap/Kconfig"
988 source "arch/arm/mach-omap1/Kconfig"
990 source "arch/arm/mach-omap2/Kconfig"
992 source "arch/arm/mach-orion5x/Kconfig"
994 source "arch/arm/mach-picoxcell/Kconfig"
996 source "arch/arm/mach-pxa/Kconfig"
997 source "arch/arm/plat-pxa/Kconfig"
999 source "arch/arm/mach-mmp/Kconfig"
1001 source "arch/arm/mach-realview/Kconfig"
1003 source "arch/arm/mach-rockchip/Kconfig"
1005 source "arch/arm/mach-sa1100/Kconfig"
1007 source "arch/arm/plat-samsung/Kconfig"
1009 source "arch/arm/mach-socfpga/Kconfig"
1011 source "arch/arm/mach-spear/Kconfig"
1013 source "arch/arm/mach-sti/Kconfig"
1015 source "arch/arm/mach-s3c24xx/Kconfig"
1017 source "arch/arm/mach-s3c64xx/Kconfig"
1019 source "arch/arm/mach-s5p64x0/Kconfig"
1021 source "arch/arm/mach-s5pc100/Kconfig"
1023 source "arch/arm/mach-s5pv210/Kconfig"
1025 source "arch/arm/mach-exynos/Kconfig"
1027 source "arch/arm/mach-shmobile/Kconfig"
1029 source "arch/arm/mach-sunxi/Kconfig"
1031 source "arch/arm/mach-prima2/Kconfig"
1033 source "arch/arm/mach-tegra/Kconfig"
1035 source "arch/arm/mach-u300/Kconfig"
1037 source "arch/arm/mach-ux500/Kconfig"
1039 source "arch/arm/mach-versatile/Kconfig"
1041 source "arch/arm/mach-vexpress/Kconfig"
1042 source "arch/arm/plat-versatile/Kconfig"
1044 source "arch/arm/mach-virt/Kconfig"
1046 source "arch/arm/mach-vt8500/Kconfig"
1048 source "arch/arm/mach-w90x900/Kconfig"
1050 source "arch/arm/mach-zynq/Kconfig"
1052 # Definitions to make life easier
1058 select GENERIC_CLOCKEVENTS
1064 select GENERIC_IRQ_CHIP
1067 config PLAT_ORION_LEGACY
1074 config PLAT_VERSATILE
1077 config ARM_TIMER_SP804
1080 select CLKSRC_OF if OF
1082 source arch/arm/mm/Kconfig
1086 default 16 if ARCH_EP93XX
1090 bool "Enable iWMMXt support" if !CPU_PJ4
1091 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1092 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1094 Enable support for iWMMXt context switching at run time if
1095 running on a CPU that supports it.
1097 config MULTI_IRQ_HANDLER
1100 Allow each machine to specify it's own IRQ handler at run time.
1103 source "arch/arm/Kconfig-nommu"
1106 config PJ4B_ERRATA_4742
1107 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1108 depends on CPU_PJ4B && MACH_ARMADA_370
1111 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1112 Event (WFE) IDLE states, a specific timing sensitivity exists between
1113 the retiring WFI/WFE instructions and the newly issued subsequent
1114 instructions. This sensitivity can result in a CPU hang scenario.
1116 The software must insert either a Data Synchronization Barrier (DSB)
1117 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1120 config ARM_ERRATA_326103
1121 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1124 Executing a SWP instruction to read-only memory does not set bit 11
1125 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1126 treat the access as a read, preventing a COW from occurring and
1127 causing the faulting task to livelock.
1129 config ARM_ERRATA_411920
1130 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1131 depends on CPU_V6 || CPU_V6K
1133 Invalidation of the Instruction Cache operation can
1134 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1135 It does not affect the MPCore. This option enables the ARM Ltd.
1136 recommended workaround.
1138 config ARM_ERRATA_430973
1139 bool "ARM errata: Stale prediction on replaced interworking branch"
1142 This option enables the workaround for the 430973 Cortex-A8
1143 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1144 interworking branch is replaced with another code sequence at the
1145 same virtual address, whether due to self-modifying code or virtual
1146 to physical address re-mapping, Cortex-A8 does not recover from the
1147 stale interworking branch prediction. This results in Cortex-A8
1148 executing the new code sequence in the incorrect ARM or Thumb state.
1149 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1150 and also flushes the branch target cache at every context switch.
1151 Note that setting specific bits in the ACTLR register may not be
1152 available in non-secure mode.
1154 config ARM_ERRATA_458693
1155 bool "ARM errata: Processor deadlock when a false hazard is created"
1157 depends on !ARCH_MULTIPLATFORM
1159 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1160 erratum. For very specific sequences of memory operations, it is
1161 possible for a hazard condition intended for a cache line to instead
1162 be incorrectly associated with a different cache line. This false
1163 hazard might then cause a processor deadlock. The workaround enables
1164 the L1 caching of the NEON accesses and disables the PLD instruction
1165 in the ACTLR register. Note that setting specific bits in the ACTLR
1166 register may not be available in non-secure mode.
1168 config ARM_ERRATA_460075
1169 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1171 depends on !ARCH_MULTIPLATFORM
1173 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1174 erratum. Any asynchronous access to the L2 cache may encounter a
1175 situation in which recent store transactions to the L2 cache are lost
1176 and overwritten with stale memory contents from external memory. The
1177 workaround disables the write-allocate mode for the L2 cache via the
1178 ACTLR register. Note that setting specific bits in the ACTLR register
1179 may not be available in non-secure mode.
1181 config ARM_ERRATA_742230
1182 bool "ARM errata: DMB operation may be faulty"
1183 depends on CPU_V7 && SMP
1184 depends on !ARCH_MULTIPLATFORM
1186 This option enables the workaround for the 742230 Cortex-A9
1187 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1188 between two write operations may not ensure the correct visibility
1189 ordering of the two writes. This workaround sets a specific bit in
1190 the diagnostic register of the Cortex-A9 which causes the DMB
1191 instruction to behave as a DSB, ensuring the correct behaviour of
1194 config ARM_ERRATA_742231
1195 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1196 depends on CPU_V7 && SMP
1197 depends on !ARCH_MULTIPLATFORM
1199 This option enables the workaround for the 742231 Cortex-A9
1200 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1201 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1202 accessing some data located in the same cache line, may get corrupted
1203 data due to bad handling of the address hazard when the line gets
1204 replaced from one of the CPUs at the same time as another CPU is
1205 accessing it. This workaround sets specific bits in the diagnostic
1206 register of the Cortex-A9 which reduces the linefill issuing
1207 capabilities of the processor.
1209 config PL310_ERRATA_588369
1210 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1211 depends on CACHE_L2X0
1213 The PL310 L2 cache controller implements three types of Clean &
1214 Invalidate maintenance operations: by Physical Address
1215 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1216 They are architecturally defined to behave as the execution of a
1217 clean operation followed immediately by an invalidate operation,
1218 both performing to the same memory location. This functionality
1219 is not correctly implemented in PL310 as clean lines are not
1220 invalidated as a result of these operations.
1222 config ARM_ERRATA_643719
1223 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1224 depends on CPU_V7 && SMP
1226 This option enables the workaround for the 643719 Cortex-A9 (prior to
1227 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1228 register returns zero when it should return one. The workaround
1229 corrects this value, ensuring cache maintenance operations which use
1230 it behave as intended and avoiding data corruption.
1232 config ARM_ERRATA_720789
1233 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1236 This option enables the workaround for the 720789 Cortex-A9 (prior to
1237 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1238 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1239 As a consequence of this erratum, some TLB entries which should be
1240 invalidated are not, resulting in an incoherency in the system page
1241 tables. The workaround changes the TLB flushing routines to invalidate
1242 entries regardless of the ASID.
1244 config PL310_ERRATA_727915
1245 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1246 depends on CACHE_L2X0
1248 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1249 operation (offset 0x7FC). This operation runs in background so that
1250 PL310 can handle normal accesses while it is in progress. Under very
1251 rare circumstances, due to this erratum, write data can be lost when
1252 PL310 treats a cacheable write transaction during a Clean &
1253 Invalidate by Way operation.
1255 config ARM_ERRATA_743622
1256 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1258 depends on !ARCH_MULTIPLATFORM
1260 This option enables the workaround for the 743622 Cortex-A9
1261 (r2p*) erratum. Under very rare conditions, a faulty
1262 optimisation in the Cortex-A9 Store Buffer may lead to data
1263 corruption. This workaround sets a specific bit in the diagnostic
1264 register of the Cortex-A9 which disables the Store Buffer
1265 optimisation, preventing the defect from occurring. This has no
1266 visible impact on the overall performance or power consumption of the
1269 config ARM_ERRATA_751472
1270 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1272 depends on !ARCH_MULTIPLATFORM
1274 This option enables the workaround for the 751472 Cortex-A9 (prior
1275 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1276 completion of a following broadcasted operation if the second
1277 operation is received by a CPU before the ICIALLUIS has completed,
1278 potentially leading to corrupted entries in the cache or TLB.
1280 config PL310_ERRATA_753970
1281 bool "PL310 errata: cache sync operation may be faulty"
1282 depends on CACHE_PL310
1284 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1286 Under some condition the effect of cache sync operation on
1287 the store buffer still remains when the operation completes.
1288 This means that the store buffer is always asked to drain and
1289 this prevents it from merging any further writes. The workaround
1290 is to replace the normal offset of cache sync operation (0x730)
1291 by another offset targeting an unmapped PL310 register 0x740.
1292 This has the same effect as the cache sync operation: store buffer
1293 drain and waiting for all buffers empty.
1295 config ARM_ERRATA_754322
1296 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1299 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1300 r3p*) erratum. A speculative memory access may cause a page table walk
1301 which starts prior to an ASID switch but completes afterwards. This
1302 can populate the micro-TLB with a stale entry which may be hit with
1303 the new ASID. This workaround places two dsb instructions in the mm
1304 switching code so that no page table walks can cross the ASID switch.
1306 config ARM_ERRATA_754327
1307 bool "ARM errata: no automatic Store Buffer drain"
1308 depends on CPU_V7 && SMP
1310 This option enables the workaround for the 754327 Cortex-A9 (prior to
1311 r2p0) erratum. The Store Buffer does not have any automatic draining
1312 mechanism and therefore a livelock may occur if an external agent
1313 continuously polls a memory location waiting to observe an update.
1314 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1315 written polling loops from denying visibility of updates to memory.
1317 config ARM_ERRATA_364296
1318 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1321 This options enables the workaround for the 364296 ARM1136
1322 r0p2 erratum (possible cache data corruption with
1323 hit-under-miss enabled). It sets the undocumented bit 31 in
1324 the auxiliary control register and the FI bit in the control
1325 register, thus disabling hit-under-miss without putting the
1326 processor into full low interrupt latency mode. ARM11MPCore
1329 config ARM_ERRATA_764369
1330 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1331 depends on CPU_V7 && SMP
1333 This option enables the workaround for erratum 764369
1334 affecting Cortex-A9 MPCore with two or more processors (all
1335 current revisions). Under certain timing circumstances, a data
1336 cache line maintenance operation by MVA targeting an Inner
1337 Shareable memory region may fail to proceed up to either the
1338 Point of Coherency or to the Point of Unification of the
1339 system. This workaround adds a DSB instruction before the
1340 relevant cache maintenance functions and sets a specific bit
1341 in the diagnostic control register of the SCU.
1343 config PL310_ERRATA_769419
1344 bool "PL310 errata: no automatic Store Buffer drain"
1345 depends on CACHE_L2X0
1347 On revisions of the PL310 prior to r3p2, the Store Buffer does
1348 not automatically drain. This can cause normal, non-cacheable
1349 writes to be retained when the memory system is idle, leading
1350 to suboptimal I/O performance for drivers using coherent DMA.
1351 This option adds a write barrier to the cpu_idle loop so that,
1352 on systems with an outer cache, the store buffer is drained
1355 config ARM_ERRATA_775420
1356 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1359 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1360 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1361 operation aborts with MMU exception, it might cause the processor
1362 to deadlock. This workaround puts DSB before executing ISB if
1363 an abort may occur on cache maintenance.
1365 config ARM_ERRATA_798181
1366 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1367 depends on CPU_V7 && SMP
1369 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1370 adequately shooting down all use of the old entries. This
1371 option enables the Linux kernel workaround for this erratum
1372 which sends an IPI to the CPUs that are running the same ASID
1373 as the one being invalidated.
1375 config ARM_ERRATA_773022
1376 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1379 This option enables the workaround for the 773022 Cortex-A15
1380 (up to r0p4) erratum. In certain rare sequences of code, the
1381 loop buffer may deliver incorrect instructions. This
1382 workaround disables the loop buffer to avoid the erratum.
1386 source "arch/arm/common/Kconfig"
1396 Find out whether you have ISA slots on your motherboard. ISA is the
1397 name of a bus system, i.e. the way the CPU talks to the other stuff
1398 inside your box. Other bus systems are PCI, EISA, MicroChannel
1399 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1400 newer boards don't support it. If you have ISA, say Y, otherwise N.
1402 # Select ISA DMA controller support
1407 # Select ISA DMA interface
1412 bool "PCI support" if MIGHT_HAVE_PCI
1414 Find out whether you have a PCI motherboard. PCI is the name of a
1415 bus system, i.e. the way the CPU talks to the other stuff inside
1416 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1417 VESA. If you have PCI, say Y, otherwise N.
1423 config PCI_NANOENGINE
1424 bool "BSE nanoEngine PCI support"
1425 depends on SA1100_NANOENGINE
1427 Enable PCI on the BSE nanoEngine board.
1432 config PCI_HOST_ITE8152
1434 depends on PCI && MACH_ARMCORE
1438 source "drivers/pci/Kconfig"
1439 source "drivers/pci/pcie/Kconfig"
1441 source "drivers/pcmcia/Kconfig"
1445 menu "Kernel Features"
1450 This option should be selected by machines which have an SMP-
1453 The only effect of this option is to make the SMP-related
1454 options available to the user for configuration.
1457 bool "Symmetric Multi-Processing"
1458 depends on CPU_V6K || CPU_V7
1459 depends on GENERIC_CLOCKEVENTS
1461 depends on MMU || ARM_MPU
1463 This enables support for systems with more than one CPU. If you have
1464 a system with only one CPU, like most personal computers, say N. If
1465 you have a system with more than one CPU, say Y.
1467 If you say N here, the kernel will run on single and multiprocessor
1468 machines, but will use only one CPU of a multiprocessor machine. If
1469 you say Y here, the kernel will run on many, but not all, single
1470 processor machines. On a single processor machine, the kernel will
1471 run faster if you say N here.
1473 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1474 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1475 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1477 If you don't know what to do here, say N.
1480 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1481 depends on SMP && !XIP_KERNEL && MMU
1484 SMP kernels contain instructions which fail on non-SMP processors.
1485 Enabling this option allows the kernel to modify itself to make
1486 these instructions safe. Disabling it allows about 1K of space
1489 If you don't know what to do here, say Y.
1491 config ARM_CPU_TOPOLOGY
1492 bool "Support cpu topology definition"
1493 depends on SMP && CPU_V7
1496 Support ARM cpu topology definition. The MPIDR register defines
1497 affinity between processors which is then used to describe the cpu
1498 topology of an ARM System.
1501 bool "Multi-core scheduler support"
1502 depends on ARM_CPU_TOPOLOGY
1504 Multi-core scheduler support improves the CPU scheduler's decision
1505 making when dealing with multi-core CPU chips at a cost of slightly
1506 increased overhead in some places. If unsure say N here.
1509 bool "SMT scheduler support"
1510 depends on ARM_CPU_TOPOLOGY
1512 Improves the CPU scheduler's decision making when dealing with
1513 MultiThreading at a cost of slightly increased overhead in some
1514 places. If unsure say N here.
1519 This option enables support for the ARM system coherency unit
1521 config HAVE_ARM_ARCH_TIMER
1522 bool "Architected timer support"
1524 select ARM_ARCH_TIMER
1525 select GENERIC_CLOCKEVENTS
1527 This option enables support for the ARM architected timer
1532 select CLKSRC_OF if OF
1534 This options enables support for the ARM timer and watchdog unit
1537 bool "Multi-Cluster Power Management"
1538 depends on CPU_V7 && SMP
1540 This option provides the common power management infrastructure
1541 for (multi-)cluster based systems, such as big.LITTLE based
1545 bool "big.LITTLE support (Experimental)"
1546 depends on CPU_V7 && SMP
1549 This option enables support selections for the big.LITTLE
1550 system architecture.
1553 bool "big.LITTLE switcher support"
1554 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1556 select ARM_CPU_SUSPEND
1558 The big.LITTLE "switcher" provides the core functionality to
1559 transparently handle transition between a cluster of A15's
1560 and a cluster of A7's in a big.LITTLE system.
1562 config BL_SWITCHER_DUMMY_IF
1563 tristate "Simple big.LITTLE switcher user interface"
1564 depends on BL_SWITCHER && DEBUG_KERNEL
1566 This is a simple and dummy char dev interface to control
1567 the big.LITTLE switcher core code. It is meant for
1568 debugging purposes only.
1571 prompt "Memory split"
1574 Select the desired split between kernel and user memory.
1576 If you are not absolutely sure what you are doing, leave this
1580 bool "3G/1G user/kernel split"
1582 bool "2G/2G user/kernel split"
1584 bool "1G/3G user/kernel split"
1589 default 0x40000000 if VMSPLIT_1G
1590 default 0x80000000 if VMSPLIT_2G
1594 int "Maximum number of CPUs (2-32)"
1600 bool "Support for hot-pluggable CPUs"
1603 Say Y here to experiment with turning CPUs off and on. CPUs
1604 can be controlled through /sys/devices/system/cpu.
1607 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1610 Say Y here if you want Linux to communicate with system firmware
1611 implementing the PSCI specification for CPU-centric power
1612 management operations described in ARM document number ARM DEN
1613 0022A ("Power State Coordination Interface System Software on
1616 # The GPIO number here must be sorted by descending number. In case of
1617 # a multiplatform kernel, we just want the highest value required by the
1618 # selected platforms.
1621 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1622 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1623 default 392 if ARCH_U8500
1624 default 352 if ARCH_VT8500
1625 default 288 if ARCH_SUNXI
1626 default 264 if MACH_H4700
1629 Maximum number of GPIOs in the system.
1631 If unsure, leave the default value.
1633 source kernel/Kconfig.preempt
1637 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1638 ARCH_S5PV210 || ARCH_EXYNOS4
1639 default AT91_TIMER_HZ if ARCH_AT91
1640 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1644 depends on HZ_FIXED = 0
1645 prompt "Timer frequency"
1669 default HZ_FIXED if HZ_FIXED != 0
1670 default 100 if HZ_100
1671 default 200 if HZ_200
1672 default 250 if HZ_250
1673 default 300 if HZ_300
1674 default 500 if HZ_500
1678 def_bool HIGH_RES_TIMERS
1681 def_bool HIGH_RES_TIMERS
1683 config THUMB2_KERNEL
1684 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1685 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1686 default y if CPU_THUMBONLY
1688 select ARM_ASM_UNIFIED
1691 By enabling this option, the kernel will be compiled in
1692 Thumb-2 mode. A compiler/assembler that understand the unified
1693 ARM-Thumb syntax is needed.
1697 config THUMB2_AVOID_R_ARM_THM_JUMP11
1698 bool "Work around buggy Thumb-2 short branch relocations in gas"
1699 depends on THUMB2_KERNEL && MODULES
1702 Various binutils versions can resolve Thumb-2 branches to
1703 locally-defined, preemptible global symbols as short-range "b.n"
1704 branch instructions.
1706 This is a problem, because there's no guarantee the final
1707 destination of the symbol, or any candidate locations for a
1708 trampoline, are within range of the branch. For this reason, the
1709 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1710 relocation in modules at all, and it makes little sense to add
1713 The symptom is that the kernel fails with an "unsupported
1714 relocation" error when loading some modules.
1716 Until fixed tools are available, passing
1717 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1718 code which hits this problem, at the cost of a bit of extra runtime
1719 stack usage in some cases.
1721 The problem is described in more detail at:
1722 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1724 Only Thumb-2 kernels are affected.
1726 Unless you are sure your tools don't have this problem, say Y.
1728 config ARM_ASM_UNIFIED
1732 bool "Use the ARM EABI to compile the kernel"
1734 This option allows for the kernel to be compiled using the latest
1735 ARM ABI (aka EABI). This is only useful if you are using a user
1736 space environment that is also compiled with EABI.
1738 Since there are major incompatibilities between the legacy ABI and
1739 EABI, especially with regard to structure member alignment, this
1740 option also changes the kernel syscall calling convention to
1741 disambiguate both ABIs and allow for backward compatibility support
1742 (selected with CONFIG_OABI_COMPAT).
1744 To use this you need GCC version 4.0.0 or later.
1747 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1748 depends on AEABI && !THUMB2_KERNEL
1750 This option preserves the old syscall interface along with the
1751 new (ARM EABI) one. It also provides a compatibility layer to
1752 intercept syscalls that have structure arguments which layout
1753 in memory differs between the legacy ABI and the new ARM EABI
1754 (only for non "thumb" binaries). This option adds a tiny
1755 overhead to all syscalls and produces a slightly larger kernel.
1757 The seccomp filter system will not be available when this is
1758 selected, since there is no way yet to sensibly distinguish
1759 between calling conventions during filtering.
1761 If you know you'll be using only pure EABI user space then you
1762 can say N here. If this option is not selected and you attempt
1763 to execute a legacy ABI binary then the result will be
1764 UNPREDICTABLE (in fact it can be predicted that it won't work
1765 at all). If in doubt say N.
1767 config ARCH_HAS_HOLES_MEMORYMODEL
1770 config ARCH_SPARSEMEM_ENABLE
1773 config ARCH_SPARSEMEM_DEFAULT
1774 def_bool ARCH_SPARSEMEM_ENABLE
1776 config ARCH_SELECT_MEMORY_MODEL
1777 def_bool ARCH_SPARSEMEM_ENABLE
1779 config HAVE_ARCH_PFN_VALID
1780 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1783 bool "High Memory Support"
1786 The address space of ARM processors is only 4 Gigabytes large
1787 and it has to accommodate user address space, kernel address
1788 space as well as some memory mapped IO. That means that, if you
1789 have a large amount of physical memory and/or IO, not all of the
1790 memory can be "permanently mapped" by the kernel. The physical
1791 memory that is not permanently mapped is called "high memory".
1793 Depending on the selected kernel/user memory split, minimum
1794 vmalloc space and actual amount of RAM, you may not need this
1795 option which should result in a slightly faster kernel.
1800 bool "Allocate 2nd-level pagetables from highmem"
1803 config HW_PERF_EVENTS
1804 bool "Enable hardware performance counter support for perf events"
1805 depends on PERF_EVENTS
1808 Enable hardware performance counter support for perf events. If
1809 disabled, perf events will use software events only.
1811 config SYS_SUPPORTS_HUGETLBFS
1815 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1819 config ARCH_WANT_GENERAL_HUGETLB
1824 config FORCE_MAX_ZONEORDER
1825 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1826 range 11 64 if ARCH_SHMOBILE_LEGACY
1827 default "12" if SOC_AM33XX
1828 default "9" if SA1111 || ARCH_EFM32
1831 The kernel memory allocator divides physically contiguous memory
1832 blocks into "zones", where each zone is a power of two number of
1833 pages. This option selects the largest power of two that the kernel
1834 keeps in the memory allocator. If you need to allocate very large
1835 blocks of physically contiguous memory, then you may need to
1836 increase this value.
1838 This config option is actually maximum order plus one. For example,
1839 a value of 11 means that the largest free memory block is 2^10 pages.
1841 config ALIGNMENT_TRAP
1843 depends on CPU_CP15_MMU
1844 default y if !ARCH_EBSA110
1845 select HAVE_PROC_CPU if PROC_FS
1847 ARM processors cannot fetch/store information which is not
1848 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1849 address divisible by 4. On 32-bit ARM processors, these non-aligned
1850 fetch/store instructions will be emulated in software if you say
1851 here, which has a severe performance impact. This is necessary for
1852 correct operation of some network protocols. With an IP-only
1853 configuration it is safe to say N, otherwise say Y.
1855 config UACCESS_WITH_MEMCPY
1856 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1858 default y if CPU_FEROCEON
1860 Implement faster copy_to_user and clear_user methods for CPU
1861 cores where a 8-word STM instruction give significantly higher
1862 memory write throughput than a sequence of individual 32bit stores.
1864 A possible side effect is a slight increase in scheduling latency
1865 between threads sharing the same address space if they invoke
1866 such copy operations with large buffers.
1868 However, if the CPU data cache is using a write-allocate mode,
1869 this option is unlikely to provide any performance gain.
1873 prompt "Enable seccomp to safely compute untrusted bytecode"
1875 This kernel feature is useful for number crunching applications
1876 that may need to compute untrusted bytecode during their
1877 execution. By using pipes or other transports made available to
1878 the process as file descriptors supporting the read/write
1879 syscalls, it's possible to isolate those applications in
1880 their own address space using seccomp. Once seccomp is
1881 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1882 and the task is only allowed to execute a few safe syscalls
1883 defined by each seccomp mode.
1885 config CC_STACKPROTECTOR
1886 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1888 This option turns on the -fstack-protector GCC feature. This
1889 feature puts, at the beginning of functions, a canary value on
1890 the stack just before the return address, and validates
1891 the value just before actually returning. Stack based buffer
1892 overflows (that need to overwrite this return address) now also
1893 overwrite the canary, which gets detected and the attack is then
1894 neutralized via a kernel panic.
1895 This feature requires gcc version 4.2 or above.
1908 bool "Xen guest support on ARM (EXPERIMENTAL)"
1909 depends on ARM && AEABI && OF
1910 depends on CPU_V7 && !CPU_V6
1911 depends on !GENERIC_ATOMIC64
1915 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1922 bool "Flattened Device Tree support"
1925 select OF_EARLY_FLATTREE
1927 Include support for flattened device tree machine descriptions.
1930 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1933 This is the traditional way of passing data to the kernel at boot
1934 time. If you are solely relying on the flattened device tree (or
1935 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1936 to remove ATAGS support from your kernel binary. If unsure,
1939 config DEPRECATED_PARAM_STRUCT
1940 bool "Provide old way to pass kernel parameters"
1943 This was deprecated in 2001 and announced to live on for 5 years.
1944 Some old boot loaders still use this way.
1946 # Compressed boot loader in ROM. Yes, we really want to ask about
1947 # TEXT and BSS so we preserve their values in the config files.
1948 config ZBOOT_ROM_TEXT
1949 hex "Compressed ROM boot loader base address"
1952 The physical address at which the ROM-able zImage is to be
1953 placed in the target. Platforms which normally make use of
1954 ROM-able zImage formats normally set this to a suitable
1955 value in their defconfig file.
1957 If ZBOOT_ROM is not enabled, this has no effect.
1959 config ZBOOT_ROM_BSS
1960 hex "Compressed ROM boot loader BSS address"
1963 The base address of an area of read/write memory in the target
1964 for the ROM-able zImage which must be available while the
1965 decompressor is running. It must be large enough to hold the
1966 entire decompressed kernel plus an additional 128 KiB.
1967 Platforms which normally make use of ROM-able zImage formats
1968 normally set this to a suitable value in their defconfig file.
1970 If ZBOOT_ROM is not enabled, this has no effect.
1973 bool "Compressed boot loader in ROM/flash"
1974 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1976 Say Y here if you intend to execute your compressed kernel image
1977 (zImage) directly from ROM or flash. If unsure, say N.
1980 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1981 depends on ZBOOT_ROM && ARCH_SH7372
1982 default ZBOOT_ROM_NONE
1984 Include experimental SD/MMC loading code in the ROM-able zImage.
1985 With this enabled it is possible to write the ROM-able zImage
1986 kernel image to an MMC or SD card and boot the kernel straight
1987 from the reset vector. At reset the processor Mask ROM will load
1988 the first part of the ROM-able zImage which in turn loads the
1989 rest the kernel image to RAM.
1991 config ZBOOT_ROM_NONE
1992 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1994 Do not load image from SD or MMC
1996 config ZBOOT_ROM_MMCIF
1997 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1999 Load image from MMCIF hardware block.
2001 config ZBOOT_ROM_SH_MOBILE_SDHI
2002 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2004 Load image from SDHI hardware block
2008 config ARM_APPENDED_DTB
2009 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2010 depends on OF && !ZBOOT_ROM
2012 With this option, the boot code will look for a device tree binary
2013 (DTB) appended to zImage
2014 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2016 This is meant as a backward compatibility convenience for those
2017 systems with a bootloader that can't be upgraded to accommodate
2018 the documented boot protocol using a device tree.
2020 Beware that there is very little in terms of protection against
2021 this option being confused by leftover garbage in memory that might
2022 look like a DTB header after a reboot if no actual DTB is appended
2023 to zImage. Do not leave this option active in a production kernel
2024 if you don't intend to always append a DTB. Proper passing of the
2025 location into r2 of a bootloader provided DTB is always preferable
2028 config ARM_ATAG_DTB_COMPAT
2029 bool "Supplement the appended DTB with traditional ATAG information"
2030 depends on ARM_APPENDED_DTB
2032 Some old bootloaders can't be updated to a DTB capable one, yet
2033 they provide ATAGs with memory configuration, the ramdisk address,
2034 the kernel cmdline string, etc. Such information is dynamically
2035 provided by the bootloader and can't always be stored in a static
2036 DTB. To allow a device tree enabled kernel to be used with such
2037 bootloaders, this option allows zImage to extract the information
2038 from the ATAG list and store it at run time into the appended DTB.
2041 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2042 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2044 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2045 bool "Use bootloader kernel arguments if available"
2047 Uses the command-line options passed by the boot loader instead of
2048 the device tree bootargs property. If the boot loader doesn't provide
2049 any, the device tree bootargs property will be used.
2051 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2052 bool "Extend with bootloader kernel arguments"
2054 The command-line arguments provided by the boot loader will be
2055 appended to the the device tree bootargs property.
2060 string "Default kernel command string"
2063 On some architectures (EBSA110 and CATS), there is currently no way
2064 for the boot loader to pass arguments to the kernel. For these
2065 architectures, you should supply some command-line options at build
2066 time by entering them here. As a minimum, you should specify the
2067 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2070 prompt "Kernel command line type" if CMDLINE != ""
2071 default CMDLINE_FROM_BOOTLOADER
2074 config CMDLINE_FROM_BOOTLOADER
2075 bool "Use bootloader kernel arguments if available"
2077 Uses the command-line options passed by the boot loader. If
2078 the boot loader doesn't provide any, the default kernel command
2079 string provided in CMDLINE will be used.
2081 config CMDLINE_EXTEND
2082 bool "Extend bootloader kernel arguments"
2084 The command-line arguments provided by the boot loader will be
2085 appended to the default kernel command string.
2087 config CMDLINE_FORCE
2088 bool "Always use the default kernel command string"
2090 Always use the default kernel command string, even if the boot
2091 loader passes other arguments to the kernel.
2092 This is useful if you cannot or don't want to change the
2093 command-line options your boot loader passes to the kernel.
2097 bool "Kernel Execute-In-Place from ROM"
2098 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2100 Execute-In-Place allows the kernel to run from non-volatile storage
2101 directly addressable by the CPU, such as NOR flash. This saves RAM
2102 space since the text section of the kernel is not loaded from flash
2103 to RAM. Read-write sections, such as the data section and stack,
2104 are still copied to RAM. The XIP kernel is not compressed since
2105 it has to run directly from flash, so it will take more space to
2106 store it. The flash address used to link the kernel object files,
2107 and for storing it, is configuration dependent. Therefore, if you
2108 say Y here, you must know the proper physical address where to
2109 store the kernel image depending on your own flash memory usage.
2111 Also note that the make target becomes "make xipImage" rather than
2112 "make zImage" or "make Image". The final kernel binary to put in
2113 ROM memory will be arch/arm/boot/xipImage.
2117 config XIP_PHYS_ADDR
2118 hex "XIP Kernel Physical Location"
2119 depends on XIP_KERNEL
2120 default "0x00080000"
2122 This is the physical address in your flash memory the kernel will
2123 be linked for and stored to. This address is dependent on your
2127 bool "Kexec system call (EXPERIMENTAL)"
2128 depends on (!SMP || PM_SLEEP_SMP)
2130 kexec is a system call that implements the ability to shutdown your
2131 current kernel, and to start another kernel. It is like a reboot
2132 but it is independent of the system firmware. And like a reboot
2133 you can start any kernel with it, not just Linux.
2135 It is an ongoing process to be certain the hardware in a machine
2136 is properly shutdown, so do not be surprised if this code does not
2137 initially work for you.
2140 bool "Export atags in procfs"
2141 depends on ATAGS && KEXEC
2144 Should the atags used to boot the kernel be exported in an "atags"
2145 file in procfs. Useful with kexec.
2148 bool "Build kdump crash kernel (EXPERIMENTAL)"
2150 Generate crash dump after being started by kexec. This should
2151 be normally only set in special crash dump kernels which are
2152 loaded in the main kernel with kexec-tools into a specially
2153 reserved region and then later executed after a crash by
2154 kdump/kexec. The crash dump kernel must be compiled to a
2155 memory address not used by the main kernel
2157 For more details see Documentation/kdump/kdump.txt
2159 config AUTO_ZRELADDR
2160 bool "Auto calculation of the decompressed kernel image address"
2161 depends on !ZBOOT_ROM
2163 ZRELADDR is the physical address where the decompressed kernel
2164 image will be placed. If AUTO_ZRELADDR is selected, the address
2165 will be determined at run-time by masking the current IP with
2166 0xf8000000. This assumes the zImage being placed in the first 128MB
2167 from start of memory.
2171 menu "CPU Power Management"
2174 source "drivers/cpufreq/Kconfig"
2177 source "drivers/cpuidle/Kconfig"
2181 menu "Floating point emulation"
2183 comment "At least one emulation must be selected"
2186 bool "NWFPE math emulation"
2187 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2189 Say Y to include the NWFPE floating point emulator in the kernel.
2190 This is necessary to run most binaries. Linux does not currently
2191 support floating point hardware so you need to say Y here even if
2192 your machine has an FPA or floating point co-processor podule.
2194 You may say N here if you are going to load the Acorn FPEmulator
2195 early in the bootup.
2198 bool "Support extended precision"
2199 depends on FPE_NWFPE
2201 Say Y to include 80-bit support in the kernel floating-point
2202 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2203 Note that gcc does not generate 80-bit operations by default,
2204 so in most cases this option only enlarges the size of the
2205 floating point emulator without any good reason.
2207 You almost surely want to say N here.
2210 bool "FastFPE math emulation (EXPERIMENTAL)"
2211 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2213 Say Y here to include the FAST floating point emulator in the kernel.
2214 This is an experimental much faster emulator which now also has full
2215 precision for the mantissa. It does not support any exceptions.
2216 It is very simple, and approximately 3-6 times faster than NWFPE.
2218 It should be sufficient for most programs. It may be not suitable
2219 for scientific calculations, but you have to check this for yourself.
2220 If you do not feel you need a faster FP emulation you should better
2224 bool "VFP-format floating point maths"
2225 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2227 Say Y to include VFP support code in the kernel. This is needed
2228 if your hardware includes a VFP unit.
2230 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2231 release notes and additional status information.
2233 Say N if your target does not have VFP hardware.
2241 bool "Advanced SIMD (NEON) Extension support"
2242 depends on VFPv3 && CPU_V7
2244 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2247 config KERNEL_MODE_NEON
2248 bool "Support for NEON in kernel mode"
2249 depends on NEON && AEABI
2251 Say Y to include support for NEON in kernel mode.
2255 menu "Userspace binary formats"
2257 source "fs/Kconfig.binfmt"
2260 tristate "RISC OS personality"
2263 Say Y here to include the kernel code necessary if you want to run
2264 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2265 experimental; if this sounds frightening, say N and sleep in peace.
2266 You can also say M here to compile this support as a module (which
2267 will be called arthur).
2271 menu "Power management options"
2273 source "kernel/power/Kconfig"
2275 config ARCH_SUSPEND_POSSIBLE
2276 depends on !ARCH_S5PC100
2277 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2278 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2281 config ARM_CPU_SUSPEND
2286 source "net/Kconfig"
2288 source "drivers/Kconfig"
2292 source "arch/arm/Kconfig.debug"
2294 source "security/Kconfig"
2296 source "crypto/Kconfig"
2298 source "lib/Kconfig"
2300 source "arch/arm/kvm/Kconfig"