2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
15 AR_CLASS( .arch armv7-a )
16 M_CLASS( .arch armv7-m )
21 * Note that these macros must not contain any code which is not
22 * 100% relocatable. Any attempt to do so will result in a crash.
23 * Please select one of the following when turning on debugging.
27 #if defined(CONFIG_DEBUG_ICEDCC)
29 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
30 .macro loadsp, rb, tmp
33 mcr p14, 0, \ch, c0, c5, 0
35 #elif defined(CONFIG_CPU_XSCALE)
36 .macro loadsp, rb, tmp
39 mcr p14, 0, \ch, c8, c0, 0
42 .macro loadsp, rb, tmp
45 mcr p14, 0, \ch, c1, c0, 0
51 #include CONFIG_DEBUG_LL_INCLUDE
57 #if defined(CONFIG_ARCH_SA1100)
58 .macro loadsp, rb, tmp
59 mov \rb, #0x80000000 @ physical base address
60 #ifdef CONFIG_DEBUG_LL_SER3
61 add \rb, \rb, #0x00050000 @ Ser3
63 add \rb, \rb, #0x00010000 @ Ser1
67 .macro loadsp, rb, tmp
85 .macro debug_reloc_start
88 kphex r6, 8 /* processor id */
90 kphex r7, 8 /* architecture id */
91 #ifdef CONFIG_CPU_CP15
93 mrc p15, 0, r0, c1, c0
94 kphex r0, 8 /* control reg */
97 kphex r5, 8 /* decompressed kernel start */
99 kphex r9, 8 /* decompressed kernel end */
101 kphex r4, 8 /* kernel execution address */
106 .macro debug_reloc_end
108 kphex r5, 8 /* end of kernel */
111 bl memdump /* dump 256 bytes at start of kernel */
115 .section ".start", #alloc, #execinstr
117 * sort out different calling conventions
121 * Always enter in ARM state for CPUs that support the ARM ISA.
122 * As of today (2014) that's exactly the members of the A and R
127 .type start,#function
133 THUMB( badr r12, 1f )
136 .word _magic_sig @ Magic numbers to help the loader
137 .word _magic_start @ absolute load/run zImage address
138 .word _magic_end @ zImage end address
139 .word 0x04030201 @ endianness flag
143 ARM_BE8( setend be ) @ go BE8 if compiled for BE8
144 AR_CLASS( mrs r9, cpsr )
145 #ifdef CONFIG_ARM_VIRT_EXT
146 bl __hyp_stub_install @ get into SVC mode, reversibly
148 mov r7, r1 @ save architecture ID
149 mov r8, r2 @ save atags pointer
151 #ifndef CONFIG_CPU_V7M
153 * Booting from Angel - need to enter SVC mode and disable
154 * FIQs/IRQs (numeric definitions from angel arm.h source).
155 * We only do this if we were in user mode on entry.
157 mrs r2, cpsr @ get current mode
158 tst r2, #3 @ not user?
160 mov r0, #0x17 @ angel_SWIreason_EnterSVC
161 ARM( swi 0x123456 ) @ angel_SWI_ARM
162 THUMB( svc 0xab ) @ angel_SWI_THUMB
164 safe_svcmode_maskall r0
165 msr spsr_cxsf, r9 @ Save the CPU boot mode in
169 * Note that some cache flushing and other stuff may
170 * be needed here - is there an Angel SWI call for this?
174 * some architecture specific code can be inserted
175 * by the linker here, but it should preserve r7, r8, and r9.
180 #ifdef CONFIG_AUTO_ZRELADDR
182 * Find the start of physical memory. As we are executing
183 * without the MMU on, we are in the physical address space.
184 * We just need to get rid of any offset by aligning the
187 * This alignment is a balance between the requirements of
188 * different platforms - we have chosen 128MB to allow
189 * platforms which align the start of their physical memory
190 * to 128MB to use this feature, while allowing the zImage
191 * to be placed within the first 128MB of memory on other
192 * platforms. Increasing the alignment means we place
193 * stricter alignment requirements on the start of physical
194 * memory, but relaxing it means that we break people who
195 * are already placing their zImage in (eg) the top 64MB
199 and r4, r4, #0xf8000000
200 /* Determine final kernel image address. */
201 add r4, r4, #TEXT_OFFSET
207 * Set up a page table only if it won't overwrite ourself.
208 * That means r4 < pc || r4 - 16k page directory > &_end.
209 * Given that r4 > &_end is most unfrequent, we add a rough
210 * additional 1MB of room for a possible appended DTB.
217 orrcc r4, r4, #1 @ remember we skipped cache_on
221 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
225 * We might be running at a different address. We need
226 * to fix up various pointers.
228 sub r0, r0, r1 @ calculate the delta offset
229 add r6, r6, r0 @ _edata
230 add r10, r10, r0 @ inflated kernel size location
233 * The kernel build system appends the size of the
234 * decompressed kernel at the end of the compressed data
235 * in little-endian form.
239 orr r9, r9, lr, lsl #8
242 orr r9, r9, lr, lsl #16
243 orr r9, r9, r10, lsl #24
245 #ifndef CONFIG_ZBOOT_ROM
246 /* malloc space is above the relocated stack (64k max) */
248 add r10, sp, #0x10000
251 * With ZBOOT_ROM the bss/stack is non relocatable,
252 * but someone could still run this code from RAM,
253 * in which case our reference is _edata.
258 mov r5, #0 @ init dtb size to 0
259 #ifdef CONFIG_ARM_APPENDED_DTB
264 * r4 = final kernel address (possibly with LSB set)
265 * r5 = appended dtb size (still unknown)
267 * r7 = architecture ID
268 * r8 = atags/device tree pointer
269 * r9 = size of decompressed image
270 * r10 = end of this image, including bss/stack/malloc space if non XIP
275 * if there are device trees (dtb) appended to zImage, advance r10 so that the
276 * dtb data will get relocated along with the kernel if necessary.
281 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
286 bne dtb_check_done @ not found
288 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
290 * OK... Let's do some funky business here.
291 * If we do have a DTB appended to zImage, and we do have
292 * an ATAG list around, we want the later to be translated
293 * and folded into the former here. No GOT fixup has occurred
294 * yet, but none of the code we're about to call uses any
298 /* Get the initial DTB size */
301 /* convert to little endian */
302 eor r1, r5, r5, ror #16
303 bic r1, r1, #0x00ff0000
305 eor r5, r5, r1, lsr #8
307 /* 50% DTB growth should be good enough */
308 add r5, r5, r5, lsr #1
309 /* preserve 64-bit alignment */
312 /* clamp to 32KB min and 1MB max */
317 /* temporarily relocate the stack past the DTB work space */
320 stmfd sp!, {r0-r3, ip, lr}
327 * If returned value is 1, there is no ATAG at the location
328 * pointed by r8. Try the typical 0x100 offset from start
329 * of RAM and hope for the best.
332 sub r0, r4, #TEXT_OFFSET
339 ldmfd sp!, {r0-r3, ip, lr}
343 mov r8, r6 @ use the appended device tree
346 * Make sure that the DTB doesn't end up in the final
347 * kernel's .bss area. To do so, we adjust the decompressed
348 * kernel size to compensate if that .bss size is larger
349 * than the relocated code.
351 ldr r5, =_kernel_bss_size
352 adr r1, wont_overwrite
357 /* Get the current DTB size */
360 /* convert r5 (dtb size) to little endian */
361 eor r1, r5, r5, ror #16
362 bic r1, r1, #0x00ff0000
364 eor r5, r5, r1, lsr #8
367 /* preserve 64-bit alignment */
371 /* relocate some pointers past the appended dtb */
379 * Check to see if we will overwrite ourselves.
380 * r4 = final kernel address (possibly with LSB set)
381 * r9 = size of decompressed image
382 * r10 = end of this image, including bss/stack/malloc space if non XIP
384 * r4 - 16k page directory >= r10 -> OK
385 * r4 + image length <= address of wont_overwrite -> OK
386 * Note: the possible LSB in r4 is harmless here.
392 adr r9, wont_overwrite
397 * Relocate ourselves past the end of the decompressed kernel.
399 * r10 = end of the decompressed kernel
400 * Because we always copy ahead, we need to do it from the end and go
401 * backward in case the source and destination overlap.
404 * Bump to the next 256-byte boundary with the size of
405 * the relocation code added. This avoids overwriting
406 * ourself when the offset is small.
408 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
411 /* Get start of code we want to copy and align it down. */
415 /* Relocate the hyp vector base if necessary */
416 #ifdef CONFIG_ARM_VIRT_EXT
418 and r0, r0, #MODE_MASK
429 sub r9, r6, r5 @ size to copy
430 add r9, r9, #31 @ rounded up to a multiple
431 bic r9, r9, #31 @ ... of 32 bytes
435 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
437 stmdb r9!, {r0 - r3, r10 - r12, lr}
440 /* Preserve offset to relocated code. */
443 #ifndef CONFIG_ZBOOT_ROM
444 /* cache_clean_flush may use the stack, so relocate it */
456 * If delta is zero, we are running at the address we were linked at.
460 * r4 = kernel execution address (possibly with LSB set)
461 * r5 = appended dtb size (0 if not present)
462 * r7 = architecture ID
474 #ifndef CONFIG_ZBOOT_ROM
476 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
477 * we need to fix up pointers into the BSS region.
478 * Note that the stack pointer has already been fixed up.
484 * Relocate all entries in the GOT table.
485 * Bump bss entries to _edata + dtb size
487 1: ldr r1, [r11, #0] @ relocate entries in the GOT
488 add r1, r1, r0 @ This fixes up C references
489 cmp r1, r2 @ if entry >= bss_start &&
490 cmphs r3, r1 @ bss_end > entry
491 addhi r1, r1, r5 @ entry += dtb size
492 str r1, [r11], #4 @ next entry
496 /* bump our bss pointers too */
503 * Relocate entries in the GOT table. We only relocate
504 * the entries that are outside the (relocated) BSS region.
506 1: ldr r1, [r11, #0] @ relocate entries in the GOT
507 cmp r1, r2 @ entry < bss_start ||
508 cmphs r3, r1 @ _end < entry
509 addlo r1, r1, r0 @ table. This fixes up the
510 str r1, [r11], #4 @ C references.
515 not_relocated: mov r0, #0
516 1: str r0, [r2], #4 @ clear bss
524 * Did we skip the cache setup earlier?
525 * That is indicated by the LSB in r4.
533 * The C runtime environment should now be setup sufficiently.
534 * Set up some pointers, and start decompressing.
535 * r4 = kernel execution address
536 * r7 = architecture ID
540 mov r1, sp @ malloc space above stack
541 add r2, sp, #0x10000 @ 64k max
546 mov r1, r7 @ restore architecture number
547 mov r2, r8 @ restore atags pointer
549 #ifdef CONFIG_ARM_VIRT_EXT
550 mrs r0, spsr @ Get saved CPU boot mode
551 and r0, r0, #MODE_MASK
552 cmp r0, #HYP_MODE @ if not booted in HYP mode...
553 bne __enter_kernel @ boot kernel directly
555 adr r12, .L__hyp_reentry_vectors_offset
560 __HVC(0) @ otherwise bounce to hyp mode
562 b . @ should never be reached
565 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
573 .word __bss_start @ r2
576 .word input_data_end - 4 @ r10 (inflated size location)
577 .word _got_start @ r11
579 .word .L_user_stack_end @ sp
580 .word _end - restart + 16384 + 1024*1024
583 #ifdef CONFIG_ARCH_RPC
585 params: ldr r0, =0x10000100 @ params_phys for RPC
592 * Turn on the cache. We need to setup some page tables so that we
593 * can have both the I and D caches on.
595 * We place the page tables 16k down from the kernel execution address,
596 * and we hope that nothing else is using it. If we're using it, we
600 * r4 = kernel execution address
601 * r7 = architecture number
604 * r0, r1, r2, r3, r9, r10, r12 corrupted
605 * This routine must preserve:
609 cache_on: mov r3, #8 @ cache_on function
613 * Initialize the highest priority protection region, PR7
614 * to cover all 32bit address and cacheable and bufferable.
616 __armv4_mpu_cache_on:
617 mov r0, #0x3f @ 4G, the whole
618 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
619 mcr p15, 0, r0, c6, c7, 1
622 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
623 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
624 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
627 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
628 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
631 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
632 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
633 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
634 mrc p15, 0, r0, c1, c0, 0 @ read control reg
635 @ ...I .... ..D. WC.M
636 orr r0, r0, #0x002d @ .... .... ..1. 11.1
637 orr r0, r0, #0x1000 @ ...1 .... .... ....
639 mcr p15, 0, r0, c1, c0, 0 @ write control reg
642 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
643 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
646 __armv3_mpu_cache_on:
647 mov r0, #0x3f @ 4G, the whole
648 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
651 mcr p15, 0, r0, c2, c0, 0 @ cache on
652 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
655 mcr p15, 0, r0, c5, c0, 0 @ access permission
658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
660 * ?? ARMv3 MMU does not allow reading the control register,
661 * does this really work on ARMv3 MPU?
663 mrc p15, 0, r0, c1, c0, 0 @ read control reg
664 @ .... .... .... WC.M
665 orr r0, r0, #0x000d @ .... .... .... 11.1
666 /* ?? this overwrites the value constructed above? */
668 mcr p15, 0, r0, c1, c0, 0 @ write control reg
670 /* ?? invalidate for the second time? */
671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
674 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
680 __setup_mmu: sub r3, r4, #16384 @ Page directory size
681 bic r3, r3, #0xff @ Align the pointer
684 * Initialise the page tables, turning on the cacheable and bufferable
685 * bits for the RAM area only.
689 mov r9, r9, lsl #18 @ start of RAM
690 add r10, r9, #0x10000000 @ a reasonable RAM size
691 mov r1, #0x12 @ XN|U + section mapping
692 orr r1, r1, #3 << 10 @ AP=11
694 1: cmp r1, r9 @ if virt > start of RAM
695 cmphs r10, r1 @ && end of RAM > virt
696 bic r1, r1, #0x1c @ clear XN|U + C + B
697 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
698 orrhs r1, r1, r6 @ set RAM section settings
699 str r1, [r0], #4 @ 1:1 mapping
704 * If ever we are running from Flash, then we surely want the cache
705 * to be enabled also for our execution instance... We map 2MB of it
706 * so there is no map overlap problem for up to 1 MB compressed kernel.
707 * If the execution is in RAM then we would only be duplicating the above.
709 orr r1, r6, #0x04 @ ensure B is set for this
713 orr r1, r1, r2, lsl #20
714 add r0, r3, r2, lsl #2
721 @ Enable unaligned access on v6, to allow better code generation
722 @ for the decompressor C code:
723 __armv6_mmu_cache_on:
724 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
725 bic r0, r0, #2 @ A (no unaligned access fault)
726 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
727 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
728 b __armv4_mmu_cache_on
730 __arm926ejs_mmu_cache_on:
731 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
732 mov r0, #4 @ put dcache in WT mode
733 mcr p15, 7, r0, c15, c0, 0
736 __armv4_mmu_cache_on:
739 mov r6, #CB_BITS | 0x12 @ U
742 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
743 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
744 mrc p15, 0, r0, c1, c0, 0 @ read control reg
745 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
747 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
748 bl __common_mmu_cache_on
750 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
754 __armv7_mmu_cache_on:
757 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
759 movne r6, #CB_BITS | 0x02 @ !XN
762 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
764 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
766 mrc p15, 0, r0, c1, c0, 0 @ read control reg
767 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
768 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
769 orr r0, r0, #0x003c @ write buffer
770 bic r0, r0, #2 @ A (no unaligned access fault)
771 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
772 @ (needed for ARM1176)
774 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
775 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
776 orrne r0, r0, #1 @ MMU enabled
777 movne r1, #0xfffffffd @ domain 0 = client
778 bic r6, r6, #1 << 31 @ 32-bit translation system
779 bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
780 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
781 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
782 mcr p15, 0, r0, c7, c5, 4 @ ISB
783 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
784 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
786 mcr p15, 0, r0, c7, c5, 4 @ ISB
787 mcr p15, 0, r0, c1, c0, 0 @ load control register
788 mrc p15, 0, r0, c1, c0, 0 @ and read it back
790 mcr p15, 0, r0, c7, c5, 4 @ ISB
795 mov r6, #CB_BITS | 0x12 @ U
798 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
799 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
800 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
801 mrc p15, 0, r0, c1, c0, 0 @ read control reg
802 orr r0, r0, #0x1000 @ I-cache enable
803 bl __common_mmu_cache_on
805 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
808 __common_mmu_cache_on:
809 #ifndef CONFIG_THUMB2_KERNEL
811 orr r0, r0, #0x000d @ Write buffer, mmu
814 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
815 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
817 .align 5 @ cache line aligned
818 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
819 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
820 sub pc, lr, r0, lsr #32 @ properly flush pipeline
823 #define PROC_ENTRY_SIZE (4*5)
826 * Here follow the relocatable cache support functions for the
827 * various processors. This is a generic hook for locating an
828 * entry and jumping to an instruction at the specified offset
829 * from the start of the block. Please note this is all position
839 call_cache_fn: adr r12, proc_types
840 #ifdef CONFIG_CPU_CP15
841 mrc p15, 0, r9, c0, c0 @ get processor ID
842 #elif defined(CONFIG_CPU_V7M)
844 * On v7-M the processor id is located in the V7M_SCB_CPUID
845 * register, but as cache handling is IMPLEMENTATION DEFINED on
846 * v7-M (if existant at all) we just return early here.
847 * If V7M_SCB_CPUID were used the cpu ID functions (i.e.
848 * __armv7_mmu_cache_{on,off,flush}) would be selected which
849 * use cp15 registers that are not implemented on v7-M.
853 ldr r9, =CONFIG_PROCESSOR_ID
855 1: ldr r1, [r12, #0] @ get value
856 ldr r2, [r12, #4] @ get mask
857 eor r1, r1, r9 @ (real ^ match)
859 ARM( addeq pc, r12, r3 ) @ call cache function
860 THUMB( addeq r12, r3 )
861 THUMB( moveq pc, r12 ) @ call cache function
862 add r12, r12, #PROC_ENTRY_SIZE
866 * Table for cache operations. This is basically:
869 * - 'cache on' method instruction
870 * - 'cache off' method instruction
871 * - 'cache flush' method instruction
873 * We match an entry using: ((real_id ^ match) & mask) == 0
875 * Writethrough caches generally only need 'on' and 'off'
876 * methods. Writeback caches _must_ have the flush method
880 .type proc_types,#object
882 .word 0x41000000 @ old ARM ID
891 .word 0x41007000 @ ARM7/710
900 .word 0x41807200 @ ARM720T (writethrough)
902 W(b) __armv4_mmu_cache_on
903 W(b) __armv4_mmu_cache_off
907 .word 0x41007400 @ ARM74x
909 W(b) __armv3_mpu_cache_on
910 W(b) __armv3_mpu_cache_off
911 W(b) __armv3_mpu_cache_flush
913 .word 0x41009400 @ ARM94x
915 W(b) __armv4_mpu_cache_on
916 W(b) __armv4_mpu_cache_off
917 W(b) __armv4_mpu_cache_flush
919 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
921 W(b) __arm926ejs_mmu_cache_on
922 W(b) __armv4_mmu_cache_off
923 W(b) __armv5tej_mmu_cache_flush
925 .word 0x00007000 @ ARM7 IDs
934 @ Everything from here on will be the new ID system.
936 .word 0x4401a100 @ sa110 / sa1100
938 W(b) __armv4_mmu_cache_on
939 W(b) __armv4_mmu_cache_off
940 W(b) __armv4_mmu_cache_flush
942 .word 0x6901b110 @ sa1110
944 W(b) __armv4_mmu_cache_on
945 W(b) __armv4_mmu_cache_off
946 W(b) __armv4_mmu_cache_flush
949 .word 0xffffff00 @ PXA9xx
950 W(b) __armv4_mmu_cache_on
951 W(b) __armv4_mmu_cache_off
952 W(b) __armv4_mmu_cache_flush
954 .word 0x56158000 @ PXA168
956 W(b) __armv4_mmu_cache_on
957 W(b) __armv4_mmu_cache_off
958 W(b) __armv5tej_mmu_cache_flush
960 .word 0x56050000 @ Feroceon
962 W(b) __armv4_mmu_cache_on
963 W(b) __armv4_mmu_cache_off
964 W(b) __armv5tej_mmu_cache_flush
966 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
967 /* this conflicts with the standard ARMv5TE entry */
968 .long 0x41009260 @ Old Feroceon
970 b __armv4_mmu_cache_on
971 b __armv4_mmu_cache_off
972 b __armv5tej_mmu_cache_flush
975 .word 0x66015261 @ FA526
977 W(b) __fa526_cache_on
978 W(b) __armv4_mmu_cache_off
979 W(b) __fa526_cache_flush
981 @ These match on the architecture ID
983 .word 0x00020000 @ ARMv4T
985 W(b) __armv4_mmu_cache_on
986 W(b) __armv4_mmu_cache_off
987 W(b) __armv4_mmu_cache_flush
989 .word 0x00050000 @ ARMv5TE
991 W(b) __armv4_mmu_cache_on
992 W(b) __armv4_mmu_cache_off
993 W(b) __armv4_mmu_cache_flush
995 .word 0x00060000 @ ARMv5TEJ
997 W(b) __armv4_mmu_cache_on
998 W(b) __armv4_mmu_cache_off
999 W(b) __armv5tej_mmu_cache_flush
1001 .word 0x0007b000 @ ARMv6
1003 W(b) __armv6_mmu_cache_on
1004 W(b) __armv4_mmu_cache_off
1005 W(b) __armv6_mmu_cache_flush
1007 .word 0x000f0000 @ new CPU Id
1009 W(b) __armv7_mmu_cache_on
1010 W(b) __armv7_mmu_cache_off
1011 W(b) __armv7_mmu_cache_flush
1013 .word 0 @ unrecognised type
1022 .size proc_types, . - proc_types
1025 * If you get a "non-constant expression in ".if" statement"
1026 * error from the assembler on this line, check that you have
1027 * not accidentally written a "b" instruction where you should
1028 * have written W(b).
1030 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1031 .error "The size of one or more proc_types entries is wrong."
1035 * Turn off the Cache and MMU. ARMv3 does not support
1036 * reading the control register, but ARMv4 does.
1039 * r0, r1, r2, r3, r9, r12 corrupted
1040 * This routine must preserve:
1044 cache_off: mov r3, #12 @ cache_off function
1047 __armv4_mpu_cache_off:
1048 mrc p15, 0, r0, c1, c0
1050 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1052 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1053 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1054 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1057 __armv3_mpu_cache_off:
1058 mrc p15, 0, r0, c1, c0
1060 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1062 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1065 __armv4_mmu_cache_off:
1067 mrc p15, 0, r0, c1, c0
1069 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1071 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1072 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1076 __armv7_mmu_cache_off:
1077 mrc p15, 0, r0, c1, c0
1083 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1085 bl __armv7_mmu_cache_flush
1088 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1090 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1091 mcr p15, 0, r0, c7, c10, 4 @ DSB
1092 mcr p15, 0, r0, c7, c5, 4 @ ISB
1096 * Clean and flush the cache to maintain consistency.
1099 * r1, r2, r3, r9, r10, r11, r12 corrupted
1100 * This routine must preserve:
1108 __armv4_mpu_cache_flush:
1113 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1114 mov r1, #7 << 5 @ 8 segments
1115 1: orr r3, r1, #63 << 26 @ 64 entries
1116 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1117 subs r3, r3, #1 << 26
1118 bcs 2b @ entries 63 to 0
1119 subs r1, r1, #1 << 5
1120 bcs 1b @ segments 7 to 0
1123 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1124 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1127 __fa526_cache_flush:
1131 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1132 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1133 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1136 __armv6_mmu_cache_flush:
1139 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1140 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1141 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1142 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1145 __armv7_mmu_cache_flush:
1148 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1149 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1152 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1155 mcr p15, 0, r10, c7, c10, 5 @ DMB
1156 stmfd sp!, {r0-r7, r9-r11}
1157 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1158 ands r3, r0, #0x7000000 @ extract loc from clidr
1159 mov r3, r3, lsr #23 @ left align loc bit field
1160 beq finished @ if loc is 0, then no need to clean
1161 mov r10, #0 @ start clean at cache level 0
1163 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1164 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1165 and r1, r1, #7 @ mask of the bits for current cache only
1166 cmp r1, #2 @ see what cache we have at this level
1167 blt skip @ skip if no cache, or just i-cache
1168 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1169 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1170 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1171 and r2, r1, #7 @ extract the length of the cache lines
1172 add r2, r2, #4 @ add 4 (line length offset)
1174 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1175 clz r5, r4 @ find bit position of way size increment
1177 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1179 mov r9, r4 @ create working copy of max way size
1181 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1182 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1183 THUMB( lsl r6, r9, r5 )
1184 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1185 THUMB( lsl r6, r7, r2 )
1186 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1187 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1188 subs r9, r9, #1 @ decrement the way
1190 subs r7, r7, #1 @ decrement the index
1193 add r10, r10, #2 @ increment cache number
1197 ldmfd sp!, {r0-r7, r9-r11}
1198 mov r10, #0 @ swith back to cache level 0
1199 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1201 mcr p15, 0, r10, c7, c10, 4 @ DSB
1202 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1203 mcr p15, 0, r10, c7, c10, 4 @ DSB
1204 mcr p15, 0, r10, c7, c5, 4 @ ISB
1207 __armv5tej_mmu_cache_flush:
1210 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1212 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1213 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1216 __armv4_mmu_cache_flush:
1219 mov r2, #64*1024 @ default: 32K dcache size (*2)
1220 mov r11, #32 @ default: 32 byte line size
1221 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1222 teq r3, r9 @ cache ID register present?
1227 mov r2, r2, lsl r1 @ base dcache size *2
1228 tst r3, #1 << 14 @ test M bit
1229 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1233 mov r11, r11, lsl r3 @ cache line size in bytes
1236 bic r1, r1, #63 @ align to longest cache line
1239 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1240 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1241 THUMB( add r1, r1, r11 )
1245 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1246 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1247 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1250 __armv3_mmu_cache_flush:
1251 __armv3_mpu_cache_flush:
1255 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1259 * Various debugging routines for printing hex characters and
1260 * memory, which again must be relocatable.
1264 .type phexbuf,#object
1266 .size phexbuf, . - phexbuf
1268 @ phex corrupts {r0, r1, r2, r3}
1269 phex: adr r3, phexbuf
1283 @ puts corrupts {r0, r1, r2, r3}
1285 1: ldrb r2, [r0], #1
1298 @ putc corrupts {r0, r1, r2, r3}
1305 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1306 memdump: mov r12, r0
1309 2: mov r0, r11, lsl #2
1317 ldr r0, [r12, r11, lsl #2]
1337 #ifdef CONFIG_ARM_VIRT_EXT
1339 __hyp_reentry_vectors:
1345 W(b) __enter_kernel @ hyp
1348 #endif /* CONFIG_ARM_VIRT_EXT */
1351 mov r0, #0 @ must be 0
1352 ARM( mov pc, r4 ) @ call kernel
1353 M_CLASS( add r4, r4, #1 ) @ enter in Thumb mode for M class
1354 THUMB( bx r4 ) @ entry point is always ARM for A/R classes
1359 .section ".stack", "aw", %nobits
1360 .L_user_stack: .space 4096