2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
18 * Note that these macros must not contain any code which is not
19 * 100% relocatable. Any attempt to do so will result in a crash.
20 * Please select one of the following when turning on debugging.
24 #if defined(CONFIG_DEBUG_ICEDCC)
26 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
27 .macro loadsp, rb, tmp
30 mcr p14, 0, \ch, c0, c5, 0
32 #elif defined(CONFIG_CPU_XSCALE)
33 .macro loadsp, rb, tmp
36 mcr p14, 0, \ch, c8, c0, 0
39 .macro loadsp, rb, tmp
42 mcr p14, 0, \ch, c1, c0, 0
48 #include CONFIG_DEBUG_LL_INCLUDE
54 #if defined(CONFIG_ARCH_SA1100)
55 .macro loadsp, rb, tmp
56 mov \rb, #0x80000000 @ physical base address
57 #ifdef CONFIG_DEBUG_LL_SER3
58 add \rb, \rb, #0x00050000 @ Ser3
60 add \rb, \rb, #0x00010000 @ Ser1
63 #elif defined(CONFIG_ARCH_S3C24XX)
64 .macro loadsp, rb, tmp
66 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
69 .macro loadsp, rb, tmp
87 .macro debug_reloc_start
90 kphex r6, 8 /* processor id */
92 kphex r7, 8 /* architecture id */
93 #ifdef CONFIG_CPU_CP15
95 mrc p15, 0, r0, c1, c0
96 kphex r0, 8 /* control reg */
99 kphex r5, 8 /* decompressed kernel start */
101 kphex r9, 8 /* decompressed kernel end */
103 kphex r4, 8 /* kernel execution address */
108 .macro debug_reloc_end
110 kphex r5, 8 /* end of kernel */
113 bl memdump /* dump 256 bytes at start of kernel */
117 .section ".start", #alloc, #execinstr
119 * sort out different calling conventions
122 .arm @ Always enter in ARM state
124 .type start,#function
130 THUMB( adr r12, BSYM(1f) )
133 .word 0x016f2818 @ Magic numbers to help the loader
134 .word start @ absolute load/run zImage address
135 .word _edata @ zImage end address
138 ARM_BE8( setend be ) @ go BE8 if compiled for BE8
140 #ifdef CONFIG_ARM_VIRT_EXT
141 bl __hyp_stub_install @ get into SVC mode, reversibly
143 mov r7, r1 @ save architecture ID
144 mov r8, r2 @ save atags pointer
146 #ifndef __ARM_ARCH_2__
148 * Booting from Angel - need to enter SVC mode and disable
149 * FIQs/IRQs (numeric definitions from angel arm.h source).
150 * We only do this if we were in user mode on entry.
152 mrs r2, cpsr @ get current mode
153 tst r2, #3 @ not user?
155 mov r0, #0x17 @ angel_SWIreason_EnterSVC
156 ARM( swi 0x123456 ) @ angel_SWI_ARM
157 THUMB( svc 0xab ) @ angel_SWI_THUMB
159 safe_svcmode_maskall r0
160 msr spsr_cxsf, r9 @ Save the CPU boot mode in
163 teqp pc, #0x0c000003 @ turn off interrupts
167 * Note that some cache flushing and other stuff may
168 * be needed here - is there an Angel SWI call for this?
172 * some architecture specific code can be inserted
173 * by the linker here, but it should preserve r7, r8, and r9.
178 #ifdef CONFIG_AUTO_ZRELADDR
179 @ determine final kernel image address
181 and r4, r4, #0xf8000000
182 add r4, r4, #TEXT_OFFSET
190 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
194 * We might be running at a different address. We need
195 * to fix up various pointers.
197 sub r0, r0, r1 @ calculate the delta offset
198 add r6, r6, r0 @ _edata
199 add r10, r10, r0 @ inflated kernel size location
202 * The kernel build system appends the size of the
203 * decompressed kernel at the end of the compressed data
204 * in little-endian form.
208 orr r9, r9, lr, lsl #8
211 orr r9, r9, lr, lsl #16
212 orr r9, r9, r10, lsl #24
214 #ifndef CONFIG_ZBOOT_ROM
215 /* malloc space is above the relocated stack (64k max) */
217 add r10, sp, #0x10000
220 * With ZBOOT_ROM the bss/stack is non relocatable,
221 * but someone could still run this code from RAM,
222 * in which case our reference is _edata.
227 mov r5, #0 @ init dtb size to 0
228 #ifdef CONFIG_ARM_APPENDED_DTB
233 * r4 = final kernel address
234 * r5 = appended dtb size (still unknown)
236 * r7 = architecture ID
237 * r8 = atags/device tree pointer
238 * r9 = size of decompressed image
239 * r10 = end of this image, including bss/stack/malloc space if non XIP
244 * if there are device trees (dtb) appended to zImage, advance r10 so that the
245 * dtb data will get relocated along with the kernel if necessary.
250 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
255 bne dtb_check_done @ not found
257 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
259 * OK... Let's do some funky business here.
260 * If we do have a DTB appended to zImage, and we do have
261 * an ATAG list around, we want the later to be translated
262 * and folded into the former here. To be on the safe side,
263 * let's temporarily move the stack away into the malloc
264 * area. No GOT fixup has occurred yet, but none of the
265 * code we're about to call uses any global variable.
268 stmfd sp!, {r0-r3, ip, lr}
275 * If returned value is 1, there is no ATAG at the location
276 * pointed by r8. Try the typical 0x100 offset from start
277 * of RAM and hope for the best.
280 sub r0, r4, #TEXT_OFFSET
286 ldmfd sp!, {r0-r3, ip, lr}
290 mov r8, r6 @ use the appended device tree
293 * Make sure that the DTB doesn't end up in the final
294 * kernel's .bss area. To do so, we adjust the decompressed
295 * kernel size to compensate if that .bss size is larger
296 * than the relocated code.
298 ldr r5, =_kernel_bss_size
299 adr r1, wont_overwrite
304 /* Get the dtb's size */
307 /* convert r5 (dtb size) to little endian */
308 eor r1, r5, r5, ror #16
309 bic r1, r1, #0x00ff0000
311 eor r5, r5, r1, lsr #8
314 /* preserve 64-bit alignment */
318 /* relocate some pointers past the appended dtb */
326 * Check to see if we will overwrite ourselves.
327 * r4 = final kernel address
328 * r9 = size of decompressed image
329 * r10 = end of this image, including bss/stack/malloc space if non XIP
331 * r4 - 16k page directory >= r10 -> OK
332 * r4 + image length <= address of wont_overwrite -> OK
338 adr r9, wont_overwrite
343 * Relocate ourselves past the end of the decompressed kernel.
345 * r10 = end of the decompressed kernel
346 * Because we always copy ahead, we need to do it from the end and go
347 * backward in case the source and destination overlap.
350 * Bump to the next 256-byte boundary with the size of
351 * the relocation code added. This avoids overwriting
352 * ourself when the offset is small.
354 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
357 /* Get start of code we want to copy and align it down. */
361 /* Relocate the hyp vector base if necessary */
362 #ifdef CONFIG_ARM_VIRT_EXT
364 and r0, r0, #MODE_MASK
375 sub r9, r6, r5 @ size to copy
376 add r9, r9, #31 @ rounded up to a multiple
377 bic r9, r9, #31 @ ... of 32 bytes
381 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
383 stmdb r9!, {r0 - r3, r10 - r12, lr}
386 /* Preserve offset to relocated code. */
389 #ifndef CONFIG_ZBOOT_ROM
390 /* cache_clean_flush may use the stack, so relocate it */
396 adr r0, BSYM(restart)
402 * If delta is zero, we are running at the address we were linked at.
406 * r4 = kernel execution address
407 * r5 = appended dtb size (0 if not present)
408 * r7 = architecture ID
420 #ifndef CONFIG_ZBOOT_ROM
422 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
423 * we need to fix up pointers into the BSS region.
424 * Note that the stack pointer has already been fixed up.
430 * Relocate all entries in the GOT table.
431 * Bump bss entries to _edata + dtb size
433 1: ldr r1, [r11, #0] @ relocate entries in the GOT
434 add r1, r1, r0 @ This fixes up C references
435 cmp r1, r2 @ if entry >= bss_start &&
436 cmphs r3, r1 @ bss_end > entry
437 addhi r1, r1, r5 @ entry += dtb size
438 str r1, [r11], #4 @ next entry
442 /* bump our bss pointers too */
449 * Relocate entries in the GOT table. We only relocate
450 * the entries that are outside the (relocated) BSS region.
452 1: ldr r1, [r11, #0] @ relocate entries in the GOT
453 cmp r1, r2 @ entry < bss_start ||
454 cmphs r3, r1 @ _end < entry
455 addlo r1, r1, r0 @ table. This fixes up the
456 str r1, [r11], #4 @ C references.
461 not_relocated: mov r0, #0
462 1: str r0, [r2], #4 @ clear bss
470 * The C runtime environment should now be setup sufficiently.
471 * Set up some pointers, and start decompressing.
472 * r4 = kernel execution address
473 * r7 = architecture ID
477 mov r1, sp @ malloc space above stack
478 add r2, sp, #0x10000 @ 64k max
483 mov r1, r7 @ restore architecture number
484 mov r2, r8 @ restore atags pointer
486 #ifdef CONFIG_ARM_VIRT_EXT
487 mrs r0, spsr @ Get saved CPU boot mode
488 and r0, r0, #MODE_MASK
489 cmp r0, #HYP_MODE @ if not booted in HYP mode...
490 bne __enter_kernel @ boot kernel directly
492 adr r12, .L__hyp_reentry_vectors_offset
497 __HVC(0) @ otherwise bounce to hyp mode
499 b . @ should never be reached
502 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
510 .word __bss_start @ r2
513 .word input_data_end - 4 @ r10 (inflated size location)
514 .word _got_start @ r11
516 .word .L_user_stack_end @ sp
519 #ifdef CONFIG_ARCH_RPC
521 params: ldr r0, =0x10000100 @ params_phys for RPC
528 * Turn on the cache. We need to setup some page tables so that we
529 * can have both the I and D caches on.
531 * We place the page tables 16k down from the kernel execution address,
532 * and we hope that nothing else is using it. If we're using it, we
536 * r4 = kernel execution address
537 * r7 = architecture number
540 * r0, r1, r2, r3, r9, r10, r12 corrupted
541 * This routine must preserve:
545 cache_on: mov r3, #8 @ cache_on function
549 * Initialize the highest priority protection region, PR7
550 * to cover all 32bit address and cacheable and bufferable.
552 __armv4_mpu_cache_on:
553 mov r0, #0x3f @ 4G, the whole
554 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
555 mcr p15, 0, r0, c6, c7, 1
558 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
559 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
560 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
563 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
564 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
567 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
568 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
569 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
570 mrc p15, 0, r0, c1, c0, 0 @ read control reg
571 @ ...I .... ..D. WC.M
572 orr r0, r0, #0x002d @ .... .... ..1. 11.1
573 orr r0, r0, #0x1000 @ ...1 .... .... ....
575 mcr p15, 0, r0, c1, c0, 0 @ write control reg
578 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
579 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
582 __armv3_mpu_cache_on:
583 mov r0, #0x3f @ 4G, the whole
584 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
587 mcr p15, 0, r0, c2, c0, 0 @ cache on
588 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
591 mcr p15, 0, r0, c5, c0, 0 @ access permission
594 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
596 * ?? ARMv3 MMU does not allow reading the control register,
597 * does this really work on ARMv3 MPU?
599 mrc p15, 0, r0, c1, c0, 0 @ read control reg
600 @ .... .... .... WC.M
601 orr r0, r0, #0x000d @ .... .... .... 11.1
602 /* ?? this overwrites the value constructed above? */
604 mcr p15, 0, r0, c1, c0, 0 @ write control reg
606 /* ?? invalidate for the second time? */
607 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
610 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
616 __setup_mmu: sub r3, r4, #16384 @ Page directory size
617 bic r3, r3, #0xff @ Align the pointer
620 * Initialise the page tables, turning on the cacheable and bufferable
621 * bits for the RAM area only.
625 mov r9, r9, lsl #18 @ start of RAM
626 add r10, r9, #0x10000000 @ a reasonable RAM size
627 mov r1, #0x12 @ XN|U + section mapping
628 orr r1, r1, #3 << 10 @ AP=11
630 1: cmp r1, r9 @ if virt > start of RAM
631 cmphs r10, r1 @ && end of RAM > virt
632 bic r1, r1, #0x1c @ clear XN|U + C + B
633 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
634 orrhs r1, r1, r6 @ set RAM section settings
635 str r1, [r0], #4 @ 1:1 mapping
640 * If ever we are running from Flash, then we surely want the cache
641 * to be enabled also for our execution instance... We map 2MB of it
642 * so there is no map overlap problem for up to 1 MB compressed kernel.
643 * If the execution is in RAM then we would only be duplicating the above.
645 orr r1, r6, #0x04 @ ensure B is set for this
649 orr r1, r1, r2, lsl #20
650 add r0, r3, r2, lsl #2
657 @ Enable unaligned access on v6, to allow better code generation
658 @ for the decompressor C code:
659 __armv6_mmu_cache_on:
660 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
661 bic r0, r0, #2 @ A (no unaligned access fault)
662 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
663 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
664 b __armv4_mmu_cache_on
666 __arm926ejs_mmu_cache_on:
667 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
668 mov r0, #4 @ put dcache in WT mode
669 mcr p15, 7, r0, c15, c0, 0
672 __armv4_mmu_cache_on:
675 mov r6, #CB_BITS | 0x12 @ U
678 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
679 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
680 mrc p15, 0, r0, c1, c0, 0 @ read control reg
681 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
683 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
684 bl __common_mmu_cache_on
686 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
690 __armv7_mmu_cache_on:
693 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
695 movne r6, #CB_BITS | 0x02 @ !XN
698 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
700 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
702 mrc p15, 0, r0, c1, c0, 0 @ read control reg
703 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
704 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
705 orr r0, r0, #0x003c @ write buffer
706 bic r0, r0, #2 @ A (no unaligned access fault)
707 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
708 @ (needed for ARM1176)
710 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
711 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
712 orrne r0, r0, #1 @ MMU enabled
713 movne r1, #0xfffffffd @ domain 0 = client
714 bic r6, r6, #1 << 31 @ 32-bit translation system
715 bic r6, r6, #3 << 0 @ use only ttbr0
716 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
717 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
718 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
720 mcr p15, 0, r0, c7, c5, 4 @ ISB
721 mcr p15, 0, r0, c1, c0, 0 @ load control register
722 mrc p15, 0, r0, c1, c0, 0 @ and read it back
724 mcr p15, 0, r0, c7, c5, 4 @ ISB
729 mov r6, #CB_BITS | 0x12 @ U
732 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
733 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
734 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
735 mrc p15, 0, r0, c1, c0, 0 @ read control reg
736 orr r0, r0, #0x1000 @ I-cache enable
737 bl __common_mmu_cache_on
739 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
742 __common_mmu_cache_on:
743 #ifndef CONFIG_THUMB2_KERNEL
745 orr r0, r0, #0x000d @ Write buffer, mmu
748 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
749 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
751 .align 5 @ cache line aligned
752 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
753 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
754 sub pc, lr, r0, lsr #32 @ properly flush pipeline
757 #define PROC_ENTRY_SIZE (4*5)
760 * Here follow the relocatable cache support functions for the
761 * various processors. This is a generic hook for locating an
762 * entry and jumping to an instruction at the specified offset
763 * from the start of the block. Please note this is all position
773 call_cache_fn: adr r12, proc_types
774 #ifdef CONFIG_CPU_CP15
775 mrc p15, 0, r9, c0, c0 @ get processor ID
777 ldr r9, =CONFIG_PROCESSOR_ID
779 1: ldr r1, [r12, #0] @ get value
780 ldr r2, [r12, #4] @ get mask
781 eor r1, r1, r9 @ (real ^ match)
783 ARM( addeq pc, r12, r3 ) @ call cache function
784 THUMB( addeq r12, r3 )
785 THUMB( moveq pc, r12 ) @ call cache function
786 add r12, r12, #PROC_ENTRY_SIZE
790 * Table for cache operations. This is basically:
793 * - 'cache on' method instruction
794 * - 'cache off' method instruction
795 * - 'cache flush' method instruction
797 * We match an entry using: ((real_id ^ match) & mask) == 0
799 * Writethrough caches generally only need 'on' and 'off'
800 * methods. Writeback caches _must_ have the flush method
804 .type proc_types,#object
806 .word 0x41000000 @ old ARM ID
815 .word 0x41007000 @ ARM7/710
824 .word 0x41807200 @ ARM720T (writethrough)
826 W(b) __armv4_mmu_cache_on
827 W(b) __armv4_mmu_cache_off
831 .word 0x41007400 @ ARM74x
833 W(b) __armv3_mpu_cache_on
834 W(b) __armv3_mpu_cache_off
835 W(b) __armv3_mpu_cache_flush
837 .word 0x41009400 @ ARM94x
839 W(b) __armv4_mpu_cache_on
840 W(b) __armv4_mpu_cache_off
841 W(b) __armv4_mpu_cache_flush
843 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
845 W(b) __arm926ejs_mmu_cache_on
846 W(b) __armv4_mmu_cache_off
847 W(b) __armv5tej_mmu_cache_flush
849 .word 0x00007000 @ ARM7 IDs
858 @ Everything from here on will be the new ID system.
860 .word 0x4401a100 @ sa110 / sa1100
862 W(b) __armv4_mmu_cache_on
863 W(b) __armv4_mmu_cache_off
864 W(b) __armv4_mmu_cache_flush
866 .word 0x6901b110 @ sa1110
868 W(b) __armv4_mmu_cache_on
869 W(b) __armv4_mmu_cache_off
870 W(b) __armv4_mmu_cache_flush
873 .word 0xffffff00 @ PXA9xx
874 W(b) __armv4_mmu_cache_on
875 W(b) __armv4_mmu_cache_off
876 W(b) __armv4_mmu_cache_flush
878 .word 0x56158000 @ PXA168
880 W(b) __armv4_mmu_cache_on
881 W(b) __armv4_mmu_cache_off
882 W(b) __armv5tej_mmu_cache_flush
884 .word 0x56050000 @ Feroceon
886 W(b) __armv4_mmu_cache_on
887 W(b) __armv4_mmu_cache_off
888 W(b) __armv5tej_mmu_cache_flush
890 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
891 /* this conflicts with the standard ARMv5TE entry */
892 .long 0x41009260 @ Old Feroceon
894 b __armv4_mmu_cache_on
895 b __armv4_mmu_cache_off
896 b __armv5tej_mmu_cache_flush
899 .word 0x66015261 @ FA526
901 W(b) __fa526_cache_on
902 W(b) __armv4_mmu_cache_off
903 W(b) __fa526_cache_flush
905 @ These match on the architecture ID
907 .word 0x00020000 @ ARMv4T
909 W(b) __armv4_mmu_cache_on
910 W(b) __armv4_mmu_cache_off
911 W(b) __armv4_mmu_cache_flush
913 .word 0x00050000 @ ARMv5TE
915 W(b) __armv4_mmu_cache_on
916 W(b) __armv4_mmu_cache_off
917 W(b) __armv4_mmu_cache_flush
919 .word 0x00060000 @ ARMv5TEJ
921 W(b) __armv4_mmu_cache_on
922 W(b) __armv4_mmu_cache_off
923 W(b) __armv5tej_mmu_cache_flush
925 .word 0x0007b000 @ ARMv6
927 W(b) __armv6_mmu_cache_on
928 W(b) __armv4_mmu_cache_off
929 W(b) __armv6_mmu_cache_flush
931 .word 0x000f0000 @ new CPU Id
933 W(b) __armv7_mmu_cache_on
934 W(b) __armv7_mmu_cache_off
935 W(b) __armv7_mmu_cache_flush
937 .word 0 @ unrecognised type
946 .size proc_types, . - proc_types
949 * If you get a "non-constant expression in ".if" statement"
950 * error from the assembler on this line, check that you have
951 * not accidentally written a "b" instruction where you should
954 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
955 .error "The size of one or more proc_types entries is wrong."
959 * Turn off the Cache and MMU. ARMv3 does not support
960 * reading the control register, but ARMv4 does.
963 * r0, r1, r2, r3, r9, r12 corrupted
964 * This routine must preserve:
968 cache_off: mov r3, #12 @ cache_off function
971 __armv4_mpu_cache_off:
972 mrc p15, 0, r0, c1, c0
974 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
976 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
977 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
978 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
981 __armv3_mpu_cache_off:
982 mrc p15, 0, r0, c1, c0
984 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
986 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
989 __armv4_mmu_cache_off:
991 mrc p15, 0, r0, c1, c0
993 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
995 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
996 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1000 __armv7_mmu_cache_off:
1001 mrc p15, 0, r0, c1, c0
1007 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1009 bl __armv7_mmu_cache_flush
1012 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1014 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1015 mcr p15, 0, r0, c7, c10, 4 @ DSB
1016 mcr p15, 0, r0, c7, c5, 4 @ ISB
1020 * Clean and flush the cache to maintain consistency.
1023 * r1, r2, r3, r9, r10, r11, r12 corrupted
1024 * This routine must preserve:
1032 __armv4_mpu_cache_flush:
1035 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1036 mov r1, #7 << 5 @ 8 segments
1037 1: orr r3, r1, #63 << 26 @ 64 entries
1038 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1039 subs r3, r3, #1 << 26
1040 bcs 2b @ entries 63 to 0
1041 subs r1, r1, #1 << 5
1042 bcs 1b @ segments 7 to 0
1045 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1046 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1049 __fa526_cache_flush:
1051 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1052 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1053 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1056 __armv6_mmu_cache_flush:
1058 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1059 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1060 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1061 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1064 __armv7_mmu_cache_flush:
1065 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1066 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1069 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1072 mcr p15, 0, r10, c7, c10, 5 @ DMB
1073 stmfd sp!, {r0-r7, r9-r11}
1074 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1075 ands r3, r0, #0x7000000 @ extract loc from clidr
1076 mov r3, r3, lsr #23 @ left align loc bit field
1077 beq finished @ if loc is 0, then no need to clean
1078 mov r10, #0 @ start clean at cache level 0
1080 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1081 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1082 and r1, r1, #7 @ mask of the bits for current cache only
1083 cmp r1, #2 @ see what cache we have at this level
1084 blt skip @ skip if no cache, or just i-cache
1085 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1086 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1087 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1088 and r2, r1, #7 @ extract the length of the cache lines
1089 add r2, r2, #4 @ add 4 (line length offset)
1091 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1092 clz r5, r4 @ find bit position of way size increment
1094 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1096 mov r9, r4 @ create working copy of max way size
1098 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1099 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1100 THUMB( lsl r6, r9, r5 )
1101 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1102 THUMB( lsl r6, r7, r2 )
1103 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1104 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1105 subs r9, r9, #1 @ decrement the way
1107 subs r7, r7, #1 @ decrement the index
1110 add r10, r10, #2 @ increment cache number
1114 ldmfd sp!, {r0-r7, r9-r11}
1115 mov r10, #0 @ swith back to cache level 0
1116 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1118 mcr p15, 0, r10, c7, c10, 4 @ DSB
1119 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1120 mcr p15, 0, r10, c7, c10, 4 @ DSB
1121 mcr p15, 0, r10, c7, c5, 4 @ ISB
1124 __armv5tej_mmu_cache_flush:
1125 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1127 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1128 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1131 __armv4_mmu_cache_flush:
1132 mov r2, #64*1024 @ default: 32K dcache size (*2)
1133 mov r11, #32 @ default: 32 byte line size
1134 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1135 teq r3, r9 @ cache ID register present?
1140 mov r2, r2, lsl r1 @ base dcache size *2
1141 tst r3, #1 << 14 @ test M bit
1142 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1146 mov r11, r11, lsl r3 @ cache line size in bytes
1149 bic r1, r1, #63 @ align to longest cache line
1152 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1153 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1154 THUMB( add r1, r1, r11 )
1158 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1159 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1160 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1163 __armv3_mmu_cache_flush:
1164 __armv3_mpu_cache_flush:
1166 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1170 * Various debugging routines for printing hex characters and
1171 * memory, which again must be relocatable.
1175 .type phexbuf,#object
1177 .size phexbuf, . - phexbuf
1179 @ phex corrupts {r0, r1, r2, r3}
1180 phex: adr r3, phexbuf
1194 @ puts corrupts {r0, r1, r2, r3}
1196 1: ldrb r2, [r0], #1
1209 @ putc corrupts {r0, r1, r2, r3}
1216 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1217 memdump: mov r12, r0
1220 2: mov r0, r11, lsl #2
1228 ldr r0, [r12, r11, lsl #2]
1248 #ifdef CONFIG_ARM_VIRT_EXT
1250 __hyp_reentry_vectors:
1256 W(b) __enter_kernel @ hyp
1259 #endif /* CONFIG_ARM_VIRT_EXT */
1262 mov r0, #0 @ must be 0
1263 ARM( mov pc, r4 ) @ call kernel
1264 THUMB( bx r4 ) @ entry point is always ARM
1269 .section ".stack", "aw", %nobits
1270 .L_user_stack: .space 4096