2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
22 #if defined(CONFIG_DEBUG_ICEDCC)
25 .macro loadsp, rb, tmp
28 mcr p14, 0, \ch, c0, c5, 0
30 #elif defined(CONFIG_CPU_V7)
31 .macro loadsp, rb, tmp
34 wait: mrc p14, 0, pc, c0, c1, 0
36 mcr p14, 0, \ch, c0, c5, 0
38 #elif defined(CONFIG_CPU_XSCALE)
39 .macro loadsp, rb, tmp
42 mcr p14, 0, \ch, c8, c0, 0
45 .macro loadsp, rb, tmp
48 mcr p14, 0, \ch, c1, c0, 0
54 #include <mach/debug-macro.S>
60 #if defined(CONFIG_ARCH_SA1100)
61 .macro loadsp, rb, tmp
62 mov \rb, #0x80000000 @ physical base address
63 #ifdef CONFIG_DEBUG_LL_SER3
64 add \rb, \rb, #0x00050000 @ Ser3
66 add \rb, \rb, #0x00010000 @ Ser1
69 #elif defined(CONFIG_ARCH_S3C2410)
70 .macro loadsp, rb, tmp
72 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
75 .macro loadsp, rb, tmp
93 .macro debug_reloc_start
96 kphex r6, 8 /* processor id */
98 kphex r7, 8 /* architecture id */
99 #ifdef CONFIG_CPU_CP15
101 mrc p15, 0, r0, c1, c0
102 kphex r0, 8 /* control reg */
105 kphex r5, 8 /* decompressed kernel start */
107 kphex r9, 8 /* decompressed kernel end */
109 kphex r4, 8 /* kernel execution address */
114 .macro debug_reloc_end
116 kphex r5, 8 /* end of kernel */
119 bl memdump /* dump 256 bytes at start of kernel */
123 .section ".start", #alloc, #execinstr
125 * sort out different calling conventions
129 .type start,#function
135 .word 0x016f2818 @ Magic numbers to help the loader
136 .word start @ absolute load/run zImage address
137 .word _edata @ zImage end address
138 1: mov r7, r1 @ save architecture ID
139 mov r8, r2 @ save atags pointer
141 #ifndef __ARM_ARCH_2__
143 * Booting from Angel - need to enter SVC mode and disable
144 * FIQs/IRQs (numeric definitions from angel arm.h source).
145 * We only do this if we were in user mode on entry.
147 mrs r2, cpsr @ get current mode
148 tst r2, #3 @ not user?
150 mov r0, #0x17 @ angel_SWIreason_EnterSVC
151 ARM( swi 0x123456 ) @ angel_SWI_ARM
152 THUMB( svc 0xab ) @ angel_SWI_THUMB
154 mrs r2, cpsr @ turn off interrupts to
155 orr r2, r2, #0xc0 @ prevent angel from running
158 teqp pc, #0x0c000003 @ turn off interrupts
162 * Note that some cache flushing and other stuff may
163 * be needed here - is there an Angel SWI call for this?
167 * some architecture specific code can be inserted
168 * by the linker here, but it should preserve r7, r8, and r9.
173 ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
174 THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip} )
175 THUMB( ldr sp, [r0, #28] )
176 subs r0, r0, r1 @ calculate the delta offset
178 @ if delta is zero, we are
179 beq not_relocated @ running at the address we
183 * We're running at a different address. We need to fix
184 * up various pointers:
185 * r5 - zImage base address (_start)
186 * r6 - size of decompressed image
194 #ifndef CONFIG_ZBOOT_ROM
196 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
197 * we need to fix up pointers into the BSS region.
207 * Relocate all entries in the GOT table.
209 1: ldr r1, [r11, #0] @ relocate entries in the GOT
210 add r1, r1, r0 @ table. This fixes up the
211 str r1, [r11], #4 @ C references.
217 * Relocate entries in the GOT table. We only relocate
218 * the entries that are outside the (relocated) BSS region.
220 1: ldr r1, [r11, #0] @ relocate entries in the GOT
221 cmp r1, r2 @ entry < bss_start ||
222 cmphs r3, r1 @ _end < entry
223 addlo r1, r1, r0 @ table. This fixes up the
224 str r1, [r11], #4 @ C references.
229 not_relocated: mov r0, #0
230 1: str r0, [r2], #4 @ clear bss
238 * The C runtime environment should now be setup
239 * sufficiently. Turn the cache on, set up some
240 * pointers, and start decompressing.
244 mov r1, sp @ malloc space above stack
245 add r2, sp, #0x10000 @ 64k max
248 * Check to see if we will overwrite ourselves.
249 * r4 = final kernel address
250 * r5 = start of this image
251 * r6 = size of decompressed image
252 * r2 = end of malloc space (and therefore this image)
255 * r4 + image length <= r5 -> OK
263 mov r5, r2 @ decompress after malloc space
268 add r0, r0, #127 + 128 @ alignment + stack
269 bic r0, r0, #127 @ align the kernel length
271 * r0 = decompressed kernel length
273 * r4 = kernel execution address
274 * r5 = decompressed kernel start
275 * r7 = architecture ID
277 * r9-r12,r14 = corrupted
279 add r1, r5, r0 @ end of decompressed kernel
283 1: ldmia r2!, {r9 - r12, r14} @ copy relocation code
284 stmia r1!, {r9 - r12, r14}
285 ldmia r2!, {r9 - r12, r14}
286 stmia r1!, {r9 - r12, r14}
290 add sp, sp, #128 @ relocate the stack
293 ARM( add pc, r5, r0 ) @ call relocation code
294 THUMB( add r12, r5, r0 )
295 THUMB( mov pc, r12 ) @ call relocation code
298 * We're not in danger of overwriting ourselves. Do this the simple way.
300 * r4 = kernel execution address
301 * r7 = architecture ID
303 wont_overwrite: mov r0, r4
311 .word __bss_start @ r2
315 .word _image_size @ r6
316 .word _got_start @ r11
318 .word user_stack+4096 @ sp
319 LC1: .word reloc_end - reloc_start
322 #ifdef CONFIG_ARCH_RPC
324 params: ldr r0, =params_phys
331 * Turn on the cache. We need to setup some page tables so that we
332 * can have both the I and D caches on.
334 * We place the page tables 16k down from the kernel execution address,
335 * and we hope that nothing else is using it. If we're using it, we
339 * r4 = kernel execution address
340 * r7 = architecture number
342 * r9 = run-time address of "start" (???)
344 * r1, r2, r3, r9, r10, r12 corrupted
345 * This routine must preserve:
349 cache_on: mov r3, #8 @ cache_on function
353 * Initialize the highest priority protection region, PR7
354 * to cover all 32bit address and cacheable and bufferable.
356 __armv4_mpu_cache_on:
357 mov r0, #0x3f @ 4G, the whole
358 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
359 mcr p15, 0, r0, c6, c7, 1
362 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
363 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
364 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
367 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
368 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
371 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
372 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
373 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
374 mrc p15, 0, r0, c1, c0, 0 @ read control reg
375 @ ...I .... ..D. WC.M
376 orr r0, r0, #0x002d @ .... .... ..1. 11.1
377 orr r0, r0, #0x1000 @ ...1 .... .... ....
379 mcr p15, 0, r0, c1, c0, 0 @ write control reg
382 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
383 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
386 __armv3_mpu_cache_on:
387 mov r0, #0x3f @ 4G, the whole
388 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
391 mcr p15, 0, r0, c2, c0, 0 @ cache on
392 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
395 mcr p15, 0, r0, c5, c0, 0 @ access permission
398 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
399 mrc p15, 0, r0, c1, c0, 0 @ read control reg
400 @ .... .... .... WC.M
401 orr r0, r0, #0x000d @ .... .... .... 11.1
403 mcr p15, 0, r0, c1, c0, 0 @ write control reg
405 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
408 __setup_mmu: sub r3, r4, #16384 @ Page directory size
409 bic r3, r3, #0xff @ Align the pointer
412 * Initialise the page tables, turning on the cacheable and bufferable
413 * bits for the RAM area only.
417 mov r9, r9, lsl #18 @ start of RAM
418 add r10, r9, #0x10000000 @ a reasonable RAM size
422 1: cmp r1, r9 @ if virt > start of RAM
423 orrhs r1, r1, #0x0c @ set cacheable, bufferable
424 cmp r1, r10 @ if virt > end of RAM
425 bichs r1, r1, #0x0c @ clear cacheable, bufferable
426 str r1, [r0], #4 @ 1:1 mapping
431 * If ever we are running from Flash, then we surely want the cache
432 * to be enabled also for our execution instance... We map 2MB of it
433 * so there is no map overlap problem for up to 1 MB compressed kernel.
434 * If the execution is in RAM then we would only be duplicating the above.
439 orr r1, r1, r2, lsl #20
440 add r0, r3, r2, lsl #2
447 __armv4_mmu_cache_on:
452 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
453 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
454 mrc p15, 0, r0, c1, c0, 0 @ read control reg
455 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
457 #ifdef CONFIG_CPU_ENDIAN_BE8
458 orr r0, r0, #1 << 25 @ big-endian page tables
460 bl __common_mmu_cache_on
462 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
466 __armv7_mmu_cache_on:
469 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
473 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
475 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
477 mrc p15, 0, r0, c1, c0, 0 @ read control reg
478 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
479 orr r0, r0, #0x003c @ write buffer
481 #ifdef CONFIG_CPU_ENDIAN_BE8
482 orr r0, r0, #1 << 25 @ big-endian page tables
484 orrne r0, r0, #1 @ MMU enabled
486 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
487 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
489 mcr p15, 0, r0, c1, c0, 0 @ load control register
490 mrc p15, 0, r0, c1, c0, 0 @ and read it back
492 mcr p15, 0, r0, c7, c5, 4 @ ISB
499 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
500 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
501 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
502 mrc p15, 0, r0, c1, c0, 0 @ read control reg
503 orr r0, r0, #0x1000 @ I-cache enable
504 bl __common_mmu_cache_on
506 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
513 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
514 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
516 bl __common_mmu_cache_on
518 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
521 __common_mmu_cache_on:
522 #ifndef CONFIG_THUMB2_KERNEL
524 orr r0, r0, #0x000d @ Write buffer, mmu
527 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
528 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
530 .align 5 @ cache line aligned
531 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
532 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
533 sub pc, lr, r0, lsr #32 @ properly flush pipeline
537 * All code following this line is relocatable. It is relocated by
538 * the above code to the end of the decompressed kernel image and
539 * executed there. During this time, we have no stacks.
541 * r0 = decompressed kernel length
543 * r4 = kernel execution address
544 * r5 = decompressed kernel start
545 * r7 = architecture ID
547 * r9-r12,r14 = corrupted
550 reloc_start: add r9, r5, r0
551 sub r9, r9, #128 @ do not copy the stack
556 ldmia r5!, {r0, r2, r3, r10 - r12, r14} @ relocate kernel
557 stmia r1!, {r0, r2, r3, r10 - r12, r14}
563 add sp, sp, #128 @ relocate the stack
566 call_kernel: bl cache_clean_flush
568 mov r0, #0 @ must be zero
569 mov r1, r7 @ restore architecture number
570 mov r2, r8 @ restore atags pointer
571 mov pc, r4 @ call kernel
574 * Here follow the relocatable cache support functions for the
575 * various processors. This is a generic hook for locating an
576 * entry and jumping to an instruction at the specified offset
577 * from the start of the block. Please note this is all position
587 call_cache_fn: adr r12, proc_types
588 #ifdef CONFIG_CPU_CP15
589 mrc p15, 0, r9, c0, c0 @ get processor ID
591 ldr r9, =CONFIG_PROCESSOR_ID
593 1: ldr r1, [r12, #0] @ get value
594 ldr r2, [r12, #4] @ get mask
595 eor r1, r1, r9 @ (real ^ match)
597 ARM( addeq pc, r12, r3 ) @ call cache function
598 THUMB( addeq r12, r3 )
599 THUMB( moveq pc, r12 ) @ call cache function
604 * Table for cache operations. This is basically:
607 * - 'cache on' method instruction
608 * - 'cache off' method instruction
609 * - 'cache flush' method instruction
611 * We match an entry using: ((real_id ^ match) & mask) == 0
613 * Writethrough caches generally only need 'on' and 'off'
614 * methods. Writeback caches _must_ have the flush method
618 .type proc_types,#object
620 .word 0x41560600 @ ARM6/610
622 W(b) __arm6_mmu_cache_off @ works, but slow
623 W(b) __arm6_mmu_cache_off
626 @ b __arm6_mmu_cache_on @ untested
627 @ b __arm6_mmu_cache_off
628 @ b __armv3_mmu_cache_flush
630 .word 0x00000000 @ old ARM ID
639 .word 0x41007000 @ ARM7/710
641 W(b) __arm7_mmu_cache_off
642 W(b) __arm7_mmu_cache_off
646 .word 0x41807200 @ ARM720T (writethrough)
648 W(b) __armv4_mmu_cache_on
649 W(b) __armv4_mmu_cache_off
653 .word 0x41007400 @ ARM74x
655 W(b) __armv3_mpu_cache_on
656 W(b) __armv3_mpu_cache_off
657 W(b) __armv3_mpu_cache_flush
659 .word 0x41009400 @ ARM94x
661 W(b) __armv4_mpu_cache_on
662 W(b) __armv4_mpu_cache_off
663 W(b) __armv4_mpu_cache_flush
665 .word 0x00007000 @ ARM7 IDs
674 @ Everything from here on will be the new ID system.
676 .word 0x4401a100 @ sa110 / sa1100
678 W(b) __armv4_mmu_cache_on
679 W(b) __armv4_mmu_cache_off
680 W(b) __armv4_mmu_cache_flush
682 .word 0x6901b110 @ sa1110
684 W(b) __armv4_mmu_cache_on
685 W(b) __armv4_mmu_cache_off
686 W(b) __armv4_mmu_cache_flush
689 .word 0xff0ffff0 @ PXA935
690 W(b) __armv4_mmu_cache_on
691 W(b) __armv4_mmu_cache_off
692 W(b) __armv4_mmu_cache_flush
694 .word 0x56158000 @ PXA168
696 W(b) __armv4_mmu_cache_on
697 W(b) __armv4_mmu_cache_off
698 W(b) __armv5tej_mmu_cache_flush
701 .word 0xff0ffff0 @ PXA935
702 W(b) __armv4_mmu_cache_on
703 W(b) __armv4_mmu_cache_off
704 W(b) __armv4_mmu_cache_flush
706 .word 0x56050000 @ Feroceon
708 W(b) __armv4_mmu_cache_on
709 W(b) __armv4_mmu_cache_off
710 W(b) __armv5tej_mmu_cache_flush
712 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
713 /* this conflicts with the standard ARMv5TE entry */
714 .long 0x41009260 @ Old Feroceon
716 b __armv4_mmu_cache_on
717 b __armv4_mmu_cache_off
718 b __armv5tej_mmu_cache_flush
721 .word 0x66015261 @ FA526
723 W(b) __fa526_cache_on
724 W(b) __armv4_mmu_cache_off
725 W(b) __fa526_cache_flush
727 @ These match on the architecture ID
729 .word 0x00020000 @ ARMv4T
731 W(b) __armv4_mmu_cache_on
732 W(b) __armv4_mmu_cache_off
733 W(b) __armv4_mmu_cache_flush
735 .word 0x00050000 @ ARMv5TE
737 W(b) __armv4_mmu_cache_on
738 W(b) __armv4_mmu_cache_off
739 W(b) __armv4_mmu_cache_flush
741 .word 0x00060000 @ ARMv5TEJ
743 W(b) __armv4_mmu_cache_on
744 W(b) __armv4_mmu_cache_off
745 W(b) __armv5tej_mmu_cache_flush
747 .word 0x0007b000 @ ARMv6
749 W(b) __armv4_mmu_cache_on
750 W(b) __armv4_mmu_cache_off
751 W(b) __armv6_mmu_cache_flush
753 .word 0x560f5810 @ Marvell PJ4 ARMv6
755 W(b) __armv4_mmu_cache_on
756 W(b) __armv4_mmu_cache_off
757 W(b) __armv6_mmu_cache_flush
759 .word 0x000f0000 @ new CPU Id
761 W(b) __armv7_mmu_cache_on
762 W(b) __armv7_mmu_cache_off
763 W(b) __armv7_mmu_cache_flush
765 .word 0 @ unrecognised type
774 .size proc_types, . - proc_types
777 * Turn off the Cache and MMU. ARMv3 does not support
778 * reading the control register, but ARMv4 does.
780 * On exit, r0, r1, r2, r3, r9, r12 corrupted
781 * This routine must preserve: r4, r6, r7
784 cache_off: mov r3, #12 @ cache_off function
787 __armv4_mpu_cache_off:
788 mrc p15, 0, r0, c1, c0
790 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
792 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
793 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
794 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
797 __armv3_mpu_cache_off:
798 mrc p15, 0, r0, c1, c0
800 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
802 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
805 __armv4_mmu_cache_off:
807 mrc p15, 0, r0, c1, c0
809 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
811 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
812 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
816 __armv7_mmu_cache_off:
817 mrc p15, 0, r0, c1, c0
823 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
825 bl __armv7_mmu_cache_flush
828 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
830 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
831 mcr p15, 0, r0, c7, c10, 4 @ DSB
832 mcr p15, 0, r0, c7, c5, 4 @ ISB
835 __arm6_mmu_cache_off:
836 mov r0, #0x00000030 @ ARM6 control reg.
837 b __armv3_mmu_cache_off
839 __arm7_mmu_cache_off:
840 mov r0, #0x00000070 @ ARM7 control reg.
841 b __armv3_mmu_cache_off
843 __armv3_mmu_cache_off:
844 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
846 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
847 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
851 * Clean and flush the cache to maintain consistency.
854 * r1, r2, r3, r9, r11, r12 corrupted
855 * This routine must preserve:
863 __armv4_mpu_cache_flush:
866 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
867 mov r1, #7 << 5 @ 8 segments
868 1: orr r3, r1, #63 << 26 @ 64 entries
869 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
870 subs r3, r3, #1 << 26
871 bcs 2b @ entries 63 to 0
873 bcs 1b @ segments 7 to 0
876 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
877 mcr p15, 0, ip, c7, c10, 4 @ drain WB
882 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
883 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
884 mcr p15, 0, r1, c7, c10, 4 @ drain WB
887 __armv6_mmu_cache_flush:
889 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
890 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
891 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
892 mcr p15, 0, r1, c7, c10, 4 @ drain WB
895 __armv7_mmu_cache_flush:
896 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
897 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
900 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
903 mcr p15, 0, r10, c7, c10, 5 @ DMB
904 stmfd sp!, {r0-r7, r9-r11}
905 mrc p15, 1, r0, c0, c0, 1 @ read clidr
906 ands r3, r0, #0x7000000 @ extract loc from clidr
907 mov r3, r3, lsr #23 @ left align loc bit field
908 beq finished @ if loc is 0, then no need to clean
909 mov r10, #0 @ start clean at cache level 0
911 add r2, r10, r10, lsr #1 @ work out 3x current cache level
912 mov r1, r0, lsr r2 @ extract cache type bits from clidr
913 and r1, r1, #7 @ mask of the bits for current cache only
914 cmp r1, #2 @ see what cache we have at this level
915 blt skip @ skip if no cache, or just i-cache
916 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
917 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
918 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
919 and r2, r1, #7 @ extract the length of the cache lines
920 add r2, r2, #4 @ add 4 (line length offset)
922 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
923 clz r5, r4 @ find bit position of way size increment
925 ands r7, r7, r1, lsr #13 @ extract max number of the index size
927 mov r9, r4 @ create working copy of max way size
929 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
930 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
931 THUMB( lsl r6, r9, r5 )
932 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
933 THUMB( lsl r6, r7, r2 )
934 THUMB( orr r11, r11, r6 ) @ factor index number into r11
935 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
936 subs r9, r9, #1 @ decrement the way
938 subs r7, r7, #1 @ decrement the index
941 add r10, r10, #2 @ increment cache number
945 ldmfd sp!, {r0-r7, r9-r11}
946 mov r10, #0 @ swith back to cache level 0
947 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
949 mcr p15, 0, r10, c7, c10, 4 @ DSB
950 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
951 mcr p15, 0, r10, c7, c10, 4 @ DSB
952 mcr p15, 0, r10, c7, c5, 4 @ ISB
955 __armv5tej_mmu_cache_flush:
956 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
958 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
959 mcr p15, 0, r0, c7, c10, 4 @ drain WB
962 __armv4_mmu_cache_flush:
963 mov r2, #64*1024 @ default: 32K dcache size (*2)
964 mov r11, #32 @ default: 32 byte line size
965 mrc p15, 0, r3, c0, c0, 1 @ read cache type
966 teq r3, r9 @ cache ID register present?
971 mov r2, r2, lsl r1 @ base dcache size *2
972 tst r3, #1 << 14 @ test M bit
973 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
977 mov r11, r11, lsl r3 @ cache line size in bytes
980 bic r1, r1, #63 @ align to longest cache line
983 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
984 THUMB( ldr r3, [r1] ) @ s/w flush D cache
985 THUMB( add r1, r1, r11 )
989 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
990 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
991 mcr p15, 0, r1, c7, c10, 4 @ drain WB
994 __armv3_mmu_cache_flush:
995 __armv3_mpu_cache_flush:
997 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1001 * Various debugging routines for printing hex characters and
1002 * memory, which again must be relocatable.
1006 .type phexbuf,#object
1008 .size phexbuf, . - phexbuf
1010 phex: adr r3, phexbuf
1025 1: ldrb r2, [r0], #1
1044 memdump: mov r12, r0
1047 2: mov r0, r11, lsl #2
1055 ldr r0, [r12, r11, lsl #2]
1077 .section ".stack", "w"
1078 user_stack: .space 4096