2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
22 #if defined(CONFIG_DEBUG_ICEDCC)
24 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
25 .macro loadsp, rb, tmp
28 mcr p14, 0, \ch, c0, c5, 0
30 #elif defined(CONFIG_CPU_XSCALE)
31 .macro loadsp, rb, tmp
34 mcr p14, 0, \ch, c8, c0, 0
37 .macro loadsp, rb, tmp
40 mcr p14, 0, \ch, c1, c0, 0
46 #include <mach/debug-macro.S>
52 #if defined(CONFIG_ARCH_SA1100)
53 .macro loadsp, rb, tmp
54 mov \rb, #0x80000000 @ physical base address
55 #ifdef CONFIG_DEBUG_LL_SER3
56 add \rb, \rb, #0x00050000 @ Ser3
58 add \rb, \rb, #0x00010000 @ Ser1
61 #elif defined(CONFIG_ARCH_S3C24XX)
62 .macro loadsp, rb, tmp
64 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
67 .macro loadsp, rb, tmp
85 .macro debug_reloc_start
88 kphex r6, 8 /* processor id */
90 kphex r7, 8 /* architecture id */
91 #ifdef CONFIG_CPU_CP15
93 mrc p15, 0, r0, c1, c0
94 kphex r0, 8 /* control reg */
97 kphex r5, 8 /* decompressed kernel start */
99 kphex r9, 8 /* decompressed kernel end */
101 kphex r4, 8 /* kernel execution address */
106 .macro debug_reloc_end
108 kphex r5, 8 /* end of kernel */
111 bl memdump /* dump 256 bytes at start of kernel */
115 .section ".start", #alloc, #execinstr
117 * sort out different calling conventions
120 .arm @ Always enter in ARM state
122 .type start,#function
128 THUMB( adr r12, BSYM(1f) )
131 .word 0x016f2818 @ Magic numbers to help the loader
132 .word start @ absolute load/run zImage address
133 .word _edata @ zImage end address
135 1: mov r7, r1 @ save architecture ID
136 mov r8, r2 @ save atags pointer
138 #ifndef __ARM_ARCH_2__
140 * Booting from Angel - need to enter SVC mode and disable
141 * FIQs/IRQs (numeric definitions from angel arm.h source).
142 * We only do this if we were in user mode on entry.
144 mrs r2, cpsr @ get current mode
145 tst r2, #3 @ not user?
147 mov r0, #0x17 @ angel_SWIreason_EnterSVC
148 ARM( swi 0x123456 ) @ angel_SWI_ARM
149 THUMB( svc 0xab ) @ angel_SWI_THUMB
151 mrs r2, cpsr @ turn off interrupts to
152 orr r2, r2, #0xc0 @ prevent angel from running
155 teqp pc, #0x0c000003 @ turn off interrupts
159 * Note that some cache flushing and other stuff may
160 * be needed here - is there an Angel SWI call for this?
164 * some architecture specific code can be inserted
165 * by the linker here, but it should preserve r7, r8, and r9.
170 #ifdef CONFIG_AUTO_ZRELADDR
171 @ determine final kernel image address
173 and r4, r4, #0xf8000000
174 add r4, r4, #TEXT_OFFSET
182 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
186 * We might be running at a different address. We need
187 * to fix up various pointers.
189 sub r0, r0, r1 @ calculate the delta offset
190 add r6, r6, r0 @ _edata
191 add r10, r10, r0 @ inflated kernel size location
194 * The kernel build system appends the size of the
195 * decompressed kernel at the end of the compressed data
196 * in little-endian form.
200 orr r9, r9, lr, lsl #8
203 orr r9, r9, lr, lsl #16
204 orr r9, r9, r10, lsl #24
206 #ifndef CONFIG_ZBOOT_ROM
207 /* malloc space is above the relocated stack (64k max) */
209 add r10, sp, #0x10000
212 * With ZBOOT_ROM the bss/stack is non relocatable,
213 * but someone could still run this code from RAM,
214 * in which case our reference is _edata.
219 mov r5, #0 @ init dtb size to 0
220 #ifdef CONFIG_ARM_APPENDED_DTB
225 * r4 = final kernel address
226 * r5 = appended dtb size (still unknown)
228 * r7 = architecture ID
229 * r8 = atags/device tree pointer
230 * r9 = size of decompressed image
231 * r10 = end of this image, including bss/stack/malloc space if non XIP
236 * if there are device trees (dtb) appended to zImage, advance r10 so that the
237 * dtb data will get relocated along with the kernel if necessary.
242 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
247 bne dtb_check_done @ not found
249 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
251 * OK... Let's do some funky business here.
252 * If we do have a DTB appended to zImage, and we do have
253 * an ATAG list around, we want the later to be translated
254 * and folded into the former here. To be on the safe side,
255 * let's temporarily move the stack away into the malloc
256 * area. No GOT fixup has occurred yet, but none of the
257 * code we're about to call uses any global variable.
260 stmfd sp!, {r0-r3, ip, lr}
267 * If returned value is 1, there is no ATAG at the location
268 * pointed by r8. Try the typical 0x100 offset from start
269 * of RAM and hope for the best.
272 sub r0, r4, #TEXT_OFFSET
278 ldmfd sp!, {r0-r3, ip, lr}
282 mov r8, r6 @ use the appended device tree
285 * Make sure that the DTB doesn't end up in the final
286 * kernel's .bss area. To do so, we adjust the decompressed
287 * kernel size to compensate if that .bss size is larger
288 * than the relocated code.
290 ldr r5, =_kernel_bss_size
291 adr r1, wont_overwrite
296 /* Get the dtb's size */
299 /* convert r5 (dtb size) to little endian */
300 eor r1, r5, r5, ror #16
301 bic r1, r1, #0x00ff0000
303 eor r5, r5, r1, lsr #8
306 /* preserve 64-bit alignment */
310 /* relocate some pointers past the appended dtb */
318 * Check to see if we will overwrite ourselves.
319 * r4 = final kernel address
320 * r9 = size of decompressed image
321 * r10 = end of this image, including bss/stack/malloc space if non XIP
323 * r4 - 16k page directory >= r10 -> OK
324 * r4 + image length <= address of wont_overwrite -> OK
330 adr r9, wont_overwrite
335 * Relocate ourselves past the end of the decompressed kernel.
337 * r10 = end of the decompressed kernel
338 * Because we always copy ahead, we need to do it from the end and go
339 * backward in case the source and destination overlap.
342 * Bump to the next 256-byte boundary with the size of
343 * the relocation code added. This avoids overwriting
344 * ourself when the offset is small.
346 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
349 /* Get start of code we want to copy and align it down. */
353 sub r9, r6, r5 @ size to copy
354 add r9, r9, #31 @ rounded up to a multiple
355 bic r9, r9, #31 @ ... of 32 bytes
359 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
361 stmdb r9!, {r0 - r3, r10 - r12, lr}
364 /* Preserve offset to relocated code. */
367 #ifndef CONFIG_ZBOOT_ROM
368 /* cache_clean_flush may use the stack, so relocate it */
374 adr r0, BSYM(restart)
380 * If delta is zero, we are running at the address we were linked at.
384 * r4 = kernel execution address
385 * r5 = appended dtb size (0 if not present)
386 * r7 = architecture ID
398 #ifndef CONFIG_ZBOOT_ROM
400 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
401 * we need to fix up pointers into the BSS region.
402 * Note that the stack pointer has already been fixed up.
408 * Relocate all entries in the GOT table.
409 * Bump bss entries to _edata + dtb size
411 1: ldr r1, [r11, #0] @ relocate entries in the GOT
412 add r1, r1, r0 @ This fixes up C references
413 cmp r1, r2 @ if entry >= bss_start &&
414 cmphs r3, r1 @ bss_end > entry
415 addhi r1, r1, r5 @ entry += dtb size
416 str r1, [r11], #4 @ next entry
420 /* bump our bss pointers too */
427 * Relocate entries in the GOT table. We only relocate
428 * the entries that are outside the (relocated) BSS region.
430 1: ldr r1, [r11, #0] @ relocate entries in the GOT
431 cmp r1, r2 @ entry < bss_start ||
432 cmphs r3, r1 @ _end < entry
433 addlo r1, r1, r0 @ table. This fixes up the
434 str r1, [r11], #4 @ C references.
439 not_relocated: mov r0, #0
440 1: str r0, [r2], #4 @ clear bss
448 * The C runtime environment should now be setup sufficiently.
449 * Set up some pointers, and start decompressing.
450 * r4 = kernel execution address
451 * r7 = architecture ID
455 mov r1, sp @ malloc space above stack
456 add r2, sp, #0x10000 @ 64k max
461 mov r0, #0 @ must be zero
462 mov r1, r7 @ restore architecture number
463 mov r2, r8 @ restore atags pointer
464 ARM( mov pc, r4 ) @ call kernel
465 THUMB( bx r4 ) @ entry point is always ARM
470 .word __bss_start @ r2
473 .word input_data_end - 4 @ r10 (inflated size location)
474 .word _got_start @ r11
476 .word .L_user_stack_end @ sp
479 #ifdef CONFIG_ARCH_RPC
481 params: ldr r0, =0x10000100 @ params_phys for RPC
488 * Turn on the cache. We need to setup some page tables so that we
489 * can have both the I and D caches on.
491 * We place the page tables 16k down from the kernel execution address,
492 * and we hope that nothing else is using it. If we're using it, we
496 * r4 = kernel execution address
497 * r7 = architecture number
500 * r0, r1, r2, r3, r9, r10, r12 corrupted
501 * This routine must preserve:
505 cache_on: mov r3, #8 @ cache_on function
509 * Initialize the highest priority protection region, PR7
510 * to cover all 32bit address and cacheable and bufferable.
512 __armv4_mpu_cache_on:
513 mov r0, #0x3f @ 4G, the whole
514 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
515 mcr p15, 0, r0, c6, c7, 1
518 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
519 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
520 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
523 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
524 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
527 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
528 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
529 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
530 mrc p15, 0, r0, c1, c0, 0 @ read control reg
531 @ ...I .... ..D. WC.M
532 orr r0, r0, #0x002d @ .... .... ..1. 11.1
533 orr r0, r0, #0x1000 @ ...1 .... .... ....
535 mcr p15, 0, r0, c1, c0, 0 @ write control reg
538 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
539 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
542 __armv3_mpu_cache_on:
543 mov r0, #0x3f @ 4G, the whole
544 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
547 mcr p15, 0, r0, c2, c0, 0 @ cache on
548 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
551 mcr p15, 0, r0, c5, c0, 0 @ access permission
554 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
556 * ?? ARMv3 MMU does not allow reading the control register,
557 * does this really work on ARMv3 MPU?
559 mrc p15, 0, r0, c1, c0, 0 @ read control reg
560 @ .... .... .... WC.M
561 orr r0, r0, #0x000d @ .... .... .... 11.1
562 /* ?? this overwrites the value constructed above? */
564 mcr p15, 0, r0, c1, c0, 0 @ write control reg
566 /* ?? invalidate for the second time? */
567 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
570 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
576 __setup_mmu: sub r3, r4, #16384 @ Page directory size
577 bic r3, r3, #0xff @ Align the pointer
580 * Initialise the page tables, turning on the cacheable and bufferable
581 * bits for the RAM area only.
585 mov r9, r9, lsl #18 @ start of RAM
586 add r10, r9, #0x10000000 @ a reasonable RAM size
587 mov r1, #0x12 @ XN|U + section mapping
588 orr r1, r1, #3 << 10 @ AP=11
590 1: cmp r1, r9 @ if virt > start of RAM
591 cmphs r10, r1 @ && end of RAM > virt
592 bic r1, r1, #0x1c @ clear XN|U + C + B
593 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
594 orrhs r1, r1, r6 @ set RAM section settings
595 str r1, [r0], #4 @ 1:1 mapping
600 * If ever we are running from Flash, then we surely want the cache
601 * to be enabled also for our execution instance... We map 2MB of it
602 * so there is no map overlap problem for up to 1 MB compressed kernel.
603 * If the execution is in RAM then we would only be duplicating the above.
605 orr r1, r6, #0x04 @ ensure B is set for this
609 orr r1, r1, r2, lsl #20
610 add r0, r3, r2, lsl #2
617 __arm926ejs_mmu_cache_on:
618 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
619 mov r0, #4 @ put dcache in WT mode
620 mcr p15, 7, r0, c15, c0, 0
623 __armv4_mmu_cache_on:
626 mov r6, #CB_BITS | 0x12 @ U
629 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
630 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
631 mrc p15, 0, r0, c1, c0, 0 @ read control reg
632 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
634 #ifdef CONFIG_CPU_ENDIAN_BE8
635 orr r0, r0, #1 << 25 @ big-endian page tables
637 bl __common_mmu_cache_on
639 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
643 __armv7_mmu_cache_on:
646 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
648 movne r6, #CB_BITS | 0x02 @ !XN
651 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
653 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
655 mrc p15, 0, r0, c1, c0, 0 @ read control reg
656 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
657 orr r0, r0, #0x003c @ write buffer
659 #ifdef CONFIG_CPU_ENDIAN_BE8
660 orr r0, r0, #1 << 25 @ big-endian page tables
662 orrne r0, r0, #1 @ MMU enabled
663 movne r1, #0xfffffffd @ domain 0 = client
664 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
665 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
667 mcr p15, 0, r0, c7, c5, 4 @ ISB
668 mcr p15, 0, r0, c1, c0, 0 @ load control register
669 mrc p15, 0, r0, c1, c0, 0 @ and read it back
671 mcr p15, 0, r0, c7, c5, 4 @ ISB
676 mov r6, #CB_BITS | 0x12 @ U
679 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
680 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
681 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
682 mrc p15, 0, r0, c1, c0, 0 @ read control reg
683 orr r0, r0, #0x1000 @ I-cache enable
684 bl __common_mmu_cache_on
686 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
689 __common_mmu_cache_on:
690 #ifndef CONFIG_THUMB2_KERNEL
692 orr r0, r0, #0x000d @ Write buffer, mmu
695 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
696 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
698 .align 5 @ cache line aligned
699 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
700 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
701 sub pc, lr, r0, lsr #32 @ properly flush pipeline
704 #define PROC_ENTRY_SIZE (4*5)
707 * Here follow the relocatable cache support functions for the
708 * various processors. This is a generic hook for locating an
709 * entry and jumping to an instruction at the specified offset
710 * from the start of the block. Please note this is all position
720 call_cache_fn: adr r12, proc_types
721 #ifdef CONFIG_CPU_CP15
722 mrc p15, 0, r9, c0, c0 @ get processor ID
724 ldr r9, =CONFIG_PROCESSOR_ID
726 1: ldr r1, [r12, #0] @ get value
727 ldr r2, [r12, #4] @ get mask
728 eor r1, r1, r9 @ (real ^ match)
730 ARM( addeq pc, r12, r3 ) @ call cache function
731 THUMB( addeq r12, r3 )
732 THUMB( moveq pc, r12 ) @ call cache function
733 add r12, r12, #PROC_ENTRY_SIZE
737 * Table for cache operations. This is basically:
740 * - 'cache on' method instruction
741 * - 'cache off' method instruction
742 * - 'cache flush' method instruction
744 * We match an entry using: ((real_id ^ match) & mask) == 0
746 * Writethrough caches generally only need 'on' and 'off'
747 * methods. Writeback caches _must_ have the flush method
751 .type proc_types,#object
753 .word 0x00000000 @ old ARM ID
762 .word 0x41007000 @ ARM7/710
771 .word 0x41807200 @ ARM720T (writethrough)
773 W(b) __armv4_mmu_cache_on
774 W(b) __armv4_mmu_cache_off
778 .word 0x41007400 @ ARM74x
780 W(b) __armv3_mpu_cache_on
781 W(b) __armv3_mpu_cache_off
782 W(b) __armv3_mpu_cache_flush
784 .word 0x41009400 @ ARM94x
786 W(b) __armv4_mpu_cache_on
787 W(b) __armv4_mpu_cache_off
788 W(b) __armv4_mpu_cache_flush
790 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
792 W(b) __arm926ejs_mmu_cache_on
793 W(b) __armv4_mmu_cache_off
794 W(b) __armv5tej_mmu_cache_flush
796 .word 0x00007000 @ ARM7 IDs
805 @ Everything from here on will be the new ID system.
807 .word 0x4401a100 @ sa110 / sa1100
809 W(b) __armv4_mmu_cache_on
810 W(b) __armv4_mmu_cache_off
811 W(b) __armv4_mmu_cache_flush
813 .word 0x6901b110 @ sa1110
815 W(b) __armv4_mmu_cache_on
816 W(b) __armv4_mmu_cache_off
817 W(b) __armv4_mmu_cache_flush
820 .word 0xffffff00 @ PXA9xx
821 W(b) __armv4_mmu_cache_on
822 W(b) __armv4_mmu_cache_off
823 W(b) __armv4_mmu_cache_flush
825 .word 0x56158000 @ PXA168
827 W(b) __armv4_mmu_cache_on
828 W(b) __armv4_mmu_cache_off
829 W(b) __armv5tej_mmu_cache_flush
831 .word 0x56050000 @ Feroceon
833 W(b) __armv4_mmu_cache_on
834 W(b) __armv4_mmu_cache_off
835 W(b) __armv5tej_mmu_cache_flush
837 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
838 /* this conflicts with the standard ARMv5TE entry */
839 .long 0x41009260 @ Old Feroceon
841 b __armv4_mmu_cache_on
842 b __armv4_mmu_cache_off
843 b __armv5tej_mmu_cache_flush
846 .word 0x66015261 @ FA526
848 W(b) __fa526_cache_on
849 W(b) __armv4_mmu_cache_off
850 W(b) __fa526_cache_flush
852 @ These match on the architecture ID
854 .word 0x00020000 @ ARMv4T
856 W(b) __armv4_mmu_cache_on
857 W(b) __armv4_mmu_cache_off
858 W(b) __armv4_mmu_cache_flush
860 .word 0x00050000 @ ARMv5TE
862 W(b) __armv4_mmu_cache_on
863 W(b) __armv4_mmu_cache_off
864 W(b) __armv4_mmu_cache_flush
866 .word 0x00060000 @ ARMv5TEJ
868 W(b) __armv4_mmu_cache_on
869 W(b) __armv4_mmu_cache_off
870 W(b) __armv5tej_mmu_cache_flush
872 .word 0x0007b000 @ ARMv6
874 W(b) __armv4_mmu_cache_on
875 W(b) __armv4_mmu_cache_off
876 W(b) __armv6_mmu_cache_flush
878 .word 0x000f0000 @ new CPU Id
880 W(b) __armv7_mmu_cache_on
881 W(b) __armv7_mmu_cache_off
882 W(b) __armv7_mmu_cache_flush
884 .word 0 @ unrecognised type
893 .size proc_types, . - proc_types
896 * If you get a "non-constant expression in ".if" statement"
897 * error from the assembler on this line, check that you have
898 * not accidentally written a "b" instruction where you should
901 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
902 .error "The size of one or more proc_types entries is wrong."
906 * Turn off the Cache and MMU. ARMv3 does not support
907 * reading the control register, but ARMv4 does.
910 * r0, r1, r2, r3, r9, r12 corrupted
911 * This routine must preserve:
915 cache_off: mov r3, #12 @ cache_off function
918 __armv4_mpu_cache_off:
919 mrc p15, 0, r0, c1, c0
921 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
923 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
924 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
925 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
928 __armv3_mpu_cache_off:
929 mrc p15, 0, r0, c1, c0
931 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
933 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
936 __armv4_mmu_cache_off:
938 mrc p15, 0, r0, c1, c0
940 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
942 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
943 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
947 __armv7_mmu_cache_off:
948 mrc p15, 0, r0, c1, c0
954 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
956 bl __armv7_mmu_cache_flush
959 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
961 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
962 mcr p15, 0, r0, c7, c10, 4 @ DSB
963 mcr p15, 0, r0, c7, c5, 4 @ ISB
967 * Clean and flush the cache to maintain consistency.
970 * r1, r2, r3, r9, r10, r11, r12 corrupted
971 * This routine must preserve:
979 __armv4_mpu_cache_flush:
982 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
983 mov r1, #7 << 5 @ 8 segments
984 1: orr r3, r1, #63 << 26 @ 64 entries
985 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
986 subs r3, r3, #1 << 26
987 bcs 2b @ entries 63 to 0
989 bcs 1b @ segments 7 to 0
992 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
993 mcr p15, 0, ip, c7, c10, 4 @ drain WB
998 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
999 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1000 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1003 __armv6_mmu_cache_flush:
1005 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1006 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1007 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1008 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1011 __armv7_mmu_cache_flush:
1012 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1013 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1016 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1019 mcr p15, 0, r10, c7, c10, 5 @ DMB
1020 stmfd sp!, {r0-r7, r9-r11}
1021 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1022 ands r3, r0, #0x7000000 @ extract loc from clidr
1023 mov r3, r3, lsr #23 @ left align loc bit field
1024 beq finished @ if loc is 0, then no need to clean
1025 mov r10, #0 @ start clean at cache level 0
1027 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1028 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1029 and r1, r1, #7 @ mask of the bits for current cache only
1030 cmp r1, #2 @ see what cache we have at this level
1031 blt skip @ skip if no cache, or just i-cache
1032 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1033 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1034 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1035 and r2, r1, #7 @ extract the length of the cache lines
1036 add r2, r2, #4 @ add 4 (line length offset)
1038 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1039 clz r5, r4 @ find bit position of way size increment
1041 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1043 mov r9, r4 @ create working copy of max way size
1045 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1046 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1047 THUMB( lsl r6, r9, r5 )
1048 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1049 THUMB( lsl r6, r7, r2 )
1050 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1051 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1052 subs r9, r9, #1 @ decrement the way
1054 subs r7, r7, #1 @ decrement the index
1057 add r10, r10, #2 @ increment cache number
1061 ldmfd sp!, {r0-r7, r9-r11}
1062 mov r10, #0 @ swith back to cache level 0
1063 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1065 mcr p15, 0, r10, c7, c10, 4 @ DSB
1066 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1067 mcr p15, 0, r10, c7, c10, 4 @ DSB
1068 mcr p15, 0, r10, c7, c5, 4 @ ISB
1071 __armv5tej_mmu_cache_flush:
1072 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1074 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1075 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1078 __armv4_mmu_cache_flush:
1079 mov r2, #64*1024 @ default: 32K dcache size (*2)
1080 mov r11, #32 @ default: 32 byte line size
1081 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1082 teq r3, r9 @ cache ID register present?
1087 mov r2, r2, lsl r1 @ base dcache size *2
1088 tst r3, #1 << 14 @ test M bit
1089 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1093 mov r11, r11, lsl r3 @ cache line size in bytes
1096 bic r1, r1, #63 @ align to longest cache line
1099 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1100 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1101 THUMB( add r1, r1, r11 )
1105 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1106 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1107 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1110 __armv3_mmu_cache_flush:
1111 __armv3_mpu_cache_flush:
1113 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1117 * Various debugging routines for printing hex characters and
1118 * memory, which again must be relocatable.
1122 .type phexbuf,#object
1124 .size phexbuf, . - phexbuf
1126 @ phex corrupts {r0, r1, r2, r3}
1127 phex: adr r3, phexbuf
1141 @ puts corrupts {r0, r1, r2, r3}
1143 1: ldrb r2, [r0], #1
1156 @ putc corrupts {r0, r1, r2, r3}
1163 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1164 memdump: mov r12, r0
1167 2: mov r0, r11, lsl #2
1175 ldr r0, [r12, r11, lsl #2]
1197 .section ".stack", "aw", %nobits
1198 .L_user_stack: .space 4096