4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Kuninori Morimoto
6 * Copyright (C) 2010 Simon Horman
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 * Parts inspired by u-boot
16 #include <linux/mmc/host.h>
17 #include <linux/mmc/core.h>
18 #include <linux/mmc/mmc.h>
19 #include <linux/mmc/sd.h>
20 #include <linux/mmc/tmio.h>
21 #include <mach/sdhi.h>
23 #define OCR_FASTBOOT (1<<29)
24 #define OCR_HCS (1<<30)
25 #define OCR_BUSY (1<<31)
27 #define RESP_CMD12 0x00000030
29 static inline u16 sd_ctrl_read16(void __iomem *base, int addr)
31 return __raw_readw(base + addr);
34 static inline u32 sd_ctrl_read32(void __iomem *base, int addr)
36 return __raw_readw(base + addr) |
37 __raw_readw(base + addr + 2) << 16;
40 static inline void sd_ctrl_write16(void __iomem *base, int addr, u16 val)
42 __raw_writew(val, base + addr);
45 static inline void sd_ctrl_write32(void __iomem *base, int addr, u32 val)
47 __raw_writew(val, base + addr);
48 __raw_writew(val >> 16, base + addr + 2);
51 #define ALL_ERROR (TMIO_STAT_CMD_IDX_ERR | TMIO_STAT_CRCFAIL | \
52 TMIO_STAT_STOPBIT_ERR | TMIO_STAT_DATATIMEOUT | \
53 TMIO_STAT_RXOVERFLOW | TMIO_STAT_TXUNDERRUN | \
54 TMIO_STAT_CMDTIMEOUT | TMIO_STAT_ILL_ACCESS | \
57 static int sdhi_intr(void __iomem *base)
59 unsigned long state = sd_ctrl_read32(base, CTL_STATUS);
61 if (state & ALL_ERROR) {
62 sd_ctrl_write32(base, CTL_STATUS, ~ALL_ERROR);
63 sd_ctrl_write32(base, CTL_IRQ_MASK,
65 sd_ctrl_read32(base, CTL_IRQ_MASK));
68 if (state & TMIO_STAT_CMDRESPEND) {
69 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
70 sd_ctrl_write32(base, CTL_IRQ_MASK,
71 TMIO_STAT_CMDRESPEND |
72 sd_ctrl_read32(base, CTL_IRQ_MASK));
75 if (state & TMIO_STAT_RXRDY) {
76 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_RXRDY);
77 sd_ctrl_write32(base, CTL_IRQ_MASK,
78 TMIO_STAT_RXRDY | TMIO_STAT_TXUNDERRUN |
79 sd_ctrl_read32(base, CTL_IRQ_MASK));
82 if (state & TMIO_STAT_DATAEND) {
83 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_DATAEND);
84 sd_ctrl_write32(base, CTL_IRQ_MASK,
86 sd_ctrl_read32(base, CTL_IRQ_MASK));
93 static int sdhi_boot_wait_resp_end(void __iomem *base)
95 int err = -EAGAIN, timeout = 10000000;
98 err = sdhi_intr(base);
108 #define CLK_MMC_ENABLE (1 << 8)
109 #define CLK_MMC_INIT (1 << 6) /* clk / 256 */
111 static void sdhi_boot_mmc_clk_stop(void __iomem *base)
113 sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, 0x0000);
115 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, ~CLK_MMC_ENABLE &
116 sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
120 static void sdhi_boot_mmc_clk_start(void __iomem *base)
122 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, CLK_MMC_ENABLE |
123 sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
125 sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, CLK_MMC_ENABLE);
129 static void sdhi_boot_reset(void __iomem *base)
131 sd_ctrl_write16(base, CTL_RESET_SD, 0x0000);
133 sd_ctrl_write16(base, CTL_RESET_SD, 0x0001);
137 /* Set MMC clock / power.
138 * Note: This controller uses a simple divider scheme therefore it cannot
139 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
140 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
143 static int sdhi_boot_mmc_set_ios(void __iomem *base, struct mmc_ios *ios)
145 if (sd_ctrl_read32(base, CTL_STATUS) & TMIO_STAT_CMD_BUSY)
149 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL,
150 ios->clock | CLK_MMC_ENABLE);
152 /* Power sequence - OFF -> ON -> UP */
153 switch (ios->power_mode) {
154 case MMC_POWER_OFF: /* power down SD bus */
155 sdhi_boot_mmc_clk_stop(base);
157 case MMC_POWER_ON: /* power up SD bus */
159 case MMC_POWER_UP: /* start bus clock */
160 sdhi_boot_mmc_clk_start(base);
164 switch (ios->bus_width) {
165 case MMC_BUS_WIDTH_1:
166 sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x80e0);
168 case MMC_BUS_WIDTH_4:
169 sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x00e0);
173 /* Let things settle. delay taken from winCE driver */
179 /* These are the bitmasks the tmio chip requires to implement the MMC response
180 * types. Note that R1 and R6 are the same in this scheme. */
181 #define RESP_NONE 0x0300
182 #define RESP_R1 0x0400
183 #define RESP_R1B 0x0500
184 #define RESP_R2 0x0600
185 #define RESP_R3 0x0700
186 #define DATA_PRESENT 0x0800
187 #define TRANSFER_READ 0x1000
189 static int sdhi_boot_request(void __iomem *base, struct mmc_command *cmd)
191 int err, c = cmd->opcode;
193 switch (mmc_resp_type(cmd)) {
194 case MMC_RSP_NONE: c |= RESP_NONE; break;
195 case MMC_RSP_R1: c |= RESP_R1; break;
196 case MMC_RSP_R1B: c |= RESP_R1B; break;
197 case MMC_RSP_R2: c |= RESP_R2; break;
198 case MMC_RSP_R3: c |= RESP_R3; break;
203 /* No interrupts so this may not be cleared */
204 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
206 sd_ctrl_write32(base, CTL_IRQ_MASK, TMIO_STAT_CMDRESPEND |
207 sd_ctrl_read32(base, CTL_IRQ_MASK));
208 sd_ctrl_write32(base, CTL_ARG_REG, cmd->arg);
209 sd_ctrl_write16(base, CTL_SD_CMD, c);
212 sd_ctrl_write32(base, CTL_IRQ_MASK,
213 ~(TMIO_STAT_CMDRESPEND | ALL_ERROR) &
214 sd_ctrl_read32(base, CTL_IRQ_MASK));
216 err = sdhi_boot_wait_resp_end(base);
220 cmd->resp[0] = sd_ctrl_read32(base, CTL_RESPONSE);
225 static int sdhi_boot_do_read_single(void __iomem *base, int high_capacity,
226 unsigned long block, unsigned short *buf)
232 struct mmc_command cmd;
234 cmd.opcode = MMC_READ_SINGLE_BLOCK | \
235 TRANSFER_READ | DATA_PRESENT;
239 cmd.arg = block * TMIO_BBS;
240 cmd.flags = MMC_RSP_R1;
241 err = sdhi_boot_request(base, &cmd);
246 sd_ctrl_write32(base, CTL_IRQ_MASK,
247 ~(TMIO_STAT_DATAEND | TMIO_STAT_RXRDY |
248 TMIO_STAT_TXUNDERRUN) &
249 sd_ctrl_read32(base, CTL_IRQ_MASK));
250 err = sdhi_boot_wait_resp_end(base);
254 sd_ctrl_write16(base, CTL_SD_XFER_LEN, TMIO_BBS);
255 for (i = 0; i < TMIO_BBS / sizeof(*buf); i++)
256 *buf++ = sd_ctrl_read16(base, RESP_CMD12);
258 err = sdhi_boot_wait_resp_end(base);
265 int sdhi_boot_do_read(void __iomem *base, int high_capacity,
266 unsigned long offset, unsigned short count,
272 for (i = 0; i < count; i++) {
273 err = sdhi_boot_do_read_single(base, high_capacity, offset + i,
274 buf + (i * TMIO_BBS /
283 #define VOLTAGES (MMC_VDD_32_33 | MMC_VDD_33_34)
285 int sdhi_boot_init(void __iomem *base)
287 bool sd_v2 = false, sd_v1_0 = false;
289 int err, high_capacity = 0;
291 sdhi_boot_mmc_clk_stop(base);
292 sdhi_boot_reset(base);
294 /* mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 0 timing 0 */
297 ios.power_mode = MMC_POWER_ON;
298 ios.bus_width = MMC_BUS_WIDTH_1;
299 ios.clock = CLK_MMC_INIT;
300 err = sdhi_boot_mmc_set_ios(base, &ios);
307 struct mmc_command cmd;
309 cmd.opcode = MMC_GO_IDLE_STATE;
311 cmd.flags = MMC_RSP_NONE;
312 err = sdhi_boot_request(base, &cmd);
318 /* CMD8 - Test for SD version 2 */
320 struct mmc_command cmd;
321 cmd.opcode = SD_SEND_IF_COND;
322 cmd.arg = (VOLTAGES != 0) << 8 | 0xaa;
323 cmd.flags = MMC_RSP_R1;
324 err = sdhi_boot_request(base, &cmd); /* Ignore error */
325 if ((cmd.resp[0] & 0xff) == 0xaa)
329 /* CMD55 - Get OCR (SD) */
332 struct mmc_command cmd;
337 cmd.opcode = MMC_APP_CMD;
338 cmd.flags = MMC_RSP_R1;
340 err = sdhi_boot_request(base, &cmd);
344 cmd.opcode = SD_APP_OP_COND;
345 cmd.flags = MMC_RSP_R3;
346 cmd.arg = (VOLTAGES & 0xff8000);
349 cmd.arg |= OCR_FASTBOOT;
350 err = sdhi_boot_request(base, &cmd);
355 } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
357 if (!err && timeout) {
360 high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
364 /* CMD1 - Get OCR (MMC) */
365 if (!sd_v2 && !sd_v1_0) {
367 struct mmc_command cmd;
370 cmd.opcode = MMC_SEND_OP_COND;
371 cmd.arg = VOLTAGES | OCR_HCS;
372 cmd.flags = MMC_RSP_R3;
373 err = sdhi_boot_request(base, &cmd);
378 } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
383 high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
388 struct mmc_command cmd;
389 cmd.opcode = MMC_ALL_SEND_CID;
391 cmd.flags = MMC_RSP_R2;
392 err = sdhi_boot_request(base, &cmd);
398 * MMC: Set the relative address
399 * SD: Get the relative address
400 * Also puts the card into the standby state
403 struct mmc_command cmd;
404 cmd.opcode = MMC_SET_RELATIVE_ADDR;
406 cmd.flags = MMC_RSP_R1;
407 err = sdhi_boot_request(base, &cmd);
410 cid = cmd.resp[0] >> 16;
415 struct mmc_command cmd;
416 cmd.opcode = MMC_SEND_CSD;
418 cmd.flags = MMC_RSP_R2;
419 err = sdhi_boot_request(base, &cmd);
424 /* CMD7 - Select the card */
426 struct mmc_command cmd;
427 cmd.opcode = MMC_SELECT_CARD;
428 //cmd.arg = rca << 16;
430 //cmd.flags = MMC_RSP_R1B;
431 cmd.flags = MMC_RSP_R1;
432 err = sdhi_boot_request(base, &cmd);
437 /* CMD16 - Set the block size */
439 struct mmc_command cmd;
440 cmd.opcode = MMC_SET_BLOCKLEN;
442 cmd.flags = MMC_RSP_R1;
443 err = sdhi_boot_request(base, &cmd);
448 return high_capacity;