arch/arm/boot/dts/arm-realview-pb1176.dts

   1 /*
   2  * Copyright 2014 Linaro Ltd
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 /dts-v1/;
  24 #include <dt-bindings/interrupt-controller/irq.h>
  25 #include "skeleton.dtsi"
  26
  27 / {
  28         model = "ARM RealView PB1176";
  29         compatible = "arm,realview-pb1176";
  30
  31         chosen { };
  32
  33         aliases {
  34                 serial0 = &pb1176_serial0;
  35                 serial1 = &pb1176_serial1;
  36                 serial2 = &pb1176_serial2;
  37                 serial3 = &pb1176_serial3;
  38                 serial4 = &fpga_serial;
  39         };
  40
  41         memory {
  42                 /* 128 MiB memory @ 0x0 */
  43                 reg = <0x00000000 0x08000000>;
  44         };
  45
  46         xtal24mhz: xtal24mhz@24M {
  47                 #clock-cells = <0>;
  48                 compatible = "fixed-clock";
  49                 clock-frequency = <24000000>;
  50         };
  51
  52         timclk: timclk@1M {
  53                 #clock-cells = <0>;
  54                 compatible = "fixed-factor-clock";
  55                 clock-div = <24>;
  56                 clock-mult = <1>;
  57                 clocks = <&xtal24mhz>;
  58         };
  59
  60         sspclk: sspclk@24M {
  61                 #clock-cells = <0>;
  62                 compatible = "fixed-factor-clock";
  63                 clock-div = <1>;
  64                 clock-mult = <1>;
  65                 clocks = <&xtal24mhz>;
  66         };
  67
  68         uartclk: uartclk@24M {
  69                 #clock-cells = <0>;
  70                 compatible = "fixed-factor-clock";
  71                 clock-div = <1>;
  72                 clock-mult = <1>;
  73                 clocks = <&xtal24mhz>;
  74         };
  75
  76         /* FIXME: this actually hangs off the PLL clocks */
  77         pclk: pclk@0 {
  78                 #clock-cells = <0>;
  79                 compatible = "fixed-clock";
  80                 clock-frequency = <0>;
  81         };
  82
  83         soc {
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 compatible = "arm,realview-pb1176-soc", "simple-bus";
  87                 regmap = <&syscon>;
  88                 ranges;
  89
  90                 syscon: syscon@10000000 {
  91                         compatible = "arm,realview-pb1176-syscon", "syscon";
  92                         reg = <0x10000000 0x1000>;
  93
  94                         led@08.0 {
  95                                 compatible = "register-bit-led";
  96                                 offset = <0x08>;
  97                                 mask = <0x01>;
  98                                 label = "versatile:0";
  99                                 linux,default-trigger = "heartbeat";
 100                                 default-state = "on";
 101                         };
 102                         led@08.1 {
 103                                 compatible = "register-bit-led";
 104                                 offset = <0x08>;
 105                                 mask = <0x02>;
 106                                 label = "versatile:1";
 107                                 linux,default-trigger = "mmc0";
 108                                 default-state = "off";
 109                         };
 110                         led@08.2 {
 111                                 compatible = "register-bit-led";
 112                                 offset = <0x08>;
 113                                 mask = <0x04>;
 114                                 label = "versatile:2";
 115                                 linux,default-trigger = "cpu0";
 116                                 default-state = "off";
 117                         };
 118                         led@08.3 {
 119                                 compatible = "register-bit-led";
 120                                 offset = <0x08>;
 121                                 mask = <0x08>;
 122                                 label = "versatile:3";
 123                                 default-state = "off";
 124                         };
 125                         led@08.4 {
 126                                 compatible = "register-bit-led";
 127                                 offset = <0x08>;
 128                                 mask = <0x10>;
 129                                 label = "versatile:4";
 130                                 default-state = "off";
 131                         };
 132                         led@08.5 {
 133                                 compatible = "register-bit-led";
 134                                 offset = <0x08>;
 135                                 mask = <0x20>;
 136                                 label = "versatile:5";
 137                                 default-state = "off";
 138                         };
 139                         led@08.6 {
 140                                 compatible = "register-bit-led";
 141                                 offset = <0x08>;
 142                                 mask = <0x40>;
 143                                 label = "versatile:6";
 144                                 default-state = "off";
 145                         };
 146                         led@08.7 {
 147                                 compatible = "register-bit-led";
 148                                 offset = <0x08>;
 149                                 mask = <0x80>;
 150                                 label = "versatile:7";
 151                                 default-state = "off";
 152                         };
 153                 };
 154
 155                 /* Primary DevChip GIC synthesized with the CPU */
 156                 intc_dc1176: interrupt-controller@10120000 {
 157                         compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
 158                         #interrupt-cells = <3>;
 159                         #address-cells = <1>;
 160                         interrupt-controller;
 161                         reg = <0x10121000 0x1000>,
 162                               <0x10120000 0x100>;
 163                 };
 164
 165                 L2: l2-cache {
 166                         compatible = "arm,l220-cache";
 167                         reg = <0x10110000 0x1000>;
 168                         interrupt-parent = <&intc_dc1176>;
 169                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 170                         cache-unified;
 171                         cache-level = <2>;
 172                         /*
 173                          * Override default cache size, sets and
 174                          * associativity as these may be erroneously set
 175                          * up by boot loader(s).
 176                          */
 177                         arm,override-auxreg;
 178                         cache-size = <131072>; // 128kB
 179                         cache-sets = <512>;
 180                         cache-line-size = <32>;
 181                 };
 182
 183                 pmu {
 184                         compatible = "arm,arm1176-pmu";
 185                         interrupt-parent = <&intc_dc1176>;
 186                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 187                 };
 188
 189                 timer01: timer@10104000 {
 190                         compatible = "arm,sp804", "arm,primecell";
 191                         reg = <0x10104000 0x1000>;
 192                         interrupt-parent = <&intc_dc1176>;
 193                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
 194                         clocks = <&timclk>, <&timclk>, <&pclk>;
 195                         clock-names = "timer1", "timer2", "apb_pclk";
 196                 };
 197
 198                 timer23: timer@10105000 {
 199                         compatible = "arm,sp804", "arm,primecell";
 200                         reg = <0x10105000 0x1000>;
 201                         interrupt-parent = <&intc_dc1176>;
 202                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 203                         arm,sp804-has-irq = <1>;
 204                         clocks = <&timclk>, <&timclk>, <&pclk>;
 205                         clock-names = "timer1", "timer2", "apb_pclk";
 206                 };
 207
 208                 pb1176_rtc: rtc@10108000 {
 209                         compatible = "arm,pl031", "arm,primecell";
 210                         reg = <0x10108000 0x1000>;
 211                         interrupt-parent = <&intc_dc1176>;
 212                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 213                         clocks = <&pclk>;
 214                         clock-names = "apb_pclk";
 215                 };
 216
 217                 pb1176_gpio0: gpio@1010a000 {
 218                         compatible = "arm,pl061", "arm,primecell";
 219                         reg = <0x1010a000 0x1000>;
 220                         gpio-controller;
 221                         interrupt-parent = <&intc_dc1176>;
 222                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 223                         #gpio-cells = <2>;
 224                         interrupt-controller;
 225                         #interrupt-cells = <2>;
 226                         clocks = <&pclk>;
 227                         clock-names = "apb_pclk";
 228                 };
 229
 230                 pb1176_ssp: ssp@1010b000 {
 231                         compatible = "arm,pl022", "arm,primecell";
 232                         reg = <0x1010b000 0x1000>;
 233                         interrupt-parent = <&intc_dc1176>;
 234                         interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
 235                         clocks = <&sspclk>, <&pclk>;
 236                         clock-names = "SSPCLK", "apb_pclk";
 237                 };
 238
 239                 pb1176_serial0: serial@1010c000 {
 240                         compatible = "arm,pl011", "arm,primecell";
 241                         reg = <0x1010c000 0x1000>;
 242                         interrupt-parent = <&intc_dc1176>;
 243                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 244                         clocks = <&uartclk>, <&pclk>;
 245                         clock-names = "uartclk", "apb_pclk";
 246                 };
 247
 248                 pb1176_serial1: serial@1010d000 {
 249                         compatible = "arm,pl011", "arm,primecell";
 250                         reg = <0x1010d000 0x1000>;
 251                         interrupt-parent = <&intc_dc1176>;
 252                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&uartclk>, <&pclk>;
 254                         clock-names = "uartclk", "apb_pclk";
 255                 };
 256
 257                 pb1176_serial2: serial@1010e000 {
 258                         compatible = "arm,pl011", "arm,primecell";
 259                         reg = <0x1010e000 0x1000>;
 260                         interrupt-parent = <&intc_dc1176>;
 261                         interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 262                         clocks = <&uartclk>, <&pclk>;
 263                         clock-names = "uartclk", "apb_pclk";
 264                 };
 265
 266                 pb1176_serial3: serial@1010f000 {
 267                         compatible = "arm,pl011", "arm,primecell";
 268                         reg = <0x1010f000 0x1000>;
 269                         interrupt-parent = <&intc_dc1176>;
 270                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 271                         clocks = <&uartclk>, <&pclk>;
 272                         clock-names = "uartclk", "apb_pclk";
 273                 };
 274         };
 275
 276         /* These peripherals are inside the FPGA rather than the DevChip */
 277         fpga {
 278                 #address-cells = <1>;
 279                 #size-cells = <1>;
 280                 compatible = "simple-bus";
 281                 ranges;
 282
 283                 fpga_charlcd: charlcd@10008000 {
 284                         compatible = "arm,versatile-lcd";
 285                         reg = <0x10008000 0x1000>;
 286                         interrupt-parent = <&intc_fpga1176>;
 287                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&pclk>;
 289                         clock-names = "apb_pclk";
 290                 };
 291
 292                 fpga_serial: serial@10009000 {
 293                         compatible = "arm,pl011", "arm,primecell";
 294                         reg = <0x10009000 0x1000>;
 295                         interrupt-parent = <&intc_fpga1176>;
 296                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 297                         clocks = <&uartclk>, <&pclk>;
 298                         clock-names = "uartclk", "apb_pclk";
 299                 };
 300
 301                 /* This GIC on the board is cascaded off the DevChip GIC */
 302                 intc_fpga1176: interrupt-controller@10040000 {
 303                         compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
 304                         #interrupt-cells = <3>;
 305                         #address-cells = <1>;
 306                         interrupt-controller;
 307                         reg = <0x10041000 0x1000>,
 308                               <0x10040000 0x100>;
 309                         interrupt-parent = <&intc_dc1176>;
 310                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 311                 };
 312
 313                 fpga_gpio0: gpio@10014000 {
 314                         compatible = "arm,pl061", "arm,primecell";
 315                         reg = <0x10014000 0x1000>;
 316                         gpio-controller;
 317                         interrupt-parent = <&intc_fpga1176>;
 318                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 319                         #gpio-cells = <2>;
 320                         interrupt-controller;
 321                         #interrupt-cells = <2>;
 322                         clocks = <&pclk>;
 323                         clock-names = "apb_pclk";
 324                 };
 325
 326                 fpga_gpio1: gpio@10015000 {
 327                         compatible = "arm,pl061", "arm,primecell";
 328                         reg = <0x10015000 0x1000>;
 329                         gpio-controller;
 330                         interrupt-parent = <&intc_fpga1176>;
 331                         interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 332                         #gpio-cells = <2>;
 333                         interrupt-controller;
 334                         #interrupt-cells = <2>;
 335                         clocks = <&pclk>;
 336                         clock-names = "apb_pclk";
 337                 };
 338
 339                 fpga_rtc: rtc@10017000 {
 340                         compatible = "arm,pl031", "arm,primecell";
 341                         reg = <0x10017000 0x1000>;
 342                         interrupt-parent = <&intc_fpga1176>;
 343                         interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 344                         clocks = <&pclk>;
 345                         clock-names = "apb_pclk";
 346                 };
 347
 348
 349         };
 350 };