2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
19 /include/ "skeleton.dtsi"
22 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada-370-xp";
27 compatible = "marvell,sheeva-v7";
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
38 coherency-fabric@d0020200 {
39 compatible = "marvell,coherency-fabric";
40 reg = <0xd0020200 0xb0>,
47 compatible = "simple-bus";
48 interrupt-parent = <&mpic>;
52 compatible = "snps,dw-apb-uart";
53 reg = <0xd0012000 0x100>;
60 compatible = "snps,dw-apb-uart";
61 reg = <0xd0012100 0x100>;
69 compatible = "marvell,armada-370-xp-timer";
70 reg = <0xd0020300 0x30>,
72 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
73 clocks = <&coreclk 2>;
76 addr-decoding@d0020000 {
77 compatible = "marvell,armada-addr-decoding-controller";
78 reg = <0xd0020000 0x258>;
82 compatible = "marvell,orion-sata";
83 reg = <0xd00a0000 0x2400>;
85 clocks = <&gateclk 15>, <&gateclk 30>;
86 clock-names = "0", "1";
93 compatible = "marvell,orion-mdio";
94 reg = <0xd0072004 0x4>;
98 compatible = "marvell,armada-370-neta";
99 reg = <0xd0070000 0x2500>;
101 clocks = <&gateclk 4>;
106 compatible = "marvell,armada-370-neta";
107 reg = <0xd0074000 0x2500>;
109 clocks = <&gateclk 3>;
114 compatible = "marvell,mv64xxx-i2c";
115 reg = <0xd0011000 0x20>;
116 #address-cells = <1>;
120 clocks = <&coreclk 0>;
125 compatible = "marvell,mv64xxx-i2c";
126 reg = <0xd0011100 0x20>;
127 #address-cells = <1>;
131 clocks = <&coreclk 0>;
136 compatible = "marvell,orion-rtc";
137 reg = <0xd0010300 0x20>;
142 compatible = "marvell,orion-sdio";
143 reg = <0xd00d4000 0x200>;
145 clocks = <&gateclk 17>;
150 compatible = "marvell,orion-ehci";
151 reg = <0xd0050000 0x500>;
157 compatible = "marvell,orion-ehci";
158 reg = <0xd0051000 0x500>;
164 compatible = "marvell,orion-spi";
165 reg = <0xd0010600 0x28>;
166 #address-cells = <1>;
170 clocks = <&coreclk 0>;
175 compatible = "marvell,orion-spi";
176 reg = <0xd0010680 0x28>;
177 #address-cells = <1>;
181 clocks = <&coreclk 0>;
185 devbus-bootcs@d0010400 {
186 compatible = "marvell,mvebu-devbus";
187 reg = <0xd0010400 0x8>;
188 #address-cells = <1>;
190 clocks = <&coreclk 0>;
194 devbus-cs0@d0010408 {
195 compatible = "marvell,mvebu-devbus";
196 reg = <0xd0010408 0x8>;
197 #address-cells = <1>;
199 clocks = <&coreclk 0>;
203 devbus-cs1@d0010410 {
204 compatible = "marvell,mvebu-devbus";
205 reg = <0xd0010410 0x8>;
206 #address-cells = <1>;
208 clocks = <&coreclk 0>;
212 devbus-cs2@d0010418 {
213 compatible = "marvell,mvebu-devbus";
214 reg = <0xd0010418 0x8>;
215 #address-cells = <1>;
217 clocks = <&coreclk 0>;
221 devbus-cs3@d0010420 {
222 compatible = "marvell,mvebu-devbus";
223 reg = <0xd0010420 0x8>;
224 #address-cells = <1>;
226 clocks = <&coreclk 0>;