arch/arm/boot/dts/armada-370.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 370 family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  *
  14  * Contains definitions specific to the Armada 370 SoC that are not
  15  * common to all Armada SoCs.
  16  */
  17
  18 /include/ "armada-370-xp.dtsi"
  19
  20 / {
  21         model = "Marvell Armada 370 family SoC";
  22         compatible = "marvell,armada370", "marvell,armada-370-xp";
  23         L2: l2-cache {
  24                 compatible = "marvell,aurora-outer-cache";
  25                 reg = <0xd0008000 0x1000>;
  26                 cache-id-part = <0x100>;
  27                 wt-override;
  28         };
  29
  30         aliases {
  31                 gpio0 = &gpio0;
  32                 gpio1 = &gpio1;
  33                 gpio2 = &gpio2;
  34         };
  35
  36         mpic: interrupt-controller@d0020000 {
  37               reg = <0xd0020a00 0x1d0>,
  38                     <0xd0021870 0x58>;
  39         };
  40
  41         soc {
  42                 system-controller@d0018200 {
  43                                 compatible = "marvell,armada-370-xp-system-controller";
  44                                 reg = <0xd0018200 0x100>;
  45                 };
  46
  47                 pinctrl {
  48                         compatible = "marvell,mv88f6710-pinctrl";
  49                         reg = <0xd0018000 0x38>;
  50                 };
  51
  52                 gpio0: gpio@d0018100 {
  53                         compatible = "marvell,orion-gpio";
  54                         reg = <0xd0018100 0x40>;
  55                         ngpios = <32>;
  56                         gpio-controller;
  57                         #gpio-cells = <2>;
  58                         interrupt-controller;
  59                         #interrupts-cells = <2>;
  60                         interrupts = <82>, <83>, <84>, <85>;
  61                 };
  62
  63                 gpio1: gpio@d0018140 {
  64                         compatible = "marvell,orion-gpio";
  65                         reg = <0xd0018140 0x40>;
  66                         ngpios = <32>;
  67                         gpio-controller;
  68                         #gpio-cells = <2>;
  69                         interrupt-controller;
  70                         #interrupts-cells = <2>;
  71                         interrupts = <87>, <88>, <89>, <90>;
  72                 };
  73
  74                 gpio2: gpio@d0018180 {
  75                         compatible = "marvell,orion-gpio";
  76                         reg = <0xd0018180 0x40>;
  77                         ngpios = <2>;
  78                         gpio-controller;
  79                         #gpio-cells = <2>;
  80                         interrupt-controller;
  81                         #interrupts-cells = <2>;
  82                         interrupts = <91>;
  83                 };
  84
  85                 coreclk: mvebu-sar@d0018230 {
  86                         compatible = "marvell,armada-370-core-clock";
  87                         reg = <0xd0018230 0x08>;
  88                         #clock-cells = <1>;
  89                 };
  90
  91                 gateclk: clock-gating-control@d0018220 {
  92                         compatible = "marvell,armada-370-gating-clock";
  93                         reg = <0xd0018220 0x4>;
  94                         clocks = <&coreclk 0>;
  95                         #clock-cells = <1>;
  96                 };
  97
  98                 xor@d0060800 {
  99                         compatible = "marvell,orion-xor";
 100                         reg = <0xd0060800 0x100
 101                                0xd0060A00 0x100>;
 102                         status = "okay";
 103
 104                         xor00 {
 105                                 interrupts = <51>;
 106                                 dmacap,memcpy;
 107                                 dmacap,xor;
 108                         };
 109                         xor01 {
 110                                 interrupts = <52>;
 111                                 dmacap,memcpy;
 112                                 dmacap,xor;
 113                                 dmacap,memset;
 114                         };
 115                 };
 116
 117                 xor@d0060900 {
 118                         compatible = "marvell,orion-xor";
 119                         reg = <0xd0060900 0x100
 120                                0xd0060b00 0x100>;
 121                         status = "okay";
 122
 123                         xor10 {
 124                                 interrupts = <94>;
 125                                 dmacap,memcpy;
 126                                 dmacap,xor;
 127                         };
 128                         xor11 {
 129                                 interrupts = <95>;
 130                                 dmacap,memcpy;
 131                                 dmacap,xor;
 132                                 dmacap,memset;
 133                         };
 134                 };
 135         };
 136 };