2 * Device Tree Include file for Marvell Armada 370 family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * Contains definitions specific to the Armada 370 SoC that are not
15 * common to all Armada SoCs.
18 #include "armada-370-xp.dtsi"
19 /include/ "skeleton.dtsi"
22 model = "Marvell Armada 370 family SoC";
23 compatible = "marvell,armada370", "marvell,armada-370-xp";
32 compatible = "marvell,armada370-mbus", "simple-bus";
35 compatible = "marvell,bootrom";
36 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
40 compatible = "marvell,armada-370-pcie";
47 bus-range = <0x00 0xff>;
50 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
59 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
60 reg = <0x0800 0 0 0 0>;
63 #interrupt-cells = <1>;
64 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
65 0x81000000 0 0 0x81000000 0x1 0 1 0>;
66 interrupt-map-mask = <0 0 0 0>;
67 interrupt-map = <0 0 0 0 &mpic 58>;
68 marvell,pcie-port = <0>;
69 marvell,pcie-lane = <0>;
70 clocks = <&gateclk 5>;
76 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
77 reg = <0x1000 0 0 0 0>;
80 #interrupt-cells = <1>;
81 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
82 0x81000000 0 0 0x81000000 0x2 0 1 0>;
83 interrupt-map-mask = <0 0 0 0>;
84 interrupt-map = <0 0 0 0 &mpic 62>;
85 marvell,pcie-port = <1>;
86 marvell,pcie-lane = <0>;
87 clocks = <&gateclk 9>;
93 system-controller@18200 {
94 compatible = "marvell,armada-370-xp-system-controller";
95 reg = <0x18200 0x100>;
99 compatible = "marvell,aurora-outer-cache";
100 reg = <0x08000 0x1000>;
101 cache-id-part = <0x100>;
105 interrupt-controller@20000 {
106 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
110 compatible = "marvell,mv88f6710-pinctrl";
111 reg = <0x18000 0x38>;
113 sdio_pins1: sdio-pins1 {
114 marvell,pins = "mpp9", "mpp11", "mpp12",
115 "mpp13", "mpp14", "mpp15";
116 marvell,function = "sd0";
119 sdio_pins2: sdio-pins2 {
120 marvell,pins = "mpp47", "mpp48", "mpp49",
121 "mpp50", "mpp51", "mpp52";
122 marvell,function = "sd0";
125 sdio_pins3: sdio-pins3 {
126 marvell,pins = "mpp48", "mpp49", "mpp50",
127 "mpp51", "mpp52", "mpp53";
128 marvell,function = "sd0";
133 compatible = "marvell,orion-gpio";
134 reg = <0x18100 0x40>;
138 interrupt-controller;
139 #interrupt-cells = <2>;
140 interrupts = <82>, <83>, <84>, <85>;
144 compatible = "marvell,orion-gpio";
145 reg = <0x18140 0x40>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 interrupts = <87>, <88>, <89>, <90>;
155 compatible = "marvell,orion-gpio";
156 reg = <0x18180 0x40>;
160 interrupt-controller;
161 #interrupt-cells = <2>;
166 compatible = "marvell,armada-370-timer";
167 clocks = <&coreclk 2>;
170 coreclk: mvebu-sar@18230 {
171 compatible = "marvell,armada-370-core-clock";
172 reg = <0x18230 0x08>;
176 gateclk: clock-gating-control@18220 {
177 compatible = "marvell,armada-370-gating-clock";
179 clocks = <&coreclk 0>;
184 compatible = "marvell,orion-xor";
203 compatible = "marvell,orion-xor";
222 clocks = <&coreclk 0>;
226 clocks = <&coreclk 0>;
230 compatible = "marvell,armada370-thermal";