2 * Device Tree Include file for Marvell Armada 370 family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * Contains definitions specific to the Armada 370 SoC that are not
15 * common to all Armada SoCs.
18 #include "armada-370-xp.dtsi"
19 /include/ "skeleton.dtsi"
22 model = "Marvell Armada 370 family SoC";
23 compatible = "marvell,armada370", "marvell,armada-370-xp";
32 compatible = "marvell,armada370-mbus", "simple-bus";
35 compatible = "marvell,bootrom";
36 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
40 compatible = "marvell,armada-370-pcie";
48 bus-range = <0x00 0xff>;
51 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
52 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
53 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
54 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
55 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
56 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
60 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
61 reg = <0x0800 0 0 0 0>;
64 #interrupt-cells = <1>;
65 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
66 0x81000000 0 0 0x81000000 0x1 0 1 0>;
67 interrupt-map-mask = <0 0 0 0>;
68 interrupt-map = <0 0 0 0 &mpic 58>;
69 marvell,pcie-port = <0>;
70 marvell,pcie-lane = <0>;
71 clocks = <&gateclk 5>;
77 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
78 reg = <0x1000 0 0 0 0>;
81 #interrupt-cells = <1>;
82 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
83 0x81000000 0 0 0x81000000 0x2 0 1 0>;
84 interrupt-map-mask = <0 0 0 0>;
85 interrupt-map = <0 0 0 0 &mpic 62>;
86 marvell,pcie-port = <1>;
87 marvell,pcie-lane = <0>;
88 clocks = <&gateclk 9>;
95 compatible = "marvell,aurora-outer-cache";
96 reg = <0x08000 0x1000>;
97 cache-id-part = <0x100>;
102 reg = <0x11000 0x20>;
106 reg = <0x11100 0x20>;
109 system-controller@18200 {
110 compatible = "marvell,armada-370-xp-system-controller";
111 reg = <0x18200 0x100>;
115 compatible = "marvell,mv88f6710-pinctrl";
116 reg = <0x18000 0x38>;
118 sdio_pins1: sdio-pins1 {
119 marvell,pins = "mpp9", "mpp11", "mpp12",
120 "mpp13", "mpp14", "mpp15";
121 marvell,function = "sd0";
124 sdio_pins2: sdio-pins2 {
125 marvell,pins = "mpp47", "mpp48", "mpp49",
126 "mpp50", "mpp51", "mpp52";
127 marvell,function = "sd0";
130 sdio_pins3: sdio-pins3 {
131 marvell,pins = "mpp48", "mpp49", "mpp50",
132 "mpp51", "mpp52", "mpp53";
133 marvell,function = "sd0";
138 compatible = "marvell,orion-gpio";
139 reg = <0x18100 0x40>;
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 interrupts = <82>, <83>, <84>, <85>;
149 compatible = "marvell,orion-gpio";
150 reg = <0x18140 0x40>;
154 interrupt-controller;
155 #interrupt-cells = <2>;
156 interrupts = <87>, <88>, <89>, <90>;
160 compatible = "marvell,orion-gpio";
161 reg = <0x18180 0x40>;
165 interrupt-controller;
166 #interrupt-cells = <2>;
170 gateclk: clock-gating-control@18220 {
171 compatible = "marvell,armada-370-gating-clock";
173 clocks = <&coreclk 0>;
177 coreclk: mvebu-sar@18230 {
178 compatible = "marvell,armada-370-core-clock";
179 reg = <0x18230 0x08>;
184 compatible = "marvell,armada370-thermal";
190 interrupt-controller@20000 {
191 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
195 compatible = "marvell,armada-370-timer";
196 clocks = <&coreclk 2>;
200 clocks = <&coreclk 0>;
204 clocks = <&coreclk 0>;
208 compatible = "marvell,orion-xor";
227 compatible = "marvell,orion-xor";