2 * Device Tree file for Marvell Armada XP evaluation board
5 * Copyright (C) 2012-2014 Marvell
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * Note: this Device Tree assumes that the bootloader has remapped the
16 * internal registers to 0xf1000000 (instead of the default
17 * 0xd0000000). The 0xf1000000 is the default used by the recent,
18 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 * boards were delivered with an older version of the bootloader that
20 * left internal registers mapped at 0xd0000000. If you are in this
21 * situation, you should either update your bootloader (preferred
22 * solution) or the below Device Tree should be adjusted.
26 #include "armada-xp-mv78460.dtsi"
29 model = "Marvell Armada XP Evaluation Board";
30 compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
33 bootargs = "console=ttyS0,115200 earlyprintk";
37 device_type = "memory";
38 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
42 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
43 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
44 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
49 /* Device Bus parameters are required */
52 devbus,bus-width = <16>;
53 devbus,turn-off-ps = <60000>;
54 devbus,badr-skew-ps = <0>;
55 devbus,acc-first-ps = <124000>;
56 devbus,acc-next-ps = <248000>;
57 devbus,rd-setup-ps = <0>;
58 devbus,rd-hold-ps = <0>;
60 /* Write parameters */
61 devbus,sync-enable = <0>;
62 devbus,wr-high-ps = <60000>;
63 devbus,wr-low-ps = <60000>;
64 devbus,ale-wr-ps = <60000>;
68 compatible = "cfi-flash";
78 * All 6 slots are physically present as
79 * standard PCIe slots on the board.
109 clock-frequency = <250000000>;
113 clock-frequency = <250000000>;
117 clock-frequency = <250000000>;
121 clock-frequency = <250000000>;
131 phy0: ethernet-phy@0 {
135 phy1: ethernet-phy@1 {
139 phy2: ethernet-phy@2 {
143 phy3: ethernet-phy@3 {
151 phy-mode = "rgmii-id";
156 phy-mode = "rgmii-id";
170 pinctrl-0 = <&sdio_pins>;
171 pinctrl-names = "default";
173 /* No CD or WP GPIOs */
193 #address-cells = <1>;
195 compatible = "m25p64";
196 reg = <0>; /* Chip select 0 */
197 spi-max-frequency = <20000000>;