arch/arm/boot/dts/armada-xp-gp.dts

   1 /*
   2  * Device Tree file for Marvell Armada XP development board
   3  * (DB-MV784MP-GP)
   4  *
   5  * Copyright (C) 2013 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 /dts-v1/;
  17 /include/ "armada-xp-mv78460.dtsi"
  18
  19 / {
  20         model = "Marvell Armada XP Development Board DB-MV784MP-GP";
  21         compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  22
  23         chosen {
  24                 bootargs = "console=ttyS0,115200 earlyprintk";
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29
  30                 /*
  31                  * 4 GB of plug-in RAM modules by default but only 3GB
  32                  * are visible, the amount of memory available can be
  33                  * changed by the bootloader according the size of the
  34                  * module actually plugged
  35                  */
  36                 reg = <0x00000000 0xC0000000>;
  37         };
  38
  39         soc {
  40                 serial@d0012000 {
  41                         clock-frequency = <250000000>;
  42                         status = "okay";
  43                 };
  44                 serial@d0012100 {
  45                         clock-frequency = <250000000>;
  46                         status = "okay";
  47                 };
  48                 serial@d0012200 {
  49                         clock-frequency = <250000000>;
  50                         status = "okay";
  51                 };
  52                 serial@d0012300 {
  53                         clock-frequency = <250000000>;
  54                         status = "okay";
  55                 };
  56
  57                 sata@d00a0000 {
  58                         nr-ports = <2>;
  59                         status = "okay";
  60                 };
  61
  62                 mdio {
  63                         phy0: ethernet-phy@0 {
  64                                 reg = <16>;
  65                         };
  66
  67                         phy1: ethernet-phy@1 {
  68                                 reg = <17>;
  69                         };
  70
  71                         phy2: ethernet-phy@2 {
  72                                 reg = <18>;
  73                         };
  74
  75                         phy3: ethernet-phy@3 {
  76                                 reg = <19>;
  77                         };
  78                 };
  79
  80                 ethernet@d0070000 {
  81                         status = "okay";
  82                         phy = <&phy0>;
  83                         phy-mode = "rgmii-id";
  84                 };
  85                 ethernet@d0074000 {
  86                         status = "okay";
  87                         phy = <&phy1>;
  88                         phy-mode = "rgmii-id";
  89                 };
  90                 ethernet@d0030000 {
  91                         status = "okay";
  92                         phy = <&phy2>;
  93                         phy-mode = "rgmii-id";
  94                 };
  95                 ethernet@d0034000 {
  96                         status = "okay";
  97                         phy = <&phy3>;
  98                         phy-mode = "rgmii-id";
  99                 };
 100
 101                 spi0: spi@d0010600 {
 102                         status = "okay";
 103
 104                         spi-flash@0 {
 105                                 #address-cells = <1>;
 106                                 #size-cells = <1>;
 107                                 compatible = "n25q128a13";
 108                                 reg = <0>; /* Chip select 0 */
 109                                 spi-max-frequency = <108000000>;
 110                         };
 111                 };
 112
 113                 devbus-bootcs@d0010400 {
 114                         status = "okay";
 115                         ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
 116
 117                         /* Device Bus parameters are required */
 118
 119                         /* Read parameters */
 120                         devbus,bus-width    = <8>;
 121                         devbus,turn-off-ps  = <60000>;
 122                         devbus,badr-skew-ps = <0>;
 123                         devbus,acc-first-ps = <124000>;
 124                         devbus,acc-next-ps  = <248000>;
 125                         devbus,rd-setup-ps  = <0>;
 126                         devbus,rd-hold-ps   = <0>;
 127
 128                         /* Write parameters */
 129                         devbus,sync-enable = <0>;
 130                         devbus,wr-high-ps  = <60000>;
 131                         devbus,wr-low-ps   = <60000>;
 132                         devbus,ale-wr-ps   = <60000>;
 133
 134                         /* NOR 16 MiB */
 135                         nor@0 {
 136                                 compatible = "cfi-flash";
 137                                 reg = <0 0x1000000>;
 138                                 bank-width = <2>;
 139                         };
 140                 };
 141
 142                 pcie-controller {
 143                         status = "okay";
 144
 145                         /*
 146                          * The 3 slots are physically present as
 147                          * standard PCIe slots on the board.
 148                          */
 149                         pcie@1,0 {
 150                                 /* Port 0, Lane 0 */
 151                                 status = "okay";
 152                         };
 153                         pcie@9,0 {
 154                                 /* Port 2, Lane 0 */
 155                                 status = "okay";
 156                         };
 157                         pcie@10,0 {
 158                                 /* Port 3, Lane 0 */
 159                                 status = "okay";
 160                         };
 161                 };
 162         };
 163 };