2 * Device Tree file for Marvell Armada XP development board
5 * Copyright (C) 2013 Marvell
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
17 /include/ "armada-xp-mv78460.dtsi"
20 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
21 compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
24 bootargs = "console=ttyS0,115200 earlyprintk";
28 device_type = "memory";
30 * 8 GB of plug-in RAM modules by default.The amount
31 * of memory available can be changed by the
32 * bootloader according the size of the module
33 * actually plugged. Only 7GB are usable because
34 * addresses from 0xC0000000 to 0xffffffff are used by
35 * the internal registers of the SoC.
37 reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
38 <0x00000001 0x00000000 0x00000001 0x00000000>;
44 clock-frequency = <250000000>;
48 clock-frequency = <250000000>;
52 clock-frequency = <250000000>;
56 clock-frequency = <250000000>;
66 phy0: ethernet-phy@0 {
70 phy1: ethernet-phy@1 {
74 phy2: ethernet-phy@2 {
78 phy3: ethernet-phy@3 {
86 phy-mode = "rgmii-id";
91 phy-mode = "rgmii-id";
96 phy-mode = "rgmii-id";
101 phy-mode = "rgmii-id";
108 #address-cells = <1>;
110 compatible = "n25q128a13";
111 reg = <0>; /* Chip select 0 */
112 spi-max-frequency = <108000000>;
116 devbus-bootcs@10400 {
118 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
120 /* Device Bus parameters are required */
122 /* Read parameters */
123 devbus,bus-width = <8>;
124 devbus,turn-off-ps = <60000>;
125 devbus,badr-skew-ps = <0>;
126 devbus,acc-first-ps = <124000>;
127 devbus,acc-next-ps = <248000>;
128 devbus,rd-setup-ps = <0>;
129 devbus,rd-hold-ps = <0>;
131 /* Write parameters */
132 devbus,sync-enable = <0>;
133 devbus,wr-high-ps = <60000>;
134 devbus,wr-low-ps = <60000>;
135 devbus,ale-wr-ps = <60000>;
139 compatible = "cfi-flash";
149 * The 3 slots are physically present as
150 * standard PCIe slots on the board.