2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * Contains definitions specific to the Armada XP MV78230 SoC that are not
13 * common to all Armada XP SoCs.
16 #include "armada-xp.dtsi"
19 model = "Marvell Armada XP MV78230 SoC";
20 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
30 enable-method = "marvell,armada-xp-smp";
34 compatible = "marvell,sheeva-v7";
41 compatible = "marvell,sheeva-v7";
49 * MV78230 has 2 PCIe units Gen2.0: One unit can be
50 * configured as x4 or quad x1 lanes. One unit is
54 compatible = "marvell,armada-xp-pcie";
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
67 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
68 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
69 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
70 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
71 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
72 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
73 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
74 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
75 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
76 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
77 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
78 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
79 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
83 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
84 reg = <0x0800 0 0 0 0>;
87 #interrupt-cells = <1>;
88 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
89 0x81000000 0 0 0x81000000 0x1 0 1 0>;
90 interrupt-map-mask = <0 0 0 0>;
91 interrupt-map = <0 0 0 0 &mpic 58>;
92 marvell,pcie-port = <0>;
93 marvell,pcie-lane = <0>;
94 clocks = <&gateclk 5>;
100 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
101 reg = <0x1000 0 0 0 0>;
102 #address-cells = <3>;
104 #interrupt-cells = <1>;
105 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
106 0x81000000 0 0 0x81000000 0x2 0 1 0>;
107 interrupt-map-mask = <0 0 0 0>;
108 interrupt-map = <0 0 0 0 &mpic 59>;
109 marvell,pcie-port = <0>;
110 marvell,pcie-lane = <1>;
111 clocks = <&gateclk 6>;
117 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
118 reg = <0x1800 0 0 0 0>;
119 #address-cells = <3>;
121 #interrupt-cells = <1>;
122 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
123 0x81000000 0 0 0x81000000 0x3 0 1 0>;
124 interrupt-map-mask = <0 0 0 0>;
125 interrupt-map = <0 0 0 0 &mpic 60>;
126 marvell,pcie-port = <0>;
127 marvell,pcie-lane = <2>;
128 clocks = <&gateclk 7>;
134 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
135 reg = <0x2000 0 0 0 0>;
136 #address-cells = <3>;
138 #interrupt-cells = <1>;
139 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
140 0x81000000 0 0 0x81000000 0x4 0 1 0>;
141 interrupt-map-mask = <0 0 0 0>;
142 interrupt-map = <0 0 0 0 &mpic 61>;
143 marvell,pcie-port = <0>;
144 marvell,pcie-lane = <3>;
145 clocks = <&gateclk 8>;
151 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
152 reg = <0x2800 0 0 0 0>;
153 #address-cells = <3>;
155 #interrupt-cells = <1>;
156 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
157 0x81000000 0 0 0x81000000 0x5 0 1 0>;
158 interrupt-map-mask = <0 0 0 0>;
159 interrupt-map = <0 0 0 0 &mpic 62>;
160 marvell,pcie-port = <1>;
161 marvell,pcie-lane = <0>;
162 clocks = <&gateclk 9>;
169 compatible = "marvell,mv78230-pinctrl";
170 reg = <0x18000 0x38>;
172 sdio_pins: sdio-pins {
173 marvell,pins = "mpp30", "mpp31", "mpp32",
174 "mpp33", "mpp34", "mpp35";
175 marvell,function = "sd0";
180 compatible = "marvell,orion-gpio";
181 reg = <0x18100 0x40>;
185 interrupt-controller;
186 #interrupt-cells = <2>;
187 interrupts = <82>, <83>, <84>, <85>;
191 compatible = "marvell,orion-gpio";
192 reg = <0x18140 0x40>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
198 interrupts = <87>, <88>, <89>;