2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * Contains definitions specific to the Armada XP MV78260 SoC that are not
13 * common to all Armada XP SoCs.
16 #include "armada-xp.dtsi"
19 model = "Marvell Armada XP MV78260 SoC";
20 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
34 compatible = "marvell,sheeva-v7";
41 compatible = "marvell,sheeva-v7";
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
50 * configured as x4 or quad x1 lanes. One unit is
54 compatible = "marvell,armada-xp-pcie";
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
75 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
76 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
77 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
78 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
79 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
80 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
81 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
83 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
84 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
85 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
86 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
87 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
88 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
89 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
90 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
92 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
93 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
97 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
98 reg = <0x0800 0 0 0 0>;
101 #interrupt-cells = <1>;
102 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
103 0x81000000 0 0 0x81000000 0x1 0 1 0>;
104 interrupt-map-mask = <0 0 0 0>;
105 interrupt-map = <0 0 0 0 &mpic 58>;
106 marvell,pcie-port = <0>;
107 marvell,pcie-lane = <0>;
108 clocks = <&gateclk 5>;
114 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
115 reg = <0x1000 0 0 0 0>;
116 #address-cells = <3>;
118 #interrupt-cells = <1>;
119 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
120 0x81000000 0 0 0x81000000 0x2 0 1 0>;
121 interrupt-map-mask = <0 0 0 0>;
122 interrupt-map = <0 0 0 0 &mpic 59>;
123 marvell,pcie-port = <0>;
124 marvell,pcie-lane = <1>;
125 clocks = <&gateclk 6>;
131 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
132 reg = <0x1800 0 0 0 0>;
133 #address-cells = <3>;
135 #interrupt-cells = <1>;
136 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
137 0x81000000 0 0 0x81000000 0x3 0 1 0>;
138 interrupt-map-mask = <0 0 0 0>;
139 interrupt-map = <0 0 0 0 &mpic 60>;
140 marvell,pcie-port = <0>;
141 marvell,pcie-lane = <2>;
142 clocks = <&gateclk 7>;
148 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
149 reg = <0x2000 0 0 0 0>;
150 #address-cells = <3>;
152 #interrupt-cells = <1>;
153 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
154 0x81000000 0 0 0x81000000 0x4 0 1 0>;
155 interrupt-map-mask = <0 0 0 0>;
156 interrupt-map = <0 0 0 0 &mpic 61>;
157 marvell,pcie-port = <0>;
158 marvell,pcie-lane = <3>;
159 clocks = <&gateclk 8>;
165 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
166 reg = <0x2800 0 0 0 0>;
167 #address-cells = <3>;
169 #interrupt-cells = <1>;
170 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
171 0x81000000 0 0 0x81000000 0x5 0 1 0>;
172 interrupt-map-mask = <0 0 0 0>;
173 interrupt-map = <0 0 0 0 &mpic 62>;
174 marvell,pcie-port = <1>;
175 marvell,pcie-lane = <0>;
176 clocks = <&gateclk 9>;
182 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
183 reg = <0x3000 0 0 0 0>;
184 #address-cells = <3>;
186 #interrupt-cells = <1>;
187 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
188 0x81000000 0 0 0x81000000 0x6 0 1 0>;
189 interrupt-map-mask = <0 0 0 0>;
190 interrupt-map = <0 0 0 0 &mpic 63>;
191 marvell,pcie-port = <1>;
192 marvell,pcie-lane = <1>;
193 clocks = <&gateclk 10>;
199 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
200 reg = <0x3800 0 0 0 0>;
201 #address-cells = <3>;
203 #interrupt-cells = <1>;
204 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
205 0x81000000 0 0 0x81000000 0x7 0 1 0>;
206 interrupt-map-mask = <0 0 0 0>;
207 interrupt-map = <0 0 0 0 &mpic 64>;
208 marvell,pcie-port = <1>;
209 marvell,pcie-lane = <2>;
210 clocks = <&gateclk 11>;
216 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
217 reg = <0x4000 0 0 0 0>;
218 #address-cells = <3>;
220 #interrupt-cells = <1>;
221 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
222 0x81000000 0 0 0x81000000 0x8 0 1 0>;
223 interrupt-map-mask = <0 0 0 0>;
224 interrupt-map = <0 0 0 0 &mpic 65>;
225 marvell,pcie-port = <1>;
226 marvell,pcie-lane = <3>;
227 clocks = <&gateclk 12>;
233 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
234 reg = <0x4800 0 0 0 0>;
235 #address-cells = <3>;
237 #interrupt-cells = <1>;
238 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
239 0x81000000 0 0 0x81000000 0x9 0 1 0>;
240 interrupt-map-mask = <0 0 0 0>;
241 interrupt-map = <0 0 0 0 &mpic 99>;
242 marvell,pcie-port = <2>;
243 marvell,pcie-lane = <0>;
244 clocks = <&gateclk 26>;
251 compatible = "marvell,mv78260-pinctrl";
252 reg = <0x18000 0x38>;
254 sdio_pins: sdio-pins {
255 marvell,pins = "mpp30", "mpp31", "mpp32",
256 "mpp33", "mpp34", "mpp35";
257 marvell,function = "sd0";
262 compatible = "marvell,orion-gpio";
263 reg = <0x18100 0x40>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
269 interrupts = <82>, <83>, <84>, <85>;
273 compatible = "marvell,orion-gpio";
274 reg = <0x18140 0x40>;
278 interrupt-controller;
279 #interrupt-cells = <2>;
280 interrupts = <87>, <88>, <89>, <90>;
284 compatible = "marvell,orion-gpio";
285 reg = <0x18180 0x40>;
289 interrupt-controller;
290 #interrupt-cells = <2>;
295 compatible = "marvell,armada-370-neta";
296 reg = <0x34000 0x4000>;
298 clocks = <&gateclk 1>;