2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * Contains definitions specific to the Armada XP MV78460 SoC that are not
13 * common to all Armada XP SoCs.
16 /include/ "armada-xp.dtsi"
19 model = "Marvell Armada XP MV78460 SoC";
20 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
35 compatible = "marvell,sheeva-v7";
42 compatible = "marvell,sheeva-v7";
49 compatible = "marvell,sheeva-v7";
56 compatible = "marvell,sheeva-v7";
64 compatible = "marvell,mv78460-pinctrl";
65 reg = <0xd0018000 0x38>;
67 sdio_pins: sdio-pins {
68 marvell,pins = "mpp30", "mpp31", "mpp32",
69 "mpp33", "mpp34", "mpp35";
70 marvell,function = "sd0";
74 gpio0: gpio@d0018100 {
75 compatible = "marvell,orion-gpio";
76 reg = <0xd0018100 0x40>;
81 #interrupts-cells = <2>;
82 interrupts = <82>, <83>, <84>, <85>;
85 gpio1: gpio@d0018140 {
86 compatible = "marvell,orion-gpio";
87 reg = <0xd0018140 0x40>;
92 #interrupts-cells = <2>;
93 interrupts = <87>, <88>, <89>, <90>;
96 gpio2: gpio@d0018180 {
97 compatible = "marvell,orion-gpio";
98 reg = <0xd0018180 0x40>;
102 interrupt-controller;
103 #interrupts-cells = <2>;
108 compatible = "marvell,armada-370-neta";
109 reg = <0xd0034000 0x2500>;
111 clocks = <&gateclk 1>;
116 * MV78460 has 4 PCIe units Gen2.0: Two units can be
117 * configured as x4 or quad x1 lanes. Two units are
121 compatible = "marvell,armada-xp-pcie";
125 #address-cells = <3>;
128 bus-range = <0x00 0xff>;
130 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
131 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
132 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
133 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
134 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
135 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
136 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
137 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
138 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
139 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
140 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
141 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
145 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
146 reg = <0x0800 0 0 0 0>;
147 #address-cells = <3>;
149 #interrupt-cells = <1>;
151 interrupt-map-mask = <0 0 0 0>;
152 interrupt-map = <0 0 0 0 &mpic 58>;
153 marvell,pcie-port = <0>;
154 marvell,pcie-lane = <0>;
155 clocks = <&gateclk 5>;
161 assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
162 reg = <0x1000 0 0 0 0>;
163 #address-cells = <3>;
165 #interrupt-cells = <1>;
167 interrupt-map-mask = <0 0 0 0>;
168 interrupt-map = <0 0 0 0 &mpic 59>;
169 marvell,pcie-port = <0>;
170 marvell,pcie-lane = <1>;
171 clocks = <&gateclk 6>;
177 assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
178 reg = <0x1800 0 0 0 0>;
179 #address-cells = <3>;
181 #interrupt-cells = <1>;
183 interrupt-map-mask = <0 0 0 0>;
184 interrupt-map = <0 0 0 0 &mpic 60>;
185 marvell,pcie-port = <0>;
186 marvell,pcie-lane = <2>;
187 clocks = <&gateclk 7>;
193 assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
194 reg = <0x2000 0 0 0 0>;
195 #address-cells = <3>;
197 #interrupt-cells = <1>;
199 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 61>;
201 marvell,pcie-port = <0>;
202 marvell,pcie-lane = <3>;
203 clocks = <&gateclk 8>;
209 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
210 reg = <0x2800 0 0 0 0>;
211 #address-cells = <3>;
213 #interrupt-cells = <1>;
215 interrupt-map-mask = <0 0 0 0>;
216 interrupt-map = <0 0 0 0 &mpic 62>;
217 marvell,pcie-port = <1>;
218 marvell,pcie-lane = <0>;
219 clocks = <&gateclk 9>;
225 assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
226 reg = <0x3000 0 0 0 0>;
227 #address-cells = <3>;
229 #interrupt-cells = <1>;
231 interrupt-map-mask = <0 0 0 0>;
232 interrupt-map = <0 0 0 0 &mpic 63>;
233 marvell,pcie-port = <1>;
234 marvell,pcie-lane = <1>;
235 clocks = <&gateclk 10>;
241 assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
242 reg = <0x3800 0 0 0 0>;
243 #address-cells = <3>;
245 #interrupt-cells = <1>;
247 interrupt-map-mask = <0 0 0 0>;
248 interrupt-map = <0 0 0 0 &mpic 64>;
249 marvell,pcie-port = <1>;
250 marvell,pcie-lane = <2>;
251 clocks = <&gateclk 11>;
257 assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
258 reg = <0x4000 0 0 0 0>;
259 #address-cells = <3>;
261 #interrupt-cells = <1>;
263 interrupt-map-mask = <0 0 0 0>;
264 interrupt-map = <0 0 0 0 &mpic 65>;
265 marvell,pcie-port = <1>;
266 marvell,pcie-lane = <3>;
267 clocks = <&gateclk 12>;
272 assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
273 reg = <0x4800 0 0 0 0>;
274 #address-cells = <3>;
276 #interrupt-cells = <1>;
278 interrupt-map-mask = <0 0 0 0>;
279 interrupt-map = <0 0 0 0 &mpic 99>;
280 marvell,pcie-port = <2>;
281 marvell,pcie-lane = <0>;
282 clocks = <&gateclk 26>;
288 assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
289 reg = <0x5000 0 0 0 0>;
290 #address-cells = <3>;
292 #interrupt-cells = <1>;
294 interrupt-map-mask = <0 0 0 0>;
295 interrupt-map = <0 0 0 0 &mpic 103>;
296 marvell,pcie-port = <3>;
297 marvell,pcie-lane = <0>;
298 clocks = <&gateclk 27>;