2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * Contains definitions specific to the Armada XP MV78460 SoC that are not
13 * common to all Armada XP SoCs.
16 #include "armada-xp.dtsi"
19 model = "Marvell Armada XP MV78460 SoC";
20 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
33 enable-method = "marvell,armada-xp-smp";
37 compatible = "marvell,sheeva-v7";
40 clock-latency = <1000000>;
45 compatible = "marvell,sheeva-v7";
48 clock-latency = <1000000>;
53 compatible = "marvell,sheeva-v7";
56 clock-latency = <1000000>;
61 compatible = "marvell,sheeva-v7";
64 clock-latency = <1000000>;
70 * MV78460 has 4 PCIe units Gen2.0: Two units can be
71 * configured as x4 or quad x1 lanes. Two units are
75 compatible = "marvell,armada-xp-pcie";
83 bus-range = <0x00 0xff>;
86 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
87 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
88 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
89 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
90 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
91 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
92 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
93 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
94 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
95 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
96 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
97 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
98 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
99 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
100 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
101 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
102 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
103 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
105 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
106 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
107 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
108 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
109 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
110 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
111 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
112 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
114 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
115 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
117 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
118 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
122 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
123 reg = <0x0800 0 0 0 0>;
124 #address-cells = <3>;
126 #interrupt-cells = <1>;
127 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
128 0x81000000 0 0 0x81000000 0x1 0 1 0>;
129 interrupt-map-mask = <0 0 0 0>;
130 interrupt-map = <0 0 0 0 &mpic 58>;
131 marvell,pcie-port = <0>;
132 marvell,pcie-lane = <0>;
133 clocks = <&gateclk 5>;
139 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
140 reg = <0x1000 0 0 0 0>;
141 #address-cells = <3>;
143 #interrupt-cells = <1>;
144 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
145 0x81000000 0 0 0x81000000 0x2 0 1 0>;
146 interrupt-map-mask = <0 0 0 0>;
147 interrupt-map = <0 0 0 0 &mpic 59>;
148 marvell,pcie-port = <0>;
149 marvell,pcie-lane = <1>;
150 clocks = <&gateclk 6>;
156 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
157 reg = <0x1800 0 0 0 0>;
158 #address-cells = <3>;
160 #interrupt-cells = <1>;
161 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
162 0x81000000 0 0 0x81000000 0x3 0 1 0>;
163 interrupt-map-mask = <0 0 0 0>;
164 interrupt-map = <0 0 0 0 &mpic 60>;
165 marvell,pcie-port = <0>;
166 marvell,pcie-lane = <2>;
167 clocks = <&gateclk 7>;
173 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
174 reg = <0x2000 0 0 0 0>;
175 #address-cells = <3>;
177 #interrupt-cells = <1>;
178 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
179 0x81000000 0 0 0x81000000 0x4 0 1 0>;
180 interrupt-map-mask = <0 0 0 0>;
181 interrupt-map = <0 0 0 0 &mpic 61>;
182 marvell,pcie-port = <0>;
183 marvell,pcie-lane = <3>;
184 clocks = <&gateclk 8>;
190 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
191 reg = <0x2800 0 0 0 0>;
192 #address-cells = <3>;
194 #interrupt-cells = <1>;
195 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
196 0x81000000 0 0 0x81000000 0x5 0 1 0>;
197 interrupt-map-mask = <0 0 0 0>;
198 interrupt-map = <0 0 0 0 &mpic 62>;
199 marvell,pcie-port = <1>;
200 marvell,pcie-lane = <0>;
201 clocks = <&gateclk 9>;
207 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
208 reg = <0x3000 0 0 0 0>;
209 #address-cells = <3>;
211 #interrupt-cells = <1>;
212 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
213 0x81000000 0 0 0x81000000 0x6 0 1 0>;
214 interrupt-map-mask = <0 0 0 0>;
215 interrupt-map = <0 0 0 0 &mpic 63>;
216 marvell,pcie-port = <1>;
217 marvell,pcie-lane = <1>;
218 clocks = <&gateclk 10>;
224 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
225 reg = <0x3800 0 0 0 0>;
226 #address-cells = <3>;
228 #interrupt-cells = <1>;
229 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
230 0x81000000 0 0 0x81000000 0x7 0 1 0>;
231 interrupt-map-mask = <0 0 0 0>;
232 interrupt-map = <0 0 0 0 &mpic 64>;
233 marvell,pcie-port = <1>;
234 marvell,pcie-lane = <2>;
235 clocks = <&gateclk 11>;
241 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
242 reg = <0x4000 0 0 0 0>;
243 #address-cells = <3>;
245 #interrupt-cells = <1>;
246 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
247 0x81000000 0 0 0x81000000 0x8 0 1 0>;
248 interrupt-map-mask = <0 0 0 0>;
249 interrupt-map = <0 0 0 0 &mpic 65>;
250 marvell,pcie-port = <1>;
251 marvell,pcie-lane = <3>;
252 clocks = <&gateclk 12>;
258 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
259 reg = <0x4800 0 0 0 0>;
260 #address-cells = <3>;
262 #interrupt-cells = <1>;
263 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
264 0x81000000 0 0 0x81000000 0x9 0 1 0>;
265 interrupt-map-mask = <0 0 0 0>;
266 interrupt-map = <0 0 0 0 &mpic 99>;
267 marvell,pcie-port = <2>;
268 marvell,pcie-lane = <0>;
269 clocks = <&gateclk 26>;
275 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
276 reg = <0x5000 0 0 0 0>;
277 #address-cells = <3>;
279 #interrupt-cells = <1>;
280 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
281 0x81000000 0 0 0x81000000 0xa 0 1 0>;
282 interrupt-map-mask = <0 0 0 0>;
283 interrupt-map = <0 0 0 0 &mpic 103>;
284 marvell,pcie-port = <3>;
285 marvell,pcie-lane = <0>;
286 clocks = <&gateclk 27>;
293 compatible = "marvell,orion-gpio";
294 reg = <0x18100 0x40>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
300 interrupts = <82>, <83>, <84>, <85>;
304 compatible = "marvell,orion-gpio";
305 reg = <0x18140 0x40>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 interrupts = <87>, <88>, <89>, <90>;
315 compatible = "marvell,orion-gpio";
316 reg = <0x18180 0x40>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
325 eth3: ethernet@34000 {
326 compatible = "marvell,armada-370-neta";
327 reg = <0x34000 0x4000>;
329 clocks = <&gateclk 1>;
337 compatible = "marvell,mv78460-pinctrl";