2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * Contains definitions specific to the Armada XP MV78460 SoC that are not
13 * common to all Armada XP SoCs.
16 #include "armada-xp.dtsi"
19 model = "Marvell Armada XP MV78460 SoC";
20 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
36 compatible = "marvell,sheeva-v7";
43 compatible = "marvell,sheeva-v7";
50 compatible = "marvell,sheeva-v7";
57 compatible = "marvell,sheeva-v7";
65 * MV78460 has 4 PCIe units Gen2.0: Two units can be
66 * configured as x4 or quad x1 lanes. Two units are
70 compatible = "marvell,armada-xp-pcie";
77 bus-range = <0x00 0xff>;
80 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
81 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
82 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
83 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
84 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
85 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
86 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
87 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
88 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
89 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
90 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
91 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
92 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
93 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
94 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
95 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
96 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
97 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
99 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
100 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
101 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
102 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
103 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
104 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
105 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
106 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
108 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
109 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
111 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
112 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
116 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
117 reg = <0x0800 0 0 0 0>;
118 #address-cells = <3>;
120 #interrupt-cells = <1>;
121 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
122 0x81000000 0 0 0x81000000 0x1 0 1 0>;
123 interrupt-map-mask = <0 0 0 0>;
124 interrupt-map = <0 0 0 0 &mpic 58>;
125 marvell,pcie-port = <0>;
126 marvell,pcie-lane = <0>;
127 clocks = <&gateclk 5>;
133 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
134 reg = <0x1000 0 0 0 0>;
135 #address-cells = <3>;
137 #interrupt-cells = <1>;
138 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
139 0x81000000 0 0 0x81000000 0x2 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &mpic 59>;
142 marvell,pcie-port = <0>;
143 marvell,pcie-lane = <1>;
144 clocks = <&gateclk 6>;
150 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
151 reg = <0x1800 0 0 0 0>;
152 #address-cells = <3>;
154 #interrupt-cells = <1>;
155 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
156 0x81000000 0 0 0x81000000 0x3 0 1 0>;
157 interrupt-map-mask = <0 0 0 0>;
158 interrupt-map = <0 0 0 0 &mpic 60>;
159 marvell,pcie-port = <0>;
160 marvell,pcie-lane = <2>;
161 clocks = <&gateclk 7>;
167 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
168 reg = <0x2000 0 0 0 0>;
169 #address-cells = <3>;
171 #interrupt-cells = <1>;
172 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
173 0x81000000 0 0 0x81000000 0x4 0 1 0>;
174 interrupt-map-mask = <0 0 0 0>;
175 interrupt-map = <0 0 0 0 &mpic 61>;
176 marvell,pcie-port = <0>;
177 marvell,pcie-lane = <3>;
178 clocks = <&gateclk 8>;
184 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
185 reg = <0x2800 0 0 0 0>;
186 #address-cells = <3>;
188 #interrupt-cells = <1>;
189 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
190 0x81000000 0 0 0x81000000 0x5 0 1 0>;
191 interrupt-map-mask = <0 0 0 0>;
192 interrupt-map = <0 0 0 0 &mpic 62>;
193 marvell,pcie-port = <1>;
194 marvell,pcie-lane = <0>;
195 clocks = <&gateclk 9>;
201 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
202 reg = <0x3000 0 0 0 0>;
203 #address-cells = <3>;
205 #interrupt-cells = <1>;
206 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
207 0x81000000 0 0 0x81000000 0x6 0 1 0>;
208 interrupt-map-mask = <0 0 0 0>;
209 interrupt-map = <0 0 0 0 &mpic 63>;
210 marvell,pcie-port = <1>;
211 marvell,pcie-lane = <1>;
212 clocks = <&gateclk 10>;
218 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
219 reg = <0x3800 0 0 0 0>;
220 #address-cells = <3>;
222 #interrupt-cells = <1>;
223 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
224 0x81000000 0 0 0x81000000 0x7 0 1 0>;
225 interrupt-map-mask = <0 0 0 0>;
226 interrupt-map = <0 0 0 0 &mpic 64>;
227 marvell,pcie-port = <1>;
228 marvell,pcie-lane = <2>;
229 clocks = <&gateclk 11>;
235 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
236 reg = <0x4000 0 0 0 0>;
237 #address-cells = <3>;
239 #interrupt-cells = <1>;
240 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
241 0x81000000 0 0 0x81000000 0x8 0 1 0>;
242 interrupt-map-mask = <0 0 0 0>;
243 interrupt-map = <0 0 0 0 &mpic 65>;
244 marvell,pcie-port = <1>;
245 marvell,pcie-lane = <3>;
246 clocks = <&gateclk 12>;
252 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
253 reg = <0x4800 0 0 0 0>;
254 #address-cells = <3>;
256 #interrupt-cells = <1>;
257 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
258 0x81000000 0 0 0x81000000 0x9 0 1 0>;
259 interrupt-map-mask = <0 0 0 0>;
260 interrupt-map = <0 0 0 0 &mpic 99>;
261 marvell,pcie-port = <2>;
262 marvell,pcie-lane = <0>;
263 clocks = <&gateclk 26>;
269 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
270 reg = <0x5000 0 0 0 0>;
271 #address-cells = <3>;
273 #interrupt-cells = <1>;
274 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
275 0x81000000 0 0 0x81000000 0xa 0 1 0>;
276 interrupt-map-mask = <0 0 0 0>;
277 interrupt-map = <0 0 0 0 &mpic 103>;
278 marvell,pcie-port = <3>;
279 marvell,pcie-lane = <0>;
280 clocks = <&gateclk 27>;
287 compatible = "marvell,mv78460-pinctrl";
288 reg = <0x18000 0x38>;
290 sdio_pins: sdio-pins {
291 marvell,pins = "mpp30", "mpp31", "mpp32",
292 "mpp33", "mpp34", "mpp35";
293 marvell,function = "sd0";
298 compatible = "marvell,orion-gpio";
299 reg = <0x18100 0x40>;
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 interrupts = <82>, <83>, <84>, <85>;
309 compatible = "marvell,orion-gpio";
310 reg = <0x18140 0x40>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
316 interrupts = <87>, <88>, <89>, <90>;
320 compatible = "marvell,orion-gpio";
321 reg = <0x18180 0x40>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
330 eth3: ethernet@34000 {
331 compatible = "marvell,armada-370-neta";
332 reg = <0x34000 0x4000>;
334 clocks = <&gateclk 1>;