2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs.
19 /include/ "armada-370-xp.dtsi"
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
26 compatible = "marvell,aurora-system-cache";
27 reg = <0xd0008000 0x1000>;
28 cache-id-part = <0x100>;
32 mpic: interrupt-controller@d0020000 {
33 reg = <0xd0020a00 0x1d0>,
37 armada-370-xp-pmsu@d0022000 {
38 compatible = "marvell,armada-370-xp-pmsu";
39 reg = <0xd0022100 0x430>,
45 compatible = "ns16550";
46 reg = <0xd0012200 0x100>;
52 compatible = "ns16550";
53 reg = <0xd0012300 0x100>;
63 coreclk: mvebu-sar@d0018230 {
64 compatible = "marvell,armada-xp-core-clock";
65 reg = <0xd0018230 0x08>;
69 cpuclk: clock-complex@d0018700 {
71 compatible = "marvell,armada-xp-cpu-clock";
72 reg = <0xd0018700 0xA0>;
73 clocks = <&coreclk 1>;
76 gateclk: clock-gating-control@d0018220 {
77 compatible = "marvell,armada-xp-gating-clock";
78 reg = <0xd0018220 0x4>;
79 clocks = <&coreclk 0>;
83 system-controller@d0018200 {
84 compatible = "marvell,armada-370-xp-system-controller";
85 reg = <0xd0018200 0x500>;
89 compatible = "marvell,armada-370-neta";
90 reg = <0xd0030000 0x2500>;
92 clocks = <&gateclk 2>;
97 compatible = "marvell,armada-370-neta";
98 reg = <0xd0034000 0x2500>;
100 clocks = <&gateclk 1>;
105 compatible = "marvell,orion-xor";
106 reg = <0xd0060900 0x100
108 clocks = <&gateclk 22>;
125 compatible = "marvell,orion-xor";
126 reg = <0xd00F0900 0x100
128 clocks = <&gateclk 28>;