2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
7 * Licensed under GPLv2 or later.
10 #include "skeleton.dtsi"
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Atmel AT91SAM9N12 SoC";
17 compatible = "atmel,at91sam9n12";
18 interrupt-parent = <&aic>;
38 compatible = "arm,arm926ejs";
43 reg = <0x20000000 0x10000000>;
47 compatible = "simple-bus";
53 compatible = "simple-bus";
58 aic: interrupt-controller@fffff000 {
59 #interrupt-cells = <3>;
60 compatible = "atmel,at91rm9200-aic";
62 reg = <0xfffff000 0x200>;
63 atmel,external-irqs = <31>;
66 ramc0: ramc@ffffe800 {
67 compatible = "atmel,at91sam9g45-ddramc";
68 reg = <0xffffe800 0x200>;
72 compatible = "atmel,at91rm9200-pmc";
73 reg = <0xfffffc00 0x100>;
77 compatible = "atmel,at91sam9g45-rstc";
78 reg = <0xfffffe00 0x10>;
82 compatible = "atmel,at91sam9260-pit";
83 reg = <0xfffffe30 0xf>;
84 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
88 compatible = "atmel,at91sam9x5-shdwc";
89 reg = <0xfffffe10 0x10>;
93 compatible = "atmel,hsmci";
94 reg = <0xf0008000 0x600>;
95 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
103 tcb0: timer@f8008000 {
104 compatible = "atmel,at91sam9x5-tcb";
105 reg = <0xf8008000 0x100>;
106 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
109 tcb1: timer@f800c000 {
110 compatible = "atmel,at91sam9x5-tcb";
111 reg = <0xf800c000 0x100>;
112 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
115 dma: dma-controller@ffffec00 {
116 compatible = "atmel,at91sam9g45-dma";
117 reg = <0xffffec00 0x200>;
118 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
123 #address-cells = <1>;
125 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
126 ranges = <0xfffff400 0xfffff400 0x800>;
130 0xffffffff 0xffe07983 0x00000000 /* pioA */
131 0x00040000 0x00047e0f 0x00000000 /* pioB */
132 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
133 0x003fffff 0x003f8000 0x00000000 /* pioD */
136 /* shared pinctrl settings */
138 pinctrl_dbgu: dbgu-0 {
140 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
141 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
146 pinctrl_usart0: usart0-0 {
148 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
149 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
152 pinctrl_usart0_rts: usart0_rts-0 {
154 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
157 pinctrl_usart0_cts: usart0_cts-0 {
159 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
164 pinctrl_usart1: usart1-0 {
166 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
167 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
172 pinctrl_usart2: usart2-0 {
174 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
175 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
178 pinctrl_usart2_rts: usart2_rts-0 {
180 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
183 pinctrl_usart2_cts: usart2_cts-0 {
185 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
190 pinctrl_usart3: usart3-0 {
192 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
193 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
196 pinctrl_usart3_rts: usart3_rts-0 {
198 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
201 pinctrl_usart3_cts: usart3_cts-0 {
203 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
208 pinctrl_uart0: uart0-0 {
210 <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
211 AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
216 pinctrl_uart1: uart1-0 {
218 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
219 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
224 pinctrl_nand: nand-0 {
226 <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
227 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
232 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
234 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
235 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
236 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
239 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
241 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
242 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
243 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
246 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
248 <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
249 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
250 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
251 AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
256 pinctrl_ssc0_tx: ssc0_tx-0 {
258 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
259 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
260 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
263 pinctrl_ssc0_rx: ssc0_rx-0 {
265 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
266 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
267 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
272 pinctrl_spi0: spi0-0 {
274 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
275 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
276 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
281 pinctrl_spi1: spi1-0 {
283 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
284 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
285 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
289 pioA: gpio@fffff400 {
290 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
291 reg = <0xfffff400 0x200>;
292 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
299 pioB: gpio@fffff600 {
300 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
301 reg = <0xfffff600 0x200>;
302 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
309 pioC: gpio@fffff800 {
310 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
311 reg = <0xfffff800 0x200>;
312 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
319 pioD: gpio@fffffa00 {
320 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
321 reg = <0xfffffa00 0x200>;
322 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
330 dbgu: serial@fffff200 {
331 compatible = "atmel,at91sam9260-usart";
332 reg = <0xfffff200 0x200>;
333 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_dbgu>;
340 compatible = "atmel,at91sam9g45-ssc";
341 reg = <0xf0010000 0x4000>;
342 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
348 usart0: serial@f801c000 {
349 compatible = "atmel,at91sam9260-usart";
350 reg = <0xf801c000 0x4000>;
351 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_usart0>;
357 usart1: serial@f8020000 {
358 compatible = "atmel,at91sam9260-usart";
359 reg = <0xf8020000 0x4000>;
360 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_usart1>;
366 usart2: serial@f8024000 {
367 compatible = "atmel,at91sam9260-usart";
368 reg = <0xf8024000 0x4000>;
369 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_usart2>;
375 usart3: serial@f8028000 {
376 compatible = "atmel,at91sam9260-usart";
377 reg = <0xf8028000 0x4000>;
378 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_usart3>;
385 compatible = "atmel,at91sam9x5-i2c";
386 reg = <0xf8010000 0x100>;
387 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
390 dma-names = "tx", "rx";
391 #address-cells = <1>;
397 compatible = "atmel,at91sam9x5-i2c";
398 reg = <0xf8014000 0x100>;
399 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
402 dma-names = "tx", "rx";
403 #address-cells = <1>;
409 #address-cells = <1>;
411 compatible = "atmel,at91rm9200-spi";
412 reg = <0xf0000000 0x100>;
413 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_spi0>;
420 #address-cells = <1>;
422 compatible = "atmel,at91rm9200-spi";
423 reg = <0xf0004000 0x100>;
424 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_spi1>;
431 nand0: nand@40000000 {
432 compatible = "atmel,at91rm9200-nand";
433 #address-cells = <1>;
435 reg = < 0x40000000 0x10000000
436 0xffffe000 0x00000600
437 0xffffe600 0x00000200
438 0x00108000 0x00018000
440 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
441 atmel,nand-addr-offset = <21>;
442 atmel,nand-cmd-offset = <22>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_nand>;
445 gpios = <&pioD 5 GPIO_ACTIVE_HIGH
446 &pioD 4 GPIO_ACTIVE_HIGH
452 usb0: ohci@00500000 {
453 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
454 reg = <0x00500000 0x00100000>;
455 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
461 compatible = "i2c-gpio";
462 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
463 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
465 i2c-gpio,sda-open-drain;
466 i2c-gpio,scl-open-drain;
467 i2c-gpio,delay-us = <2>; /* ~100 kHz */
468 #address-cells = <1>;