2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
7 * Licensed under GPLv2 or later.
10 /include/ "skeleton.dtsi"
13 model = "Atmel AT91SAM9N12 SoC";
14 compatible = "atmel,at91sam9n12";
15 interrupt-parent = <&aic>;
35 compatible = "arm,arm926ejs";
40 reg = <0x20000000 0x10000000>;
44 compatible = "simple-bus";
50 compatible = "simple-bus";
55 aic: interrupt-controller@fffff000 {
56 #interrupt-cells = <3>;
57 compatible = "atmel,at91rm9200-aic";
59 reg = <0xfffff000 0x200>;
62 ramc0: ramc@ffffe800 {
63 compatible = "atmel,at91sam9g45-ddramc";
64 reg = <0xffffe800 0x200>;
68 compatible = "atmel,at91rm9200-pmc";
69 reg = <0xfffffc00 0x100>;
73 compatible = "atmel,at91sam9g45-rstc";
74 reg = <0xfffffe00 0x10>;
78 compatible = "atmel,at91sam9260-pit";
79 reg = <0xfffffe30 0xf>;
84 compatible = "atmel,at91sam9x5-shdwc";
85 reg = <0xfffffe10 0x10>;
89 compatible = "atmel,hsmci";
90 reg = <0xf0008000 0x600>;
91 interrupts = <12 4 0>;
99 tcb0: timer@f8008000 {
100 compatible = "atmel,at91sam9x5-tcb";
101 reg = <0xf8008000 0x100>;
102 interrupts = <17 4 0>;
105 tcb1: timer@f800c000 {
106 compatible = "atmel,at91sam9x5-tcb";
107 reg = <0xf800c000 0x100>;
108 interrupts = <17 4 0>;
111 dma: dma-controller@ffffec00 {
112 compatible = "atmel,at91sam9g45-dma";
113 reg = <0xffffec00 0x200>;
114 interrupts = <20 4 0>;
119 #address-cells = <1>;
121 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
122 ranges = <0xfffff400 0xfffff400 0x800>;
126 0xffffffff 0xffe07983 0x00000000 /* pioA */
127 0x00040000 0x00047e0f 0x00000000 /* pioB */
128 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
129 0x003fffff 0x003f8000 0x00000000 /* pioD */
132 /* shared pinctrl settings */
134 pinctrl_dbgu: dbgu-0 {
136 <0 9 0x1 0x0 /* PA9 periph A */
137 0 10 0x1 0x1>; /* PA10 periph with pullup */
142 pinctrl_usart0: usart0-0 {
144 <0 1 0x1 0x1 /* PA1 periph A with pullup */
145 0 0 0x1 0x0>; /* PA0 periph A */
148 pinctrl_usart0_rts: usart0_rts-0 {
150 <0 2 0x1 0x0>; /* PA2 periph A */
153 pinctrl_usart0_cts: usart0_cts-0 {
155 <0 3 0x1 0x0>; /* PA3 periph A */
160 pinctrl_usart1: usart1-0 {
162 <0 6 0x1 0x1 /* PA6 periph A with pullup */
163 0 5 0x1 0x0>; /* PA5 periph A */
168 pinctrl_usart2: usart2-0 {
170 <0 8 0x1 0x1 /* PA8 periph A with pullup */
171 0 7 0x1 0x0>; /* PA7 periph A */
174 pinctrl_usart2_rts: usart2_rts-0 {
176 <1 0 0x2 0x0>; /* PB0 periph B */
179 pinctrl_usart2_cts: usart2_cts-0 {
181 <1 1 0x2 0x0>; /* PB1 periph B */
186 pinctrl_usart3: usart3-0 {
188 <2 23 0x2 0x1 /* PC23 periph B with pullup */
189 2 22 0x2 0x0>; /* PC22 periph B */
192 pinctrl_usart3_rts: usart3_rts-0 {
194 <2 24 0x2 0x0>; /* PC24 periph B */
197 pinctrl_usart3_cts: usart3_cts-0 {
199 <2 25 0x2 0x0>; /* PC25 periph B */
204 pinctrl_uart0: uart0-0 {
206 <2 9 0x3 0x1 /* PC9 periph C with pullup */
207 2 8 0x3 0x0>; /* PC8 periph C */
212 pinctrl_uart1: uart1-0 {
214 <2 16 0x3 0x1 /* PC17 periph C with pullup */
215 2 17 0x3 0x0>; /* PC16 periph C */
220 pinctrl_nand: nand-0 {
222 <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
223 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
228 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
230 <0 17 0x1 0x0 /* PA17 periph A */
231 0 16 0x1 0x1 /* PA16 periph A with pullup */
232 0 15 0x1 0x1>; /* PA15 periph A with pullup */
235 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
237 <0 18 0x1 0x1 /* PA18 periph A with pullup */
238 0 19 0x1 0x1 /* PA19 periph A with pullup */
239 0 20 0x1 0x1>; /* PA20 periph A with pullup */
242 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
244 <0 11 0x2 0x1 /* PA11 periph B with pullup */
245 0 12 0x2 0x1 /* PA12 periph B with pullup */
246 0 13 0x2 0x1 /* PA13 periph B with pullup */
247 0 14 0x2 0x1>; /* PA14 periph B with pullup */
252 pinctrl_ssc0_tx: ssc0_tx-0 {
254 <0 24 0x2 0x0 /* PA24 periph B */
255 0 25 0x2 0x0 /* PA25 periph B */
256 0 26 0x2 0x0>; /* PA26 periph B */
259 pinctrl_ssc0_rx: ssc0_rx-0 {
261 <0 27 0x2 0x0 /* PA27 periph B */
262 0 28 0x2 0x0 /* PA28 periph B */
263 0 29 0x2 0x0>; /* PA29 periph B */
268 pinctrl_spi0: spi0-0 {
270 <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */
271 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */
272 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
277 pinctrl_spi1: spi1-0 {
279 <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */
280 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */
281 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
285 pioA: gpio@fffff400 {
286 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
287 reg = <0xfffff400 0x200>;
288 interrupts = <2 4 1>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
295 pioB: gpio@fffff600 {
296 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
297 reg = <0xfffff600 0x200>;
298 interrupts = <2 4 1>;
301 interrupt-controller;
302 #interrupt-cells = <2>;
305 pioC: gpio@fffff800 {
306 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
307 reg = <0xfffff800 0x200>;
308 interrupts = <3 4 1>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
315 pioD: gpio@fffffa00 {
316 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
317 reg = <0xfffffa00 0x200>;
318 interrupts = <3 4 1>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
326 dbgu: serial@fffff200 {
327 compatible = "atmel,at91sam9260-usart";
328 reg = <0xfffff200 0x200>;
329 interrupts = <1 4 7>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_dbgu>;
336 compatible = "atmel,at91sam9g45-ssc";
337 reg = <0xf0010000 0x4000>;
338 interrupts = <28 4 5>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
344 usart0: serial@f801c000 {
345 compatible = "atmel,at91sam9260-usart";
346 reg = <0xf801c000 0x4000>;
347 interrupts = <5 4 5>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_usart0>;
353 usart1: serial@f8020000 {
354 compatible = "atmel,at91sam9260-usart";
355 reg = <0xf8020000 0x4000>;
356 interrupts = <6 4 5>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_usart1>;
362 usart2: serial@f8024000 {
363 compatible = "atmel,at91sam9260-usart";
364 reg = <0xf8024000 0x4000>;
365 interrupts = <7 4 5>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_usart2>;
371 usart3: serial@f8028000 {
372 compatible = "atmel,at91sam9260-usart";
373 reg = <0xf8028000 0x4000>;
374 interrupts = <8 4 5>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_usart3>;
381 compatible = "atmel,at91sam9x5-i2c";
382 reg = <0xf8010000 0x100>;
383 interrupts = <9 4 6>;
386 dma-names = "tx", "rx";
387 #address-cells = <1>;
393 compatible = "atmel,at91sam9x5-i2c";
394 reg = <0xf8014000 0x100>;
395 interrupts = <10 4 6>;
398 dma-names = "tx", "rx";
399 #address-cells = <1>;
405 #address-cells = <1>;
407 compatible = "atmel,at91rm9200-spi";
408 reg = <0xf0000000 0x100>;
409 interrupts = <13 4 3>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_spi0>;
416 #address-cells = <1>;
418 compatible = "atmel,at91rm9200-spi";
419 reg = <0xf0004000 0x100>;
420 interrupts = <14 4 3>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_spi1>;
427 nand0: nand@40000000 {
428 compatible = "atmel,at91rm9200-nand";
429 #address-cells = <1>;
431 reg = < 0x40000000 0x10000000
432 0xffffe000 0x00000600
433 0xffffe600 0x00000200
434 0x00108000 0x00018000
436 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
437 atmel,nand-addr-offset = <21>;
438 atmel,nand-cmd-offset = <22>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&pinctrl_nand>;
448 usb0: ohci@00500000 {
449 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
450 reg = <0x00500000 0x00100000>;
451 interrupts = <22 4 2>;
457 compatible = "i2c-gpio";
458 gpios = <&pioA 30 0 /* sda */
461 i2c-gpio,sda-open-drain;
462 i2c-gpio,scl-open-drain;
463 i2c-gpio,delay-us = <2>; /* ~100 kHz */
464 #address-cells = <1>;