2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include "skeleton.dtsi"
18 interrupt-parent = <&gic>;
21 compatible = "simple-bus";
22 ranges = <0x00000000 0x18000000 0x00001000>;
27 compatible = "ns16550";
29 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
30 clock-frequency = <100000000>;
35 compatible = "ns16550";
37 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
38 clock-frequency = <100000000>;
44 compatible = "simple-bus";
45 ranges = <0x00000000 0x19020000 0x00003000>;
50 compatible = "arm,cortex-a9-scu";
55 compatible = "arm,cortex-a9-global-timer";
57 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&clk_periph>;
62 compatible = "arm,cortex-a9-twd-timer";
64 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
65 clocks = <&clk_periph>;
68 gic: interrupt-controller@1000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
73 reg = <0x1000 0x1000>,
77 L2: cache-controller@2000 {
78 compatible = "arm,pl310-cache";
79 reg = <0x2000 0x1000>;
89 /* As long as we do not have a real clock driver us this
92 compatible = "fixed-clock";
94 clock-frequency = <400000000>;
99 compatible = "brcm,bus-axi";
100 reg = <0x18000000 0x1000>;
101 ranges = <0x00000000 0x18000000 0x00100000>;
102 #address-cells = <1>;
105 #interrupt-cells = <1>;
106 interrupt-map-mask = <0x000fffff 0xffff>;
109 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
111 /* USB 2.0 Controller */
112 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
114 /* USB 3.0 Controller */
115 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
117 /* Ethernet Controller 0 */
118 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
120 /* Ethernet Controller 1 */
121 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
123 /* Ethernet Controller 2 */
124 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
126 /* Ethernet Controller 3 */
127 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
129 /* NAND Controller */
130 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
131 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
132 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
133 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
134 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
135 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
136 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
137 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
139 chipcommon: chipcommon@0 {
140 reg = <0x00000000 0x1000>;