2 * Broadcom BCM63138 DSL SoCs Device Tree
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
8 #include "skeleton.dtsi"
11 compatible = "brcm,bcm63138";
12 model = "Broadcom BCM63138 DSL SoC";
13 interrupt-parent = <&gic>;
26 compatible = "arm,cortex-a9";
27 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
43 arm_timer_clk: arm_timer_clk {
45 compatible = "fixed-clock";
46 clock-frequency = <500000000>;
49 periph_clk: periph_clk {
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
53 clock-output-names = "periph";
59 compatible = "simple-bus";
60 ranges = <0 0x80000000 0x784000>;
64 L2: cache-controller@1d000 {
65 compatible = "arm,pl310-cache";
66 reg = <0x1d000 0x1000>;
70 cache-size = <0x80000>;
71 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
75 compatible = "arm,cortex-a9-scu";
76 reg = <0x1e000 0x100>;
79 gic: interrupt-controller@1e100 {
80 compatible = "arm,cortex-a9-gic";
83 #interrupt-cells = <3>;
88 global_timer: timer@1e200 {
89 compatible = "arm,cortex-a9-global-timer";
91 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&arm_timer_clk>;
95 local_timer: local-timer@1e600 {
96 compatible = "arm,cortex-a9-twd-timer";
98 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&arm_timer_clk>;
102 twd_watchdog: watchdog@1e620 {
103 compatible = "arm,cortex-a9-twd-wdt";
104 reg = <0x1e620 0x20>;
105 interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
109 /* Legacy UBUS base */
111 compatible = "simple-bus";
112 #address-cells = <1>;
114 ranges = <0 0xfffe8000 0x8100>;
116 serial0: serial@600 {
117 compatible = "brcm,bcm6345-uart";
119 interrupts = <GIC_SPI 32 0>;
120 clocks = <&periph_clk>;
121 clock-names = "periph";
125 serial1: serial@620 {
126 compatible = "brcm,bcm6345-uart";
128 interrupts = <GIC_SPI 33 0>;
129 clocks = <&periph_clk>;
130 clock-names = "periph";