2 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include "skeleton.dtsi"
15 #include <dt-bindings/clock/berlin2.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 model = "Marvell Armada 1500 (BG2) SoC";
20 compatible = "marvell,berlin2", "marvell,berlin";
27 compatible = "marvell,pj4b";
29 next-level-cache = <&l2>;
34 compatible = "marvell,pj4b";
36 next-level-cache = <&l2>;
42 compatible = "fixed-clock";
44 clock-frequency = <25000000>;
48 compatible = "simple-bus";
51 interrupt-parent = <&gic>;
53 ranges = <0 0xf7000000 0x1000000>;
55 l2: l2-cache-controller@ac0000 {
56 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
57 reg = <0xac0000 0x1000>;
62 scu: snoop-control-unit@ad0000 {
63 compatible = "arm,cortex-a9-scu";
64 reg = <0xad0000 0x58>;
67 gic: interrupt-controller@ad1000 {
68 compatible = "arm,cortex-a9-gic";
69 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
71 #interrupt-cells = <3>;
75 compatible = "arm,cortex-a9-twd-timer";
76 reg = <0xad0600 0x20>;
77 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&chip CLKID_TWD>;
82 compatible = "simple-bus";
86 ranges = <0 0xe80000 0x10000>;
87 interrupt-parent = <&aic>;
90 compatible = "snps,dw-apb-gpio";
96 compatible = "snps,dw-apb-gpio-port";
101 interrupt-controller;
102 #interrupt-cells = <2>;
108 compatible = "snps,dw-apb-gpio";
109 reg = <0x0800 0x400>;
110 #address-cells = <1>;
114 compatible = "snps,dw-apb-gpio-port";
119 interrupt-controller;
120 #interrupt-cells = <2>;
126 compatible = "snps,dw-apb-gpio";
127 reg = <0x0c00 0x400>;
128 #address-cells = <1>;
132 compatible = "snps,dw-apb-gpio-port";
137 interrupt-controller;
138 #interrupt-cells = <2>;
144 compatible = "snps,dw-apb-gpio";
145 reg = <0x1000 0x400>;
146 #address-cells = <1>;
150 compatible = "snps,dw-apb-gpio-port";
155 interrupt-controller;
156 #interrupt-cells = <2>;
162 compatible = "snps,dw-apb-timer";
165 clocks = <&chip CLKID_CFG>;
166 clock-names = "timer";
171 compatible = "snps,dw-apb-timer";
174 clocks = <&chip CLKID_CFG>;
175 clock-names = "timer";
180 compatible = "snps,dw-apb-timer";
183 clocks = <&chip CLKID_CFG>;
184 clock-names = "timer";
189 compatible = "snps,dw-apb-timer";
192 clocks = <&chip CLKID_CFG>;
193 clock-names = "timer";
198 compatible = "snps,dw-apb-timer";
201 clocks = <&chip CLKID_CFG>;
202 clock-names = "timer";
207 compatible = "snps,dw-apb-timer";
210 clocks = <&chip CLKID_CFG>;
211 clock-names = "timer";
216 compatible = "snps,dw-apb-timer";
219 clocks = <&chip CLKID_CFG>;
220 clock-names = "timer";
225 compatible = "snps,dw-apb-timer";
228 clocks = <&chip CLKID_CFG>;
229 clock-names = "timer";
233 aic: interrupt-controller@3000 {
234 compatible = "snps,dw-apb-ictl";
235 reg = <0x3000 0xc00>;
236 interrupt-controller;
237 #interrupt-cells = <1>;
238 interrupt-parent = <&gic>;
239 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
243 chip: chip-control@ea0000 {
244 compatible = "marvell,berlin2-chip-ctrl";
246 reg = <0xea0000 0x400>;
248 clock-names = "refclk";
252 compatible = "simple-bus";
253 #address-cells = <1>;
256 ranges = <0 0xfc0000 0x10000>;
257 interrupt-parent = <&sic>;
259 sm_gpio1: gpio@5000 {
260 compatible = "snps,dw-apb-gpio";
261 reg = <0x5000 0x400>;
262 #address-cells = <1>;
266 compatible = "snps,dw-apb-gpio-port";
274 sm_gpio0: gpio@c000 {
275 compatible = "snps,dw-apb-gpio";
276 reg = <0xc000 0x400>;
277 #address-cells = <1>;
281 compatible = "snps,dw-apb-gpio-port";
286 interrupt-controller;
287 #interrupt-cells = <2>;
293 compatible = "snps,dw-apb-uart";
294 reg = <0x9000 0x100>;
299 pinctrl-0 = <&uart0_pmux>;
300 pinctrl-names = "default";
305 compatible = "snps,dw-apb-uart";
306 reg = <0xa000 0x100>;
311 pinctrl-0 = <&uart1_pmux>;
312 pinctrl-names = "default";
317 compatible = "snps,dw-apb-uart";
318 reg = <0xb000 0x100>;
323 pinctrl-0 = <&uart2_pmux>;
324 pinctrl-names = "default";
328 sysctrl: system-controller@d000 {
329 compatible = "marvell,berlin2-system-ctrl";
330 reg = <0xd000 0x100>;
332 uart0_pmux: uart0-pmux {
337 uart1_pmux: uart1-pmux {
342 uart2_pmux: uart2-pmux {
348 sic: interrupt-controller@e000 {
349 compatible = "snps,dw-apb-ictl";
350 reg = <0xe000 0x400>;
351 interrupt-controller;
352 #interrupt-cells = <1>;
353 interrupt-parent = <&gic>;
354 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;