2 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include "skeleton.dtsi"
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 model = "Marvell Armada 1500 (BG2) SoC";
19 compatible = "marvell,berlin2", "marvell,berlin";
26 compatible = "marvell,pj4b";
28 next-level-cache = <&l2>;
33 compatible = "marvell,pj4b";
35 next-level-cache = <&l2>;
42 compatible = "fixed-clock";
44 clock-frequency = <25000000>;
48 compatible = "fixed-clock";
50 clock-frequency = <100000000>;
53 sysclk: system-clock {
54 compatible = "fixed-clock";
56 clock-frequency = <400000000>;
61 compatible = "simple-bus";
64 interrupt-parent = <&gic>;
66 ranges = <0 0xf7000000 0x1000000>;
68 l2: l2-cache-controller@ac0000 {
69 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
70 reg = <0xac0000 0x1000>;
75 gic: interrupt-controller@ad1000 {
76 compatible = "arm,cortex-a9-gic";
77 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
79 #interrupt-cells = <3>;
83 compatible = "arm,cortex-a9-twd-timer";
84 reg = <0xad0600 0x20>;
85 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
90 compatible = "simple-bus";
94 ranges = <0 0xe80000 0x10000>;
95 interrupt-parent = <&aic>;
98 compatible = "snps,dw-apb-timer";
102 clock-names = "timer";
107 compatible = "snps,dw-apb-timer";
111 clock-names = "timer";
116 compatible = "snps,dw-apb-timer";
120 clock-names = "timer";
125 compatible = "snps,dw-apb-timer";
129 clock-names = "timer";
134 compatible = "snps,dw-apb-timer";
138 clock-names = "timer";
143 compatible = "snps,dw-apb-timer";
147 clock-names = "timer";
152 compatible = "snps,dw-apb-timer";
156 clock-names = "timer";
161 compatible = "snps,dw-apb-timer";
165 clock-names = "timer";
169 aic: interrupt-controller@3000 {
170 compatible = "snps,dw-apb-ictl";
171 reg = <0x3000 0xc00>;
172 interrupt-controller;
173 #interrupt-cells = <1>;
174 interrupt-parent = <&gic>;
175 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
180 compatible = "simple-bus";
181 #address-cells = <1>;
184 ranges = <0 0xfc0000 0x10000>;
185 interrupt-parent = <&sic>;
188 compatible = "snps,dw-apb-uart";
189 reg = <0x9000 0x100>;
198 compatible = "snps,dw-apb-uart";
199 reg = <0xa000 0x100>;
208 compatible = "snps,dw-apb-uart";
209 reg = <0xb000 0x100>;
217 sic: interrupt-controller@e000 {
218 compatible = "snps,dw-apb-ictl";
219 reg = <0xe000 0x400>;
220 interrupt-controller;
221 #interrupt-cells = <1>;
222 interrupt-parent = <&gic>;
223 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;