2 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include "skeleton.dtsi"
15 #include <dt-bindings/clock/berlin2.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 model = "Marvell Armada 1500 (BG2) SoC";
20 compatible = "marvell,berlin2", "marvell,berlin";
25 enable-method = "marvell,berlin-smp";
28 compatible = "marvell,pj4b";
30 next-level-cache = <&l2>;
35 compatible = "marvell,pj4b";
37 next-level-cache = <&l2>;
43 compatible = "fixed-clock";
45 clock-frequency = <25000000>;
49 compatible = "simple-bus";
52 interrupt-parent = <&gic>;
54 ranges = <0 0xf7000000 0x1000000>;
56 sdhci0: sdhci@ab0000 {
57 compatible = "mrvl,pxav3-mmc";
58 reg = <0xab0000 0x200>;
59 clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
60 clock-names = "io", "core";
61 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
65 sdhci1: sdhci@ab0800 {
66 compatible = "mrvl,pxav3-mmc";
67 reg = <0xab0800 0x200>;
68 clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
69 clock-names = "io", "core";
70 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
74 sdhci2: sdhci@ab1000 {
75 compatible = "mrvl,pxav3-mmc";
76 reg = <0xab1000 0x200>;
77 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
79 clock-names = "io", "core";
80 pinctrl-0 = <&emmc_pmux>;
81 pinctrl-names = "default";
85 l2: l2-cache-controller@ac0000 {
86 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
87 reg = <0xac0000 0x1000>;
92 scu: snoop-control-unit@ad0000 {
93 compatible = "arm,cortex-a9-scu";
94 reg = <0xad0000 0x58>;
97 gic: interrupt-controller@ad1000 {
98 compatible = "arm,cortex-a9-gic";
99 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
100 interrupt-controller;
101 #interrupt-cells = <3>;
105 compatible = "arm,cortex-a9-twd-timer";
106 reg = <0xad0600 0x20>;
107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
108 clocks = <&chip CLKID_TWD>;
111 eth1: ethernet@b90000 {
112 compatible = "marvell,pxa168-eth";
113 reg = <0xb90000 0x10000>;
114 clocks = <&chip CLKID_GETH1>;
115 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
116 /* set by bootloader */
117 local-mac-address = [00 00 00 00 00 00];
118 #address-cells = <1>;
120 phy-connection-type = "mii";
121 phy-handle = <ðphy1>;
124 ethphy1: ethernet-phy@0 {
130 compatible = "marvell,berlin-cpu-ctrl";
131 reg = <0xdd0000 0x10000>;
134 eth0: ethernet@e50000 {
135 compatible = "marvell,pxa168-eth";
136 reg = <0xe50000 0x10000>;
137 clocks = <&chip CLKID_GETH0>;
138 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
139 /* set by bootloader */
140 local-mac-address = [00 00 00 00 00 00];
141 #address-cells = <1>;
143 phy-connection-type = "mii";
144 phy-handle = <ðphy0>;
147 ethphy0: ethernet-phy@0 {
153 compatible = "simple-bus";
154 #address-cells = <1>;
157 ranges = <0 0xe80000 0x10000>;
158 interrupt-parent = <&aic>;
161 compatible = "snps,dw-apb-gpio";
162 reg = <0x0400 0x400>;
163 #address-cells = <1>;
167 compatible = "snps,dw-apb-gpio-port";
172 interrupt-controller;
173 #interrupt-cells = <2>;
179 compatible = "snps,dw-apb-gpio";
180 reg = <0x0800 0x400>;
181 #address-cells = <1>;
185 compatible = "snps,dw-apb-gpio-port";
190 interrupt-controller;
191 #interrupt-cells = <2>;
197 compatible = "snps,dw-apb-gpio";
198 reg = <0x0c00 0x400>;
199 #address-cells = <1>;
203 compatible = "snps,dw-apb-gpio-port";
208 interrupt-controller;
209 #interrupt-cells = <2>;
215 compatible = "snps,dw-apb-gpio";
216 reg = <0x1000 0x400>;
217 #address-cells = <1>;
221 compatible = "snps,dw-apb-gpio-port";
226 interrupt-controller;
227 #interrupt-cells = <2>;
233 compatible = "snps,dw-apb-timer";
236 clocks = <&chip CLKID_CFG>;
237 clock-names = "timer";
242 compatible = "snps,dw-apb-timer";
245 clocks = <&chip CLKID_CFG>;
246 clock-names = "timer";
251 compatible = "snps,dw-apb-timer";
254 clocks = <&chip CLKID_CFG>;
255 clock-names = "timer";
260 compatible = "snps,dw-apb-timer";
263 clocks = <&chip CLKID_CFG>;
264 clock-names = "timer";
269 compatible = "snps,dw-apb-timer";
272 clocks = <&chip CLKID_CFG>;
273 clock-names = "timer";
278 compatible = "snps,dw-apb-timer";
281 clocks = <&chip CLKID_CFG>;
282 clock-names = "timer";
287 compatible = "snps,dw-apb-timer";
290 clocks = <&chip CLKID_CFG>;
291 clock-names = "timer";
296 compatible = "snps,dw-apb-timer";
299 clocks = <&chip CLKID_CFG>;
300 clock-names = "timer";
304 aic: interrupt-controller@3000 {
305 compatible = "snps,dw-apb-ictl";
306 reg = <0x3000 0xc00>;
307 interrupt-controller;
308 #interrupt-cells = <1>;
309 interrupt-parent = <&gic>;
310 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
315 compatible = "marvell,berlin2-ahci", "generic-ahci";
316 reg = <0xe90000 0x1000>;
317 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&chip CLKID_SATA>;
319 #address-cells = <1>;
324 phys = <&sata_phy 0>;
330 phys = <&sata_phy 1>;
335 sata_phy: phy@e900a0 {
336 compatible = "marvell,berlin2-sata-phy";
337 reg = <0xe900a0 0x200>;
338 clocks = <&chip CLKID_SATA>;
339 #address-cells = <1>;
353 chip: chip-control@ea0000 {
354 compatible = "marvell,berlin2-chip-ctrl";
357 reg = <0xea0000 0x400>;
359 clock-names = "refclk";
361 emmc_pmux: emmc-pmux {
368 compatible = "simple-bus";
369 #address-cells = <1>;
372 ranges = <0 0xfc0000 0x10000>;
373 interrupt-parent = <&sic>;
375 sm_gpio1: gpio@5000 {
376 compatible = "snps,dw-apb-gpio";
377 reg = <0x5000 0x400>;
378 #address-cells = <1>;
382 compatible = "snps,dw-apb-gpio-port";
390 sm_gpio0: gpio@c000 {
391 compatible = "snps,dw-apb-gpio";
392 reg = <0xc000 0x400>;
393 #address-cells = <1>;
397 compatible = "snps,dw-apb-gpio-port";
402 interrupt-controller;
403 #interrupt-cells = <2>;
409 compatible = "snps,dw-apb-uart";
410 reg = <0x9000 0x100>;
415 pinctrl-0 = <&uart0_pmux>;
416 pinctrl-names = "default";
421 compatible = "snps,dw-apb-uart";
422 reg = <0xa000 0x100>;
427 pinctrl-0 = <&uart1_pmux>;
428 pinctrl-names = "default";
433 compatible = "snps,dw-apb-uart";
434 reg = <0xb000 0x100>;
439 pinctrl-0 = <&uart2_pmux>;
440 pinctrl-names = "default";
444 sysctrl: system-controller@d000 {
445 compatible = "marvell,berlin2-system-ctrl";
446 reg = <0xd000 0x100>;
448 uart0_pmux: uart0-pmux {
453 uart1_pmux: uart1-pmux {
458 uart2_pmux: uart2-pmux {
464 sic: interrupt-controller@e000 {
465 compatible = "snps,dw-apb-ictl";
466 reg = <0xe000 0x400>;
467 interrupt-controller;
468 #interrupt-cells = <1>;
469 interrupt-parent = <&gic>;
470 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;