2 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include "skeleton.dtsi"
15 #include <dt-bindings/clock/berlin2.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 model = "Marvell Armada 1500-mini (BG2CD) SoC";
20 compatible = "marvell,berlin2cd", "marvell,berlin";
27 compatible = "arm,cortex-a9";
29 next-level-cache = <&l2>;
35 compatible = "fixed-clock";
37 clock-frequency = <25000000>;
41 compatible = "simple-bus";
44 interrupt-parent = <&gic>;
46 ranges = <0 0xf7000000 0x1000000>;
48 l2: l2-cache-controller@ac0000 {
49 compatible = "arm,pl310-cache";
50 reg = <0xac0000 0x1000>;
55 gic: interrupt-controller@ad1000 {
56 compatible = "arm,cortex-a9-gic";
57 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
59 #interrupt-cells = <3>;
63 compatible = "arm,cortex-a9-twd-timer";
64 reg = <0xad0600 0x20>;
65 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
66 clocks = <&chip CLKID_TWD>;
70 compatible = "simple-bus";
74 ranges = <0 0xe80000 0x10000>;
75 interrupt-parent = <&aic>;
78 compatible = "snps,dw-apb-gpio";
84 compatible = "snps,dw-apb-gpio-port";
90 #interrupt-cells = <2>;
96 compatible = "snps,dw-apb-gpio";
102 compatible = "snps,dw-apb-gpio-port";
107 interrupt-controller;
108 #interrupt-cells = <2>;
114 compatible = "snps,dw-apb-gpio";
115 reg = <0x0c00 0x400>;
116 #address-cells = <1>;
120 compatible = "snps,dw-apb-gpio-port";
125 interrupt-controller;
126 #interrupt-cells = <2>;
132 compatible = "snps,dw-apb-gpio";
133 reg = <0x1000 0x400>;
134 #address-cells = <1>;
138 compatible = "snps,dw-apb-gpio-port";
143 interrupt-controller;
144 #interrupt-cells = <2>;
150 compatible = "snps,dw-apb-timer";
153 clocks = <&chip CLKID_CFG>;
154 clock-names = "timer";
159 compatible = "snps,dw-apb-timer";
162 clocks = <&chip CLKID_CFG>;
163 clock-names = "timer";
168 compatible = "snps,dw-apb-timer";
171 clocks = <&chip CLKID_CFG>;
172 clock-names = "timer";
177 compatible = "snps,dw-apb-timer";
180 clocks = <&chip CLKID_CFG>;
181 clock-names = "timer";
186 compatible = "snps,dw-apb-timer";
189 clocks = <&chip CLKID_CFG>;
190 clock-names = "timer";
195 compatible = "snps,dw-apb-timer";
198 clocks = <&chip CLKID_CFG>;
199 clock-names = "timer";
204 compatible = "snps,dw-apb-timer";
207 clocks = <&chip CLKID_CFG>;
208 clock-names = "timer";
213 compatible = "snps,dw-apb-timer";
216 clocks = <&chip CLKID_CFG>;
217 clock-names = "timer";
221 aic: interrupt-controller@3000 {
222 compatible = "snps,dw-apb-ictl";
223 reg = <0x3000 0xc00>;
224 interrupt-controller;
225 #interrupt-cells = <1>;
226 interrupt-parent = <&gic>;
227 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
231 chip: chip-control@ea0000 {
232 compatible = "marvell,berlin2cd-chip-ctrl";
234 reg = <0xea0000 0x400>;
236 clock-names = "refclk";
238 uart0_pmux: uart0-pmux {
245 compatible = "simple-bus";
246 #address-cells = <1>;
249 ranges = <0 0xfc0000 0x10000>;
250 interrupt-parent = <&sic>;
252 sm_gpio1: gpio@5000 {
253 compatible = "snps,dw-apb-gpio";
254 reg = <0x5000 0x400>;
255 #address-cells = <1>;
259 compatible = "snps,dw-apb-gpio-port";
267 sm_gpio0: gpio@c000 {
268 compatible = "snps,dw-apb-gpio";
269 reg = <0xc000 0x400>;
270 #address-cells = <1>;
274 compatible = "snps,dw-apb-gpio-port";
283 compatible = "snps,dw-apb-uart";
284 reg = <0x9000 0x100>;
289 pinctrl-0 = <&uart0_pmux>;
290 pinctrl-names = "default";
295 compatible = "snps,dw-apb-uart";
296 reg = <0xa000 0x100>;
304 sysctrl: system-controller@d000 {
305 compatible = "marvell,berlin2cd-system-ctrl";
306 reg = <0xd000 0x100>;
309 sic: interrupt-controller@e000 {
310 compatible = "snps,dw-apb-ictl";
311 reg = <0xe000 0x400>;
312 interrupt-controller;
313 #interrupt-cells = <1>;
314 interrupt-parent = <&gic>;
315 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;