2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <dt-bindings/clock/berlin2q.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "skeleton.dtsi"
15 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
16 compatible = "marvell,berlin2q", "marvell,berlin";
21 enable-method = "marvell,berlin-smp";
24 compatible = "arm,cortex-a9";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&l2>;
38 compatible = "arm,cortex-a9";
40 next-level-cache = <&l2>;
45 compatible = "arm,cortex-a9";
47 next-level-cache = <&l2>;
53 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
59 compatible = "simple-bus";
63 ranges = <0 0xf7000000 0x1000000>;
64 interrupt-parent = <&gic>;
66 sdhci0: sdhci@ab0000 {
67 compatible = "mrvl,pxav3-mmc";
68 reg = <0xab0000 0x200>;
69 clocks = <&chip CLKID_SDIO1XIN>;
70 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
74 sdhci1: sdhci@ab0800 {
75 compatible = "mrvl,pxav3-mmc";
76 reg = <0xab0800 0x200>;
77 clocks = <&chip CLKID_SDIO1XIN>;
78 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
82 sdhci2: sdhci@ab1000 {
83 compatible = "mrvl,pxav3-mmc";
84 reg = <0xab1000 0x200>;
85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&chip CLKID_SDIO1XIN>;
90 l2: l2-cache-controller@ac0000 {
91 compatible = "arm,pl310-cache";
92 reg = <0xac0000 0x1000>;
94 arm,data-latency = <2 2 2>;
95 arm,tag-latency = <2 2 2>;
98 scu: snoop-control-unit@ad0000 {
99 compatible = "arm,cortex-a9-scu";
100 reg = <0xad0000 0x58>;
104 compatible = "arm,cortex-a9-twd-timer";
105 reg = <0xad0600 0x20>;
106 clocks = <&chip CLKID_TWD>;
107 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
110 gic: interrupt-controller@ad1000 {
111 compatible = "arm,cortex-a9-gic";
112 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
113 interrupt-controller;
114 #interrupt-cells = <3>;
117 usb_phy2: phy@a2f400 {
118 compatible = "marvell,berlin2-usb-phy";
119 reg = <0xa2f400 0x128>;
121 resets = <&chip 0x104 14>;
126 compatible = "chipidea,usb2";
127 reg = <0xa30000 0x10000>;
128 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&chip CLKID_USB2>;
131 phy-names = "usb-phy";
135 usb_phy0: phy@b74000 {
136 compatible = "marvell,berlin2-usb-phy";
137 reg = <0xb74000 0x128>;
139 resets = <&chip 0x104 12>;
143 usb_phy1: phy@b78000 {
144 compatible = "marvell,berlin2-usb-phy";
145 reg = <0xb78000 0x128>;
147 resets = <&chip 0x104 13>;
151 eth0: ethernet@b90000 {
152 compatible = "marvell,pxa168-eth";
153 reg = <0xb90000 0x10000>;
154 clocks = <&chip CLKID_GETH0>;
155 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
156 /* set by bootloader */
157 local-mac-address = [00 00 00 00 00 00];
158 #address-cells = <1>;
160 phy-connection-type = "mii";
161 phy-handle = <ðphy0>;
164 ethphy0: ethernet-phy@0 {
170 compatible = "marvell,berlin-cpu-ctrl";
171 reg = <0xdd0000 0x10000>;
175 compatible = "simple-bus";
176 #address-cells = <1>;
179 ranges = <0 0xe80000 0x10000>;
180 interrupt-parent = <&aic>;
183 compatible = "snps,dw-apb-gpio";
184 reg = <0x0400 0x400>;
185 #address-cells = <1>;
189 compatible = "snps,dw-apb-gpio-port";
192 snps,nr-gpios = <32>;
194 interrupt-controller;
195 #interrupt-cells = <2>;
201 compatible = "snps,dw-apb-gpio";
202 reg = <0x0800 0x400>;
203 #address-cells = <1>;
207 compatible = "snps,dw-apb-gpio-port";
210 snps,nr-gpios = <32>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
219 compatible = "snps,dw-apb-gpio";
220 reg = <0x0c00 0x400>;
221 #address-cells = <1>;
225 compatible = "snps,dw-apb-gpio-port";
228 snps,nr-gpios = <32>;
230 interrupt-controller;
231 #interrupt-cells = <2>;
237 compatible = "snps,dw-apb-gpio";
238 reg = <0x1000 0x400>;
239 #address-cells = <1>;
243 compatible = "snps,dw-apb-gpio-port";
246 snps,nr-gpios = <32>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
255 compatible = "snps,designware-i2c";
256 #address-cells = <1>;
258 reg = <0x1400 0x100>;
259 interrupt-parent = <&aic>;
261 clocks = <&chip CLKID_CFG>;
262 pinctrl-0 = <&twsi0_pmux>;
263 pinctrl-names = "default";
268 compatible = "snps,designware-i2c";
269 #address-cells = <1>;
271 reg = <0x1800 0x100>;
272 interrupt-parent = <&aic>;
274 clocks = <&chip CLKID_CFG>;
275 pinctrl-0 = <&twsi1_pmux>;
276 pinctrl-names = "default";
281 compatible = "snps,dw-apb-timer";
283 clocks = <&chip CLKID_CFG>;
284 clock-names = "timer";
289 compatible = "snps,dw-apb-timer";
291 clocks = <&chip CLKID_CFG>;
292 clock-names = "timer";
296 compatible = "snps,dw-apb-timer";
298 clocks = <&chip CLKID_CFG>;
299 clock-names = "timer";
304 compatible = "snps,dw-apb-timer";
306 clocks = <&chip CLKID_CFG>;
307 clock-names = "timer";
312 compatible = "snps,dw-apb-timer";
314 clocks = <&chip CLKID_CFG>;
315 clock-names = "timer";
320 compatible = "snps,dw-apb-timer";
322 clocks = <&chip CLKID_CFG>;
323 clock-names = "timer";
328 compatible = "snps,dw-apb-timer";
330 clocks = <&chip CLKID_CFG>;
331 clock-names = "timer";
336 compatible = "snps,dw-apb-timer";
338 clocks = <&chip CLKID_CFG>;
339 clock-names = "timer";
343 aic: interrupt-controller@3800 {
344 compatible = "snps,dw-apb-ictl";
346 interrupt-controller;
347 #interrupt-cells = <1>;
348 interrupt-parent = <&gic>;
349 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
353 compatible = "snps,dw-apb-gpio";
354 reg = <0x5000 0x400>;
355 #address-cells = <1>;
359 compatible = "snps,dw-apb-gpio-port";
362 snps,nr-gpios = <32>;
368 compatible = "snps,dw-apb-gpio";
369 reg = <0xc000 0x400>;
370 #address-cells = <1>;
374 compatible = "snps,dw-apb-gpio-port";
377 snps,nr-gpios = <32>;
383 chip: chip-control@ea0000 {
384 compatible = "marvell,berlin2q-chip-ctrl";
387 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
389 clock-names = "refclk";
391 twsi0_pmux: twsi0-pmux {
396 twsi1_pmux: twsi1-pmux {
403 compatible = "marvell,berlin2q-ahci", "generic-ahci";
404 reg = <0xe90000 0x1000>;
405 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&chip CLKID_SATA>;
407 #address-cells = <1>;
412 phys = <&sata_phy 0>;
418 phys = <&sata_phy 1>;
423 sata_phy: phy@e900a0 {
424 compatible = "marvell,berlin2q-sata-phy";
425 reg = <0xe900a0 0x200>;
426 clocks = <&chip CLKID_SATA>;
427 #address-cells = <1>;
442 compatible = "chipidea,usb2";
443 reg = <0xed0000 0x10000>;
444 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&chip CLKID_USB0>;
447 phy-names = "usb-phy";
452 compatible = "chipidea,usb2";
453 reg = <0xee0000 0x10000>;
454 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&chip CLKID_USB1>;
457 phy-names = "usb-phy";
462 compatible = "simple-bus";
463 #address-cells = <1>;
466 ranges = <0 0xfc0000 0x10000>;
467 interrupt-parent = <&sic>;
470 compatible = "snps,designware-i2c";
471 #address-cells = <1>;
473 reg = <0x7000 0x100>;
474 interrupt-parent = <&sic>;
477 pinctrl-0 = <&twsi2_pmux>;
478 pinctrl-names = "default";
483 compatible = "snps,designware-i2c";
484 #address-cells = <1>;
486 reg = <0x8000 0x100>;
487 interrupt-parent = <&sic>;
490 pinctrl-0 = <&twsi3_pmux>;
491 pinctrl-names = "default";
496 compatible = "snps,dw-apb-uart";
497 reg = <0x9000 0x100>;
498 interrupt-parent = <&sic>;
502 pinctrl-0 = <&uart0_pmux>;
503 pinctrl-names = "default";
508 compatible = "snps,dw-apb-uart";
509 reg = <0xa000 0x100>;
510 interrupt-parent = <&sic>;
514 pinctrl-0 = <&uart1_pmux>;
515 pinctrl-names = "default";
519 sysctrl: pin-controller@d000 {
520 compatible = "marvell,berlin2q-system-ctrl";
521 reg = <0xd000 0x100>;
523 uart0_pmux: uart0-pmux {
528 uart1_pmux: uart1-pmux {
533 twsi2_pmux: twsi2-pmux {
538 twsi3_pmux: twsi3-pmux {
544 sic: interrupt-controller@e000 {
545 compatible = "snps,dw-apb-ictl";
547 interrupt-controller;
548 #interrupt-cells = <1>;
549 interrupt-parent = <&gic>;
550 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;