2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <dt-bindings/clock/berlin2q.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "skeleton.dtsi"
15 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
16 compatible = "marvell,berlin2q", "marvell,berlin";
23 compatible = "arm,cortex-a9";
25 next-level-cache = <&l2>;
30 compatible = "arm,cortex-a9";
32 next-level-cache = <&l2>;
37 compatible = "arm,cortex-a9";
39 next-level-cache = <&l2>;
44 compatible = "arm,cortex-a9";
46 next-level-cache = <&l2>;
52 compatible = "fixed-clock";
54 clock-frequency = <25000000>;
58 compatible = "simple-bus";
62 ranges = <0 0xf7000000 0x1000000>;
63 interrupt-parent = <&gic>;
65 sdhci0: sdhci@ab0000 {
66 compatible = "mrvl,pxav3-mmc";
67 reg = <0xab0000 0x200>;
68 clocks = <&chip CLKID_SDIO1XIN>;
69 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
73 sdhci1: sdhci@ab0800 {
74 compatible = "mrvl,pxav3-mmc";
75 reg = <0xab0800 0x200>;
76 clocks = <&chip CLKID_SDIO1XIN>;
77 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
81 sdhci2: sdhci@ab1000 {
82 compatible = "mrvl,pxav3-mmc";
83 reg = <0xab1000 0x200>;
84 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&chip CLKID_SDIO1XIN>;
89 l2: l2-cache-controller@ac0000 {
90 compatible = "arm,pl310-cache";
91 reg = <0xac0000 0x1000>;
95 scu: snoop-control-unit@ad0000 {
96 compatible = "arm,cortex-a9-scu";
97 reg = <0xad0000 0x58>;
101 compatible = "arm,cortex-a9-twd-timer";
102 reg = <0xad0600 0x20>;
103 clocks = <&chip CLKID_TWD>;
104 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
107 gic: interrupt-controller@ad1000 {
108 compatible = "arm,cortex-a9-gic";
109 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
110 interrupt-controller;
111 #interrupt-cells = <3>;
115 compatible = "simple-bus";
116 #address-cells = <1>;
119 ranges = <0 0xe80000 0x10000>;
120 interrupt-parent = <&aic>;
123 compatible = "snps,dw-apb-gpio";
124 reg = <0x0400 0x400>;
125 #address-cells = <1>;
129 compatible = "snps,dw-apb-gpio-port";
132 snps,nr-gpios = <32>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
141 compatible = "snps,dw-apb-gpio";
142 reg = <0x0800 0x400>;
143 #address-cells = <1>;
147 compatible = "snps,dw-apb-gpio-port";
150 snps,nr-gpios = <32>;
152 interrupt-controller;
153 #interrupt-cells = <2>;
159 compatible = "snps,dw-apb-gpio";
160 reg = <0x0c00 0x400>;
161 #address-cells = <1>;
165 compatible = "snps,dw-apb-gpio-port";
168 snps,nr-gpios = <32>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
177 compatible = "snps,dw-apb-gpio";
178 reg = <0x1000 0x400>;
179 #address-cells = <1>;
183 compatible = "snps,dw-apb-gpio-port";
186 snps,nr-gpios = <32>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
195 compatible = "snps,dw-apb-timer";
197 clocks = <&chip CLKID_CFG>;
198 clock-names = "timer";
203 compatible = "snps,dw-apb-timer";
205 clocks = <&chip CLKID_CFG>;
206 clock-names = "timer";
211 compatible = "snps,dw-apb-timer";
213 clocks = <&chip CLKID_CFG>;
214 clock-names = "timer";
219 compatible = "snps,dw-apb-timer";
221 clocks = <&chip CLKID_CFG>;
222 clock-names = "timer";
227 compatible = "snps,dw-apb-timer";
229 clocks = <&chip CLKID_CFG>;
230 clock-names = "timer";
235 compatible = "snps,dw-apb-timer";
237 clocks = <&chip CLKID_CFG>;
238 clock-names = "timer";
243 compatible = "snps,dw-apb-timer";
245 clocks = <&chip CLKID_CFG>;
246 clock-names = "timer";
251 compatible = "snps,dw-apb-timer";
253 clocks = <&chip CLKID_CFG>;
254 clock-names = "timer";
258 aic: interrupt-controller@3800 {
259 compatible = "snps,dw-apb-ictl";
261 interrupt-controller;
262 #interrupt-cells = <1>;
263 interrupt-parent = <&gic>;
264 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
268 compatible = "snps,dw-apb-gpio";
269 reg = <0x5000 0x400>;
270 #address-cells = <1>;
274 compatible = "snps,dw-apb-gpio-port";
277 snps,nr-gpios = <32>;
283 compatible = "snps,dw-apb-gpio";
284 reg = <0xc000 0x400>;
285 #address-cells = <1>;
289 compatible = "snps,dw-apb-gpio-port";
292 snps,nr-gpios = <32>;
298 chip: chip-control@ea0000 {
299 compatible = "marvell,berlin2q-chip-ctrl";
301 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
303 clock-names = "refclk";
307 compatible = "simple-bus";
308 #address-cells = <1>;
311 ranges = <0 0xfc0000 0x10000>;
312 interrupt-parent = <&sic>;
315 compatible = "snps,dw-apb-uart";
316 reg = <0x9000 0x100>;
317 interrupt-parent = <&sic>;
321 pinctrl-0 = <&uart0_pmux>;
322 pinctrl-names = "default";
327 compatible = "snps,dw-apb-uart";
328 reg = <0xa000 0x100>;
329 interrupt-parent = <&sic>;
333 pinctrl-0 = <&uart1_pmux>;
334 pinctrl-names = "default";
338 sysctrl: pin-controller@d000 {
339 compatible = "marvell,berlin2q-system-ctrl";
340 reg = <0xd000 0x100>;
342 uart0_pmux: uart0-pmux {
347 uart1_pmux: uart1-pmux {
353 sic: interrupt-controller@e000 {
354 compatible = "snps,dw-apb-ictl";
356 interrupt-controller;
357 #interrupt-cells = <1>;
358 interrupt-parent = <&gic>;
359 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;