2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
15 * b) Permission is hereby granted, free of charge, to any person
16 * obtaining a copy of this software and associated documentation
17 * files (the "Software"), to deal in the Software without
18 * restriction, including without limitation the rights to use,
19 * copy, modify, merge, publish, distribute, sublicense, and/or
20 * sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following
24 * The above copyright notice and this permission notice shall be
25 * included in all copies or substantial portions of the Software.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
29 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
31 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
32 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
33 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
34 * OTHER DEALINGS IN THE SOFTWARE.
37 #include <dt-bindings/clock/berlin2q.h>
38 #include <dt-bindings/interrupt-controller/arm-gic.h>
40 #include "skeleton.dtsi"
43 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
44 compatible = "marvell,berlin2q", "marvell,berlin";
49 enable-method = "marvell,berlin-smp";
52 compatible = "arm,cortex-a9";
54 next-level-cache = <&l2>;
59 compatible = "arm,cortex-a9";
61 next-level-cache = <&l2>;
66 compatible = "arm,cortex-a9";
68 next-level-cache = <&l2>;
73 compatible = "arm,cortex-a9";
75 next-level-cache = <&l2>;
81 compatible = "fixed-clock";
83 clock-frequency = <25000000>;
87 compatible = "simple-bus";
91 ranges = <0 0xf7000000 0x1000000>;
92 interrupt-parent = <&gic>;
95 compatible = "arm,cortex-a9-pmu";
96 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
102 sdhci0: sdhci@ab0000 {
103 compatible = "mrvl,pxav3-mmc";
104 reg = <0xab0000 0x200>;
105 clocks = <&chip CLKID_SDIO1XIN>;
106 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
110 sdhci1: sdhci@ab0800 {
111 compatible = "mrvl,pxav3-mmc";
112 reg = <0xab0800 0x200>;
113 clocks = <&chip CLKID_SDIO1XIN>;
114 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
118 sdhci2: sdhci@ab1000 {
119 compatible = "mrvl,pxav3-mmc";
120 reg = <0xab1000 0x200>;
121 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
123 clock-names = "io", "core";
127 l2: l2-cache-controller@ac0000 {
128 compatible = "arm,pl310-cache";
129 reg = <0xac0000 0x1000>;
131 arm,data-latency = <2 2 2>;
132 arm,tag-latency = <2 2 2>;
135 scu: snoop-control-unit@ad0000 {
136 compatible = "arm,cortex-a9-scu";
137 reg = <0xad0000 0x58>;
141 compatible = "arm,cortex-a9-twd-timer";
142 reg = <0xad0600 0x20>;
143 clocks = <&chip CLKID_TWD>;
144 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
147 gic: interrupt-controller@ad1000 {
148 compatible = "arm,cortex-a9-gic";
149 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
150 interrupt-controller;
151 #interrupt-cells = <3>;
154 usb_phy2: phy@a2f400 {
155 compatible = "marvell,berlin2-usb-phy";
156 reg = <0xa2f400 0x128>;
158 resets = <&chip 0x104 14>;
163 compatible = "chipidea,usb2";
164 reg = <0xa30000 0x10000>;
165 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&chip CLKID_USB2>;
168 phy-names = "usb-phy";
172 usb_phy0: phy@b74000 {
173 compatible = "marvell,berlin2-usb-phy";
174 reg = <0xb74000 0x128>;
176 resets = <&chip 0x104 12>;
180 usb_phy1: phy@b78000 {
181 compatible = "marvell,berlin2-usb-phy";
182 reg = <0xb78000 0x128>;
184 resets = <&chip 0x104 13>;
188 eth0: ethernet@b90000 {
189 compatible = "marvell,pxa168-eth";
190 reg = <0xb90000 0x10000>;
191 clocks = <&chip CLKID_GETH0>;
192 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
193 /* set by bootloader */
194 local-mac-address = [00 00 00 00 00 00];
195 #address-cells = <1>;
197 phy-connection-type = "mii";
198 phy-handle = <ðphy0>;
201 ethphy0: ethernet-phy@0 {
207 compatible = "marvell,berlin-cpu-ctrl";
208 reg = <0xdd0000 0x10000>;
212 compatible = "simple-bus";
213 #address-cells = <1>;
216 ranges = <0 0xe80000 0x10000>;
217 interrupt-parent = <&aic>;
220 compatible = "snps,dw-apb-gpio";
221 reg = <0x0400 0x400>;
222 #address-cells = <1>;
226 compatible = "snps,dw-apb-gpio-port";
229 snps,nr-gpios = <32>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
238 compatible = "snps,dw-apb-gpio";
239 reg = <0x0800 0x400>;
240 #address-cells = <1>;
244 compatible = "snps,dw-apb-gpio-port";
247 snps,nr-gpios = <32>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
256 compatible = "snps,dw-apb-gpio";
257 reg = <0x0c00 0x400>;
258 #address-cells = <1>;
262 compatible = "snps,dw-apb-gpio-port";
265 snps,nr-gpios = <32>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
274 compatible = "snps,dw-apb-gpio";
275 reg = <0x1000 0x400>;
276 #address-cells = <1>;
280 compatible = "snps,dw-apb-gpio-port";
283 snps,nr-gpios = <32>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
292 compatible = "snps,designware-i2c";
293 #address-cells = <1>;
295 reg = <0x1400 0x100>;
296 interrupt-parent = <&aic>;
298 clocks = <&chip CLKID_CFG>;
299 pinctrl-0 = <&twsi0_pmux>;
300 pinctrl-names = "default";
305 compatible = "snps,designware-i2c";
306 #address-cells = <1>;
308 reg = <0x1800 0x100>;
309 interrupt-parent = <&aic>;
311 clocks = <&chip CLKID_CFG>;
312 pinctrl-0 = <&twsi1_pmux>;
313 pinctrl-names = "default";
318 compatible = "snps,dw-apb-timer";
320 clocks = <&chip CLKID_CFG>;
321 clock-names = "timer";
326 compatible = "snps,dw-apb-timer";
328 clocks = <&chip CLKID_CFG>;
329 clock-names = "timer";
333 compatible = "snps,dw-apb-timer";
335 clocks = <&chip CLKID_CFG>;
336 clock-names = "timer";
341 compatible = "snps,dw-apb-timer";
343 clocks = <&chip CLKID_CFG>;
344 clock-names = "timer";
349 compatible = "snps,dw-apb-timer";
351 clocks = <&chip CLKID_CFG>;
352 clock-names = "timer";
357 compatible = "snps,dw-apb-timer";
359 clocks = <&chip CLKID_CFG>;
360 clock-names = "timer";
365 compatible = "snps,dw-apb-timer";
367 clocks = <&chip CLKID_CFG>;
368 clock-names = "timer";
373 compatible = "snps,dw-apb-timer";
375 clocks = <&chip CLKID_CFG>;
376 clock-names = "timer";
380 aic: interrupt-controller@3800 {
381 compatible = "snps,dw-apb-ictl";
383 interrupt-controller;
384 #interrupt-cells = <1>;
385 interrupt-parent = <&gic>;
386 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
390 chip: chip-control@ea0000 {
391 compatible = "marvell,berlin2q-chip-ctrl";
394 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
396 clock-names = "refclk";
398 twsi0_pmux: twsi0-pmux {
403 twsi1_pmux: twsi1-pmux {
410 compatible = "marvell,berlin2q-ahci", "generic-ahci";
411 reg = <0xe90000 0x1000>;
412 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&chip CLKID_SATA>;
414 #address-cells = <1>;
419 phys = <&sata_phy 0>;
425 phys = <&sata_phy 1>;
430 sata_phy: phy@e900a0 {
431 compatible = "marvell,berlin2q-sata-phy";
432 reg = <0xe900a0 0x200>;
433 clocks = <&chip CLKID_SATA>;
434 #address-cells = <1>;
449 compatible = "chipidea,usb2";
450 reg = <0xed0000 0x10000>;
451 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&chip CLKID_USB0>;
454 phy-names = "usb-phy";
459 compatible = "chipidea,usb2";
460 reg = <0xee0000 0x10000>;
461 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&chip CLKID_USB1>;
464 phy-names = "usb-phy";
469 compatible = "simple-bus";
470 #address-cells = <1>;
473 ranges = <0 0xfc0000 0x10000>;
474 interrupt-parent = <&sic>;
476 sm_gpio1: gpio@5000 {
477 compatible = "snps,dw-apb-gpio";
478 reg = <0x5000 0x400>;
479 #address-cells = <1>;
483 compatible = "snps,dw-apb-gpio-port";
486 snps,nr-gpios = <32>;
492 compatible = "snps,designware-i2c";
493 #address-cells = <1>;
495 reg = <0x7000 0x100>;
496 interrupt-parent = <&sic>;
499 pinctrl-0 = <&twsi2_pmux>;
500 pinctrl-names = "default";
505 compatible = "snps,designware-i2c";
506 #address-cells = <1>;
508 reg = <0x8000 0x100>;
509 interrupt-parent = <&sic>;
512 pinctrl-0 = <&twsi3_pmux>;
513 pinctrl-names = "default";
518 compatible = "snps,dw-apb-uart";
519 reg = <0x9000 0x100>;
520 interrupt-parent = <&sic>;
524 pinctrl-0 = <&uart0_pmux>;
525 pinctrl-names = "default";
530 compatible = "snps,dw-apb-uart";
531 reg = <0xa000 0x100>;
532 interrupt-parent = <&sic>;
536 pinctrl-0 = <&uart1_pmux>;
537 pinctrl-names = "default";
541 sm_gpio0: gpio@c000 {
542 compatible = "snps,dw-apb-gpio";
543 reg = <0xc000 0x400>;
544 #address-cells = <1>;
548 compatible = "snps,dw-apb-gpio-port";
551 snps,nr-gpios = <32>;
556 sysctrl: pin-controller@d000 {
557 compatible = "marvell,berlin2q-system-ctrl";
558 reg = <0xd000 0x100>;
560 uart0_pmux: uart0-pmux {
565 uart1_pmux: uart1-pmux {
570 twsi2_pmux: twsi2-pmux {
575 twsi3_pmux: twsi3-pmux {
581 sic: interrupt-controller@e000 {
582 compatible = "snps,dw-apb-ictl";
584 interrupt-controller;
585 #interrupt-cells = <1>;
586 interrupt-parent = <&gic>;
587 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;